2 * ARM GICv3 support - common bits of emulated and KVM kernel model
4 * Copyright (c) 2012 Linaro Limited
5 * Copyright (c) 2015 Huawei.
6 * Written by Peter Maydell
7 * Extended to 64 cores by Shlomo Pongratz
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "hw/intc/arm_gicv3_common.h"
27 static void gicv3_pre_save(void *opaque
)
29 GICv3State
*s
= (GICv3State
*)opaque
;
30 ARMGICv3CommonClass
*c
= ARM_GICV3_COMMON_GET_CLASS(s
);
37 static int gicv3_post_load(void *opaque
, int version_id
)
39 GICv3State
*s
= (GICv3State
*)opaque
;
40 ARMGICv3CommonClass
*c
= ARM_GICV3_COMMON_GET_CLASS(s
);
48 static const VMStateDescription vmstate_gicv3
= {
51 .pre_save
= gicv3_pre_save
,
52 .post_load
= gicv3_post_load
,
55 void gicv3_init_irqs_and_mmio(GICv3State
*s
, qemu_irq_handler handler
,
56 const MemoryRegionOps
*ops
)
58 SysBusDevice
*sbd
= SYS_BUS_DEVICE(s
);
61 /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
62 * GPIO array layout is thus:
64 * [N..N+31] PPIs for CPU 0
65 * [N+32..N+63] PPIs for CPU 1
68 i
= s
->num_irq
- GIC_INTERNAL
+ GIC_INTERNAL
* s
->num_cpu
;
69 qdev_init_gpio_in(DEVICE(s
), handler
, i
);
71 s
->parent_irq
= g_malloc(s
->num_cpu
* sizeof(qemu_irq
));
72 s
->parent_fiq
= g_malloc(s
->num_cpu
* sizeof(qemu_irq
));
74 for (i
= 0; i
< s
->num_cpu
; i
++) {
75 sysbus_init_irq(sbd
, &s
->parent_irq
[i
]);
77 for (i
= 0; i
< s
->num_cpu
; i
++) {
78 sysbus_init_irq(sbd
, &s
->parent_fiq
[i
]);
81 memory_region_init_io(&s
->iomem_dist
, OBJECT(s
), ops
, s
,
82 "gicv3_dist", 0x10000);
83 memory_region_init_io(&s
->iomem_redist
, OBJECT(s
), ops
? &ops
[1] : NULL
, s
,
84 "gicv3_redist", 0x20000 * s
->num_cpu
);
86 sysbus_init_mmio(sbd
, &s
->iomem_dist
);
87 sysbus_init_mmio(sbd
, &s
->iomem_redist
);
90 static void arm_gicv3_common_realize(DeviceState
*dev
, Error
**errp
)
92 GICv3State
*s
= ARM_GICV3_COMMON(dev
);
94 /* revision property is actually reserved and currently used only in order
95 * to keep the interface compatible with GICv2 code, avoiding extra
96 * conditions. However, in future it could be used, for example, if we
99 if (s
->revision
!= 3) {
100 error_setg(errp
, "unsupported GIC revision %d", s
->revision
);
105 static void arm_gicv3_common_reset(DeviceState
*dev
)
110 static Property arm_gicv3_common_properties
[] = {
111 DEFINE_PROP_UINT32("num-cpu", GICv3State
, num_cpu
, 1),
112 DEFINE_PROP_UINT32("num-irq", GICv3State
, num_irq
, 32),
113 DEFINE_PROP_UINT32("revision", GICv3State
, revision
, 3),
114 DEFINE_PROP_BOOL("has-security-extensions", GICv3State
, security_extn
, 0),
115 DEFINE_PROP_END_OF_LIST(),
118 static void arm_gicv3_common_class_init(ObjectClass
*klass
, void *data
)
120 DeviceClass
*dc
= DEVICE_CLASS(klass
);
122 dc
->reset
= arm_gicv3_common_reset
;
123 dc
->realize
= arm_gicv3_common_realize
;
124 dc
->props
= arm_gicv3_common_properties
;
125 dc
->vmsd
= &vmstate_gicv3
;
128 static const TypeInfo arm_gicv3_common_type
= {
129 .name
= TYPE_ARM_GICV3_COMMON
,
130 .parent
= TYPE_SYS_BUS_DEVICE
,
131 .instance_size
= sizeof(GICv3State
),
132 .class_size
= sizeof(ARMGICv3CommonClass
),
133 .class_init
= arm_gicv3_common_class_init
,
137 static void register_types(void)
139 type_register_static(&arm_gicv3_common_type
);
142 type_init(register_types
)