2 * ARM Nested Vectored Interrupt Controller
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licensed under the GPL.
9 * The ARMv7M System controller is fairly tightly tied in with the
10 * NVIC. Much of that is also implemented here.
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
16 #include "hw/sysbus.h"
17 #include "qemu/timer.h"
18 #include "hw/intc/armv7m_nvic.h"
19 #include "target/arm/cpu.h"
20 #include "exec/exec-all.h"
22 #include "qemu/module.h"
25 /* IRQ number counting:
27 * the num-irq property counts the number of external IRQ lines
29 * NVICState::num_irq counts the total number of exceptions
30 * (external IRQs, the 15 internal exceptions including reset,
31 * and one for the unused exception number 0).
33 * NVIC_MAX_IRQ is the highest permitted number of external IRQ lines.
35 * NVIC_MAX_VECTORS is the highest permitted number of exceptions.
37 * Iterating through all exceptions should typically be done with
38 * for (i = 1; i < s->num_irq; i++) to avoid the unused slot 0.
40 * The external qemu_irq lines are the NVIC's external IRQ lines,
41 * so line 0 is exception 16.
43 * In the terminology of the architecture manual, "interrupts" are
44 * a subcategory of exception referring to the external interrupts
45 * (which are exception numbers NVIC_FIRST_IRQ and upward).
46 * For historical reasons QEMU tends to use "interrupt" and
47 * "exception" more or less interchangeably.
49 #define NVIC_FIRST_IRQ NVIC_INTERNAL_VECTORS
50 #define NVIC_MAX_IRQ (NVIC_MAX_VECTORS - NVIC_FIRST_IRQ)
52 /* Effective running priority of the CPU when no exception is active
53 * (higher than the highest possible priority value)
55 #define NVIC_NOEXC_PRIO 0x100
56 /* Maximum priority of non-secure exceptions when AIRCR.PRIS is set */
57 #define NVIC_NS_PRIO_LIMIT 0x80
59 static const uint8_t nvic_id
[] = {
60 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
63 static int nvic_pending_prio(NVICState
*s
)
65 /* return the group priority of the current pending interrupt,
66 * or NVIC_NOEXC_PRIO if no interrupt is pending
68 return s
->vectpending_prio
;
71 /* Return the value of the ISCR RETTOBASE bit:
72 * 1 if there is exactly one active exception
73 * 0 if there is more than one active exception
74 * UNKNOWN if there are no active exceptions (we choose 1,
75 * which matches the choice Cortex-M3 is documented as making).
77 * NB: some versions of the documentation talk about this
78 * counting "active exceptions other than the one shown by IPSR";
79 * this is only different in the obscure corner case where guest
80 * code has manually deactivated an exception and is about
81 * to fail an exception-return integrity check. The definition
82 * above is the one from the v8M ARM ARM and is also in line
83 * with the behaviour documented for the Cortex-M3.
85 static bool nvic_rettobase(NVICState
*s
)
88 bool check_sec
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
);
90 for (irq
= ARMV7M_EXCP_RESET
; irq
< s
->num_irq
; irq
++) {
91 if (s
->vectors
[irq
].active
||
92 (check_sec
&& irq
< NVIC_INTERNAL_VECTORS
&&
93 s
->sec_vectors
[irq
].active
)) {
104 /* Return the value of the ISCR ISRPENDING bit:
105 * 1 if an external interrupt is pending
106 * 0 if no external interrupt is pending
108 static bool nvic_isrpending(NVICState
*s
)
112 /* We can shortcut if the highest priority pending interrupt
113 * happens to be external or if there is nothing pending.
115 if (s
->vectpending
> NVIC_FIRST_IRQ
) {
118 if (s
->vectpending
== 0) {
122 for (irq
= NVIC_FIRST_IRQ
; irq
< s
->num_irq
; irq
++) {
123 if (s
->vectors
[irq
].pending
) {
130 static bool exc_is_banked(int exc
)
132 /* Return true if this is one of the limited set of exceptions which
133 * are banked (and thus have state in sec_vectors[])
135 return exc
== ARMV7M_EXCP_HARD
||
136 exc
== ARMV7M_EXCP_MEM
||
137 exc
== ARMV7M_EXCP_USAGE
||
138 exc
== ARMV7M_EXCP_SVC
||
139 exc
== ARMV7M_EXCP_PENDSV
||
140 exc
== ARMV7M_EXCP_SYSTICK
;
143 /* Return a mask word which clears the subpriority bits from
144 * a priority value for an M-profile exception, leaving only
145 * the group priority.
147 static inline uint32_t nvic_gprio_mask(NVICState
*s
, bool secure
)
149 return ~0U << (s
->prigroup
[secure
] + 1);
152 static bool exc_targets_secure(NVICState
*s
, int exc
)
154 /* Return true if this non-banked exception targets Secure state. */
155 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
159 if (exc
>= NVIC_FIRST_IRQ
) {
160 return !s
->itns
[exc
];
163 /* Function shouldn't be called for banked exceptions. */
164 assert(!exc_is_banked(exc
));
167 case ARMV7M_EXCP_NMI
:
168 case ARMV7M_EXCP_BUS
:
169 return !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
);
170 case ARMV7M_EXCP_SECURE
:
172 case ARMV7M_EXCP_DEBUG
:
173 /* TODO: controlled by DEMCR.SDME, which we don't yet implement */
176 /* reset, and reserved (unused) low exception numbers.
177 * We'll get called by code that loops through all the exception
178 * numbers, but it doesn't matter what we return here as these
179 * non-existent exceptions will never be pended or active.
185 static int exc_group_prio(NVICState
*s
, int rawprio
, bool targets_secure
)
187 /* Return the group priority for this exception, given its raw
188 * (group-and-subgroup) priority value and whether it is targeting
189 * secure state or not.
194 rawprio
&= nvic_gprio_mask(s
, targets_secure
);
195 /* AIRCR.PRIS causes us to squash all NS priorities into the
196 * lower half of the total range
198 if (!targets_secure
&&
199 (s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_PRIS_MASK
)) {
200 rawprio
= (rawprio
>> 1) + NVIC_NS_PRIO_LIMIT
;
205 /* Recompute vectpending and exception_prio for a CPU which implements
206 * the Security extension
208 static void nvic_recompute_state_secure(NVICState
*s
)
211 int pend_prio
= NVIC_NOEXC_PRIO
;
212 int active_prio
= NVIC_NOEXC_PRIO
;
214 bool pending_is_s_banked
= false;
215 int pend_subprio
= 0;
217 /* R_CQRV: precedence is by:
218 * - lowest group priority; if both the same then
219 * - lowest subpriority; if both the same then
220 * - lowest exception number; if both the same (ie banked) then
221 * - secure exception takes precedence
222 * Compare pseudocode RawExecutionPriority.
223 * Annoyingly, now we have two prigroup values (for S and NS)
224 * we can't do the loop comparison on raw priority values.
226 for (i
= 1; i
< s
->num_irq
; i
++) {
227 for (bank
= M_REG_S
; bank
>= M_REG_NS
; bank
--) {
232 if (bank
== M_REG_S
) {
233 if (!exc_is_banked(i
)) {
236 vec
= &s
->sec_vectors
[i
];
237 targets_secure
= true;
239 vec
= &s
->vectors
[i
];
240 targets_secure
= !exc_is_banked(i
) && exc_targets_secure(s
, i
);
243 prio
= exc_group_prio(s
, vec
->prio
, targets_secure
);
244 subprio
= vec
->prio
& ~nvic_gprio_mask(s
, targets_secure
);
245 if (vec
->enabled
&& vec
->pending
&&
246 ((prio
< pend_prio
) ||
247 (prio
== pend_prio
&& prio
>= 0 && subprio
< pend_subprio
))) {
249 pend_subprio
= subprio
;
251 pending_is_s_banked
= (bank
== M_REG_S
);
253 if (vec
->active
&& prio
< active_prio
) {
259 s
->vectpending_is_s_banked
= pending_is_s_banked
;
260 s
->vectpending
= pend_irq
;
261 s
->vectpending_prio
= pend_prio
;
262 s
->exception_prio
= active_prio
;
264 trace_nvic_recompute_state_secure(s
->vectpending
,
265 s
->vectpending_is_s_banked
,
270 /* Recompute vectpending and exception_prio */
271 static void nvic_recompute_state(NVICState
*s
)
274 int pend_prio
= NVIC_NOEXC_PRIO
;
275 int active_prio
= NVIC_NOEXC_PRIO
;
278 /* In theory we could write one function that handled both
279 * the "security extension present" and "not present"; however
280 * the security related changes significantly complicate the
281 * recomputation just by themselves and mixing both cases together
282 * would be even worse, so we retain a separate non-secure-only
283 * version for CPUs which don't implement the security extension.
285 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
286 nvic_recompute_state_secure(s
);
290 for (i
= 1; i
< s
->num_irq
; i
++) {
291 VecInfo
*vec
= &s
->vectors
[i
];
293 if (vec
->enabled
&& vec
->pending
&& vec
->prio
< pend_prio
) {
294 pend_prio
= vec
->prio
;
297 if (vec
->active
&& vec
->prio
< active_prio
) {
298 active_prio
= vec
->prio
;
302 if (active_prio
> 0) {
303 active_prio
&= nvic_gprio_mask(s
, false);
307 pend_prio
&= nvic_gprio_mask(s
, false);
310 s
->vectpending
= pend_irq
;
311 s
->vectpending_prio
= pend_prio
;
312 s
->exception_prio
= active_prio
;
314 trace_nvic_recompute_state(s
->vectpending
,
319 /* Return the current execution priority of the CPU
320 * (equivalent to the pseudocode ExecutionPriority function).
321 * This is a value between -2 (NMI priority) and NVIC_NOEXC_PRIO.
323 static inline int nvic_exec_prio(NVICState
*s
)
325 CPUARMState
*env
= &s
->cpu
->env
;
326 int running
= NVIC_NOEXC_PRIO
;
328 if (env
->v7m
.basepri
[M_REG_NS
] > 0) {
329 running
= exc_group_prio(s
, env
->v7m
.basepri
[M_REG_NS
], M_REG_NS
);
332 if (env
->v7m
.basepri
[M_REG_S
] > 0) {
333 int basepri
= exc_group_prio(s
, env
->v7m
.basepri
[M_REG_S
], M_REG_S
);
334 if (running
> basepri
) {
339 if (env
->v7m
.primask
[M_REG_NS
]) {
340 if (env
->v7m
.aircr
& R_V7M_AIRCR_PRIS_MASK
) {
341 if (running
> NVIC_NS_PRIO_LIMIT
) {
342 running
= NVIC_NS_PRIO_LIMIT
;
349 if (env
->v7m
.primask
[M_REG_S
]) {
353 if (env
->v7m
.faultmask
[M_REG_NS
]) {
354 if (env
->v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
357 if (env
->v7m
.aircr
& R_V7M_AIRCR_PRIS_MASK
) {
358 if (running
> NVIC_NS_PRIO_LIMIT
) {
359 running
= NVIC_NS_PRIO_LIMIT
;
367 if (env
->v7m
.faultmask
[M_REG_S
]) {
368 running
= (env
->v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) ? -3 : -1;
371 /* consider priority of active handler */
372 return MIN(running
, s
->exception_prio
);
375 bool armv7m_nvic_neg_prio_requested(void *opaque
, bool secure
)
377 /* Return true if the requested execution priority is negative
378 * for the specified security state, ie that security state
379 * has an active NMI or HardFault or has set its FAULTMASK.
380 * Note that this is not the same as whether the execution
381 * priority is actually negative (for instance AIRCR.PRIS may
382 * mean we don't allow FAULTMASK_NS to actually make the execution
383 * priority negative). Compare pseudocode IsReqExcPriNeg().
385 NVICState
*s
= opaque
;
387 if (s
->cpu
->env
.v7m
.faultmask
[secure
]) {
391 if (secure
? s
->sec_vectors
[ARMV7M_EXCP_HARD
].active
:
392 s
->vectors
[ARMV7M_EXCP_HARD
].active
) {
396 if (s
->vectors
[ARMV7M_EXCP_NMI
].active
&&
397 exc_targets_secure(s
, ARMV7M_EXCP_NMI
) == secure
) {
404 bool armv7m_nvic_can_take_pending_exception(void *opaque
)
406 NVICState
*s
= opaque
;
408 return nvic_exec_prio(s
) > nvic_pending_prio(s
);
411 int armv7m_nvic_raw_execution_priority(void *opaque
)
413 NVICState
*s
= opaque
;
415 return s
->exception_prio
;
418 /* caller must call nvic_irq_update() after this.
419 * secure indicates the bank to use for banked exceptions (we assert if
420 * we are passed secure=true for a non-banked exception).
422 static void set_prio(NVICState
*s
, unsigned irq
, bool secure
, uint8_t prio
)
424 assert(irq
> ARMV7M_EXCP_NMI
); /* only use for configurable prios */
425 assert(irq
< s
->num_irq
);
427 prio
&= MAKE_64BIT_MASK(8 - s
->num_prio_bits
, s
->num_prio_bits
);
430 assert(exc_is_banked(irq
));
431 s
->sec_vectors
[irq
].prio
= prio
;
433 s
->vectors
[irq
].prio
= prio
;
436 trace_nvic_set_prio(irq
, secure
, prio
);
439 /* Return the current raw priority register value.
440 * secure indicates the bank to use for banked exceptions (we assert if
441 * we are passed secure=true for a non-banked exception).
443 static int get_prio(NVICState
*s
, unsigned irq
, bool secure
)
445 assert(irq
> ARMV7M_EXCP_NMI
); /* only use for configurable prios */
446 assert(irq
< s
->num_irq
);
449 assert(exc_is_banked(irq
));
450 return s
->sec_vectors
[irq
].prio
;
452 return s
->vectors
[irq
].prio
;
456 /* Recompute state and assert irq line accordingly.
457 * Must be called after changes to:
458 * vec->active, vec->enabled, vec->pending or vec->prio for any vector
461 static void nvic_irq_update(NVICState
*s
)
466 nvic_recompute_state(s
);
467 pend_prio
= nvic_pending_prio(s
);
469 /* Raise NVIC output if this IRQ would be taken, except that we
470 * ignore the effects of the BASEPRI, FAULTMASK and PRIMASK (which
471 * will be checked for in arm_v7m_cpu_exec_interrupt()); changes
472 * to those CPU registers don't cause us to recalculate the NVIC
475 lvl
= (pend_prio
< s
->exception_prio
);
476 trace_nvic_irq_update(s
->vectpending
, pend_prio
, s
->exception_prio
, lvl
);
477 qemu_set_irq(s
->excpout
, lvl
);
481 * armv7m_nvic_clear_pending: mark the specified exception as not pending
483 * @irq: the exception number to mark as not pending
484 * @secure: false for non-banked exceptions or for the nonsecure
485 * version of a banked exception, true for the secure version of a banked
488 * Marks the specified exception as not pending. Note that we will assert()
489 * if @secure is true and @irq does not specify one of the fixed set
490 * of architecturally banked exceptions.
492 static void armv7m_nvic_clear_pending(void *opaque
, int irq
, bool secure
)
494 NVICState
*s
= (NVICState
*)opaque
;
497 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
500 assert(exc_is_banked(irq
));
501 vec
= &s
->sec_vectors
[irq
];
503 vec
= &s
->vectors
[irq
];
505 trace_nvic_clear_pending(irq
, secure
, vec
->enabled
, vec
->prio
);
512 static void do_armv7m_nvic_set_pending(void *opaque
, int irq
, bool secure
,
515 /* Pend an exception, including possibly escalating it to HardFault.
517 * This function handles both "normal" pending of interrupts and
518 * exceptions, and also derived exceptions (ones which occur as
519 * a result of trying to take some other exception).
521 * If derived == true, the caller guarantees that we are part way through
522 * trying to take an exception (but have not yet called
523 * armv7m_nvic_acknowledge_irq() to make it active), and so:
524 * - s->vectpending is the "original exception" we were trying to take
525 * - irq is the "derived exception"
526 * - nvic_exec_prio(s) gives the priority before exception entry
527 * Here we handle the prioritization logic which the pseudocode puts
528 * in the DerivedLateArrival() function.
531 NVICState
*s
= (NVICState
*)opaque
;
532 bool banked
= exc_is_banked(irq
);
536 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
537 assert(!secure
|| banked
);
539 vec
= (banked
&& secure
) ? &s
->sec_vectors
[irq
] : &s
->vectors
[irq
];
541 targets_secure
= banked
? secure
: exc_targets_secure(s
, irq
);
543 trace_nvic_set_pending(irq
, secure
, targets_secure
,
544 derived
, vec
->enabled
, vec
->prio
);
547 /* Derived exceptions are always synchronous. */
548 assert(irq
>= ARMV7M_EXCP_HARD
&& irq
< ARMV7M_EXCP_PENDSV
);
550 if (irq
== ARMV7M_EXCP_DEBUG
&&
551 exc_group_prio(s
, vec
->prio
, secure
) >= nvic_exec_prio(s
)) {
552 /* DebugMonitorFault, but its priority is lower than the
553 * preempted exception priority: just ignore it.
558 if (irq
== ARMV7M_EXCP_HARD
&& vec
->prio
>= s
->vectpending_prio
) {
559 /* If this is a terminal exception (one which means we cannot
560 * take the original exception, like a failure to read its
561 * vector table entry), then we must take the derived exception.
562 * If the derived exception can't take priority over the
563 * original exception, then we go into Lockup.
565 * For QEMU, we rely on the fact that a derived exception is
566 * terminal if and only if it's reported to us as HardFault,
567 * which saves having to have an extra argument is_terminal
568 * that we'd only use in one place.
570 cpu_abort(&s
->cpu
->parent_obj
,
571 "Lockup: can't take terminal derived exception "
572 "(original exception priority %d)\n",
573 s
->vectpending_prio
);
575 /* We now continue with the same code as for a normal pending
576 * exception, which will cause us to pend the derived exception.
577 * We'll then take either the original or the derived exception
578 * based on which is higher priority by the usual mechanism
579 * for selecting the highest priority pending interrupt.
583 if (irq
>= ARMV7M_EXCP_HARD
&& irq
< ARMV7M_EXCP_PENDSV
) {
584 /* If a synchronous exception is pending then it may be
585 * escalated to HardFault if:
586 * * it is equal or lower priority to current execution
588 * (ie we need to take it immediately but we can't do so).
589 * Asynchronous exceptions (and interrupts) simply remain pending.
591 * For QEMU, we don't have any imprecise (asynchronous) faults,
592 * so we can assume that PREFETCH_ABORT and DATA_ABORT are always
594 * Debug exceptions are awkward because only Debug exceptions
595 * resulting from the BKPT instruction should be escalated,
596 * but we don't currently implement any Debug exceptions other
597 * than those that result from BKPT, so we treat all debug exceptions
598 * as needing escalation.
600 * This all means we can identify whether to escalate based only on
601 * the exception number and don't (yet) need the caller to explicitly
602 * tell us whether this exception is synchronous or not.
604 int running
= nvic_exec_prio(s
);
605 bool escalate
= false;
607 if (exc_group_prio(s
, vec
->prio
, secure
) >= running
) {
608 trace_nvic_escalate_prio(irq
, vec
->prio
, running
);
610 } else if (!vec
->enabled
) {
611 trace_nvic_escalate_disabled(irq
);
617 /* We need to escalate this exception to a synchronous HardFault.
618 * If BFHFNMINS is set then we escalate to the banked HF for
619 * the target security state of the original exception; otherwise
620 * we take a Secure HardFault.
622 irq
= ARMV7M_EXCP_HARD
;
623 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
) &&
625 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
))) {
626 vec
= &s
->sec_vectors
[irq
];
628 vec
= &s
->vectors
[irq
];
630 if (running
<= vec
->prio
) {
631 /* We want to escalate to HardFault but we can't take the
632 * synchronous HardFault at this point either. This is a
633 * Lockup condition due to a guest bug. We don't model
634 * Lockup, so report via cpu_abort() instead.
636 cpu_abort(&s
->cpu
->parent_obj
,
637 "Lockup: can't escalate %d to HardFault "
638 "(current priority %d)\n", irq
, running
);
641 /* HF may be banked but there is only one shared HFSR */
642 s
->cpu
->env
.v7m
.hfsr
|= R_V7M_HFSR_FORCED_MASK
;
652 void armv7m_nvic_set_pending(void *opaque
, int irq
, bool secure
)
654 do_armv7m_nvic_set_pending(opaque
, irq
, secure
, false);
657 void armv7m_nvic_set_pending_derived(void *opaque
, int irq
, bool secure
)
659 do_armv7m_nvic_set_pending(opaque
, irq
, secure
, true);
662 void armv7m_nvic_set_pending_lazyfp(void *opaque
, int irq
, bool secure
)
665 * Pend an exception during lazy FP stacking. This differs
666 * from the usual exception pending because the logic for
667 * whether we should escalate depends on the saved context
668 * in the FPCCR register, not on the current state of the CPU/NVIC.
670 NVICState
*s
= (NVICState
*)opaque
;
671 bool banked
= exc_is_banked(irq
);
674 bool escalate
= false;
676 * We will only look at bits in fpccr if this is a banked exception
677 * (in which case 'secure' tells us whether it is the S or NS version).
678 * All the bits for the non-banked exceptions are in fpccr_s.
680 uint32_t fpccr_s
= s
->cpu
->env
.v7m
.fpccr
[M_REG_S
];
681 uint32_t fpccr
= s
->cpu
->env
.v7m
.fpccr
[secure
];
683 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
684 assert(!secure
|| banked
);
686 vec
= (banked
&& secure
) ? &s
->sec_vectors
[irq
] : &s
->vectors
[irq
];
688 targets_secure
= banked
? secure
: exc_targets_secure(s
, irq
);
691 case ARMV7M_EXCP_DEBUG
:
692 if (!(fpccr_s
& R_V7M_FPCCR_MONRDY_MASK
)) {
693 /* Ignore DebugMonitor exception */
697 case ARMV7M_EXCP_MEM
:
698 escalate
= !(fpccr
& R_V7M_FPCCR_MMRDY_MASK
);
700 case ARMV7M_EXCP_USAGE
:
701 escalate
= !(fpccr
& R_V7M_FPCCR_UFRDY_MASK
);
703 case ARMV7M_EXCP_BUS
:
704 escalate
= !(fpccr_s
& R_V7M_FPCCR_BFRDY_MASK
);
706 case ARMV7M_EXCP_SECURE
:
707 escalate
= !(fpccr_s
& R_V7M_FPCCR_SFRDY_MASK
);
710 g_assert_not_reached();
715 * Escalate to HardFault: faults that initially targeted Secure
716 * continue to do so, even if HF normally targets NonSecure.
718 irq
= ARMV7M_EXCP_HARD
;
719 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
) &&
721 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
))) {
722 vec
= &s
->sec_vectors
[irq
];
724 vec
= &s
->vectors
[irq
];
729 nvic_exec_prio(s
) <= exc_group_prio(s
, vec
->prio
, secure
)) {
730 if (!(fpccr_s
& R_V7M_FPCCR_HFRDY_MASK
)) {
732 * We want to escalate to HardFault but the context the
733 * FP state belongs to prevents the exception pre-empting.
735 cpu_abort(&s
->cpu
->parent_obj
,
736 "Lockup: can't escalate to HardFault during "
737 "lazy FP register stacking\n");
742 s
->cpu
->env
.v7m
.hfsr
|= R_V7M_HFSR_FORCED_MASK
;
747 * We do not call nvic_irq_update(), because we know our caller
748 * is going to handle causing us to take the exception by
749 * raising EXCP_LAZYFP, so raising the IRQ line would be
750 * pointless extra work. We just need to recompute the
751 * priorities so that armv7m_nvic_can_take_pending_exception()
752 * returns the right answer.
754 nvic_recompute_state(s
);
758 /* Make pending IRQ active. */
759 void armv7m_nvic_acknowledge_irq(void *opaque
)
761 NVICState
*s
= (NVICState
*)opaque
;
762 CPUARMState
*env
= &s
->cpu
->env
;
763 const int pending
= s
->vectpending
;
764 const int running
= nvic_exec_prio(s
);
767 assert(pending
> ARMV7M_EXCP_RESET
&& pending
< s
->num_irq
);
769 if (s
->vectpending_is_s_banked
) {
770 vec
= &s
->sec_vectors
[pending
];
772 vec
= &s
->vectors
[pending
];
775 assert(vec
->enabled
);
776 assert(vec
->pending
);
778 assert(s
->vectpending_prio
< running
);
780 trace_nvic_acknowledge_irq(pending
, s
->vectpending_prio
);
785 write_v7m_exception(env
, s
->vectpending
);
790 void armv7m_nvic_get_pending_irq_info(void *opaque
,
791 int *pirq
, bool *ptargets_secure
)
793 NVICState
*s
= (NVICState
*)opaque
;
794 const int pending
= s
->vectpending
;
797 assert(pending
> ARMV7M_EXCP_RESET
&& pending
< s
->num_irq
);
799 if (s
->vectpending_is_s_banked
) {
800 targets_secure
= true;
802 targets_secure
= !exc_is_banked(pending
) &&
803 exc_targets_secure(s
, pending
);
806 trace_nvic_get_pending_irq_info(pending
, targets_secure
);
808 *ptargets_secure
= targets_secure
;
812 int armv7m_nvic_complete_irq(void *opaque
, int irq
, bool secure
)
814 NVICState
*s
= (NVICState
*)opaque
;
818 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
821 * For negative priorities, v8M will forcibly deactivate the appropriate
822 * NMI or HardFault regardless of what interrupt we're being asked to
823 * deactivate (compare the DeActivate() pseudocode). This is a guard
824 * against software returning from NMI or HardFault with a corrupted
825 * IPSR and leaving the CPU in a negative-priority state.
826 * v7M does not do this, but simply deactivates the requested interrupt.
828 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
)) {
829 switch (armv7m_nvic_raw_execution_priority(s
)) {
831 if (s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
832 vec
= &s
->vectors
[ARMV7M_EXCP_HARD
];
834 vec
= &s
->sec_vectors
[ARMV7M_EXCP_HARD
];
838 vec
= &s
->vectors
[ARMV7M_EXCP_NMI
];
841 vec
= &s
->sec_vectors
[ARMV7M_EXCP_HARD
];
849 if (secure
&& exc_is_banked(irq
)) {
850 vec
= &s
->sec_vectors
[irq
];
852 vec
= &s
->vectors
[irq
];
856 trace_nvic_complete_irq(irq
, secure
);
859 /* Tell the caller this was an illegal exception return */
863 ret
= nvic_rettobase(s
);
867 /* Re-pend the exception if it's still held high; only
868 * happens for extenal IRQs
870 assert(irq
>= NVIC_FIRST_IRQ
);
879 bool armv7m_nvic_get_ready_status(void *opaque
, int irq
, bool secure
)
882 * Return whether an exception is "ready", i.e. it is enabled and is
883 * configured at a priority which would allow it to interrupt the
884 * current execution priority.
886 * irq and secure have the same semantics as for armv7m_nvic_set_pending():
887 * for non-banked exceptions secure is always false; for banked exceptions
888 * it indicates which of the exceptions is required.
890 NVICState
*s
= (NVICState
*)opaque
;
891 bool banked
= exc_is_banked(irq
);
893 int running
= nvic_exec_prio(s
);
895 assert(irq
> ARMV7M_EXCP_RESET
&& irq
< s
->num_irq
);
896 assert(!secure
|| banked
);
899 * HardFault is an odd special case: we always check against -1,
900 * even if we're secure and HardFault has priority -3; we never
901 * need to check for enabled state.
903 if (irq
== ARMV7M_EXCP_HARD
) {
907 vec
= (banked
&& secure
) ? &s
->sec_vectors
[irq
] : &s
->vectors
[irq
];
909 return vec
->enabled
&&
910 exc_group_prio(s
, vec
->prio
, secure
) < running
;
913 /* callback when external interrupt line is changed */
914 static void set_irq_level(void *opaque
, int n
, int level
)
916 NVICState
*s
= opaque
;
921 assert(n
>= NVIC_FIRST_IRQ
&& n
< s
->num_irq
);
923 trace_nvic_set_irq_level(n
, level
);
925 /* The pending status of an external interrupt is
926 * latched on rising edge and exception handler return.
928 * Pulsing the IRQ will always run the handler
929 * once, and the handler will re-run until the
930 * level is low when the handler completes.
932 vec
= &s
->vectors
[n
];
933 if (level
!= vec
->level
) {
936 armv7m_nvic_set_pending(s
, n
, false);
941 /* callback when external NMI line is changed */
942 static void nvic_nmi_trigger(void *opaque
, int n
, int level
)
944 NVICState
*s
= opaque
;
946 trace_nvic_set_nmi_level(level
);
949 * The architecture doesn't specify whether NMI should share
950 * the normal-interrupt behaviour of being resampled on
951 * exception handler return. We choose not to, so just
952 * set NMI pending here and don't track the current level.
955 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_NMI
, false);
959 static uint32_t nvic_readl(NVICState
*s
, uint32_t offset
, MemTxAttrs attrs
)
961 ARMCPU
*cpu
= s
->cpu
;
965 case 4: /* Interrupt Control Type. */
966 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
969 return ((s
->num_irq
- NVIC_FIRST_IRQ
) / 32) - 1;
970 case 0xc: /* CPPWR */
971 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
974 /* We make the IMPDEF choice that nothing can ever go into a
975 * non-retentive power state, which allows us to RAZ/WI this.
978 case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
980 int startvec
= 8 * (offset
- 0x380) + NVIC_FIRST_IRQ
;
983 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
990 for (i
= 0; i
< 32 && startvec
+ i
< s
->num_irq
; i
++) {
991 if (s
->itns
[startvec
+ i
]) {
997 case 0xd00: /* CPUID Base. */
999 case 0xd04: /* Interrupt Control State (ICSR) */
1001 val
= cpu
->env
.v7m
.exception
;
1003 val
|= (s
->vectpending
& 0xff) << 12;
1004 /* ISRPENDING - set if any external IRQ is pending */
1005 if (nvic_isrpending(s
)) {
1008 /* RETTOBASE - set if only one handler is active */
1009 if (nvic_rettobase(s
)) {
1014 if (s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].pending
) {
1018 if (s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].pending
) {
1023 if (s
->vectors
[ARMV7M_EXCP_SYSTICK
].pending
) {
1027 if (s
->vectors
[ARMV7M_EXCP_PENDSV
].pending
) {
1032 if ((attrs
.secure
|| (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
))
1033 && s
->vectors
[ARMV7M_EXCP_NMI
].pending
) {
1036 /* ISRPREEMPT: RES0 when halting debug not implemented */
1037 /* STTNS: RES0 for the Main Extension */
1039 case 0xd08: /* Vector Table Offset. */
1040 return cpu
->env
.v7m
.vecbase
[attrs
.secure
];
1041 case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
1042 val
= 0xfa050000 | (s
->prigroup
[attrs
.secure
] << 8);
1044 /* s->aircr stores PRIS, BFHFNMINS, SYSRESETREQS */
1045 val
|= cpu
->env
.v7m
.aircr
;
1047 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1048 /* BFHFNMINS is R/O from NS; other bits are RAZ/WI. If
1049 * security isn't supported then BFHFNMINS is RAO (and
1050 * the bit in env.v7m.aircr is always set).
1052 val
|= cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
;
1056 case 0xd10: /* System Control. */
1057 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1060 return cpu
->env
.v7m
.scr
[attrs
.secure
];
1061 case 0xd14: /* Configuration Control. */
1062 /* The BFHFNMIGN bit is the only non-banked bit; we
1063 * keep it in the non-secure copy of the register.
1065 val
= cpu
->env
.v7m
.ccr
[attrs
.secure
];
1066 val
|= cpu
->env
.v7m
.ccr
[M_REG_NS
] & R_V7M_CCR_BFHFNMIGN_MASK
;
1068 case 0xd24: /* System Handler Control and State (SHCSR) */
1069 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1074 if (s
->sec_vectors
[ARMV7M_EXCP_MEM
].active
) {
1077 if (s
->sec_vectors
[ARMV7M_EXCP_HARD
].active
) {
1080 if (s
->sec_vectors
[ARMV7M_EXCP_USAGE
].active
) {
1083 if (s
->sec_vectors
[ARMV7M_EXCP_SVC
].active
) {
1086 if (s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].active
) {
1089 if (s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].active
) {
1092 if (s
->sec_vectors
[ARMV7M_EXCP_USAGE
].pending
) {
1095 if (s
->sec_vectors
[ARMV7M_EXCP_MEM
].pending
) {
1098 if (s
->sec_vectors
[ARMV7M_EXCP_SVC
].pending
) {
1101 if (s
->sec_vectors
[ARMV7M_EXCP_MEM
].enabled
) {
1104 if (s
->sec_vectors
[ARMV7M_EXCP_USAGE
].enabled
) {
1107 if (s
->sec_vectors
[ARMV7M_EXCP_HARD
].pending
) {
1110 /* SecureFault is not banked but is always RAZ/WI to NS */
1111 if (s
->vectors
[ARMV7M_EXCP_SECURE
].active
) {
1114 if (s
->vectors
[ARMV7M_EXCP_SECURE
].enabled
) {
1117 if (s
->vectors
[ARMV7M_EXCP_SECURE
].pending
) {
1121 if (s
->vectors
[ARMV7M_EXCP_MEM
].active
) {
1124 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1125 /* HARDFAULTACT, HARDFAULTPENDED not present in v7M */
1126 if (s
->vectors
[ARMV7M_EXCP_HARD
].active
) {
1129 if (s
->vectors
[ARMV7M_EXCP_HARD
].pending
) {
1133 if (s
->vectors
[ARMV7M_EXCP_USAGE
].active
) {
1136 if (s
->vectors
[ARMV7M_EXCP_SVC
].active
) {
1139 if (s
->vectors
[ARMV7M_EXCP_PENDSV
].active
) {
1142 if (s
->vectors
[ARMV7M_EXCP_SYSTICK
].active
) {
1145 if (s
->vectors
[ARMV7M_EXCP_USAGE
].pending
) {
1148 if (s
->vectors
[ARMV7M_EXCP_MEM
].pending
) {
1151 if (s
->vectors
[ARMV7M_EXCP_SVC
].pending
) {
1154 if (s
->vectors
[ARMV7M_EXCP_MEM
].enabled
) {
1157 if (s
->vectors
[ARMV7M_EXCP_USAGE
].enabled
) {
1161 if (attrs
.secure
|| (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
1162 if (s
->vectors
[ARMV7M_EXCP_BUS
].active
) {
1165 if (s
->vectors
[ARMV7M_EXCP_BUS
].pending
) {
1168 if (s
->vectors
[ARMV7M_EXCP_BUS
].enabled
) {
1171 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
) &&
1172 s
->vectors
[ARMV7M_EXCP_NMI
].active
) {
1173 /* NMIACT is not present in v7M */
1178 /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
1179 if (s
->vectors
[ARMV7M_EXCP_DEBUG
].active
) {
1183 case 0xd2c: /* Hard Fault Status. */
1184 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1187 return cpu
->env
.v7m
.hfsr
;
1188 case 0xd30: /* Debug Fault Status. */
1189 return cpu
->env
.v7m
.dfsr
;
1190 case 0xd34: /* MMFAR MemManage Fault Address */
1191 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1194 return cpu
->env
.v7m
.mmfar
[attrs
.secure
];
1195 case 0xd38: /* Bus Fault Address. */
1196 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1199 if (!attrs
.secure
&&
1200 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
1203 return cpu
->env
.v7m
.bfar
;
1204 case 0xd3c: /* Aux Fault Status. */
1205 /* TODO: Implement fault status registers. */
1206 qemu_log_mask(LOG_UNIMP
,
1207 "Aux Fault status registers unimplemented\n");
1209 case 0xd40: /* PFR0. */
1210 return cpu
->id_pfr0
;
1211 case 0xd44: /* PFR1. */
1212 return cpu
->id_pfr1
;
1213 case 0xd48: /* DFR0. */
1214 return cpu
->id_dfr0
;
1215 case 0xd4c: /* AFR0. */
1216 return cpu
->id_afr0
;
1217 case 0xd50: /* MMFR0. */
1218 return cpu
->id_mmfr0
;
1219 case 0xd54: /* MMFR1. */
1220 return cpu
->id_mmfr1
;
1221 case 0xd58: /* MMFR2. */
1222 return cpu
->id_mmfr2
;
1223 case 0xd5c: /* MMFR3. */
1224 return cpu
->id_mmfr3
;
1225 case 0xd60: /* ISAR0. */
1226 return cpu
->isar
.id_isar0
;
1227 case 0xd64: /* ISAR1. */
1228 return cpu
->isar
.id_isar1
;
1229 case 0xd68: /* ISAR2. */
1230 return cpu
->isar
.id_isar2
;
1231 case 0xd6c: /* ISAR3. */
1232 return cpu
->isar
.id_isar3
;
1233 case 0xd70: /* ISAR4. */
1234 return cpu
->isar
.id_isar4
;
1235 case 0xd74: /* ISAR5. */
1236 return cpu
->isar
.id_isar5
;
1237 case 0xd78: /* CLIDR */
1239 case 0xd7c: /* CTR */
1241 case 0xd80: /* CSSIDR */
1243 int idx
= cpu
->env
.v7m
.csselr
[attrs
.secure
] & R_V7M_CSSELR_INDEX_MASK
;
1244 return cpu
->ccsidr
[idx
];
1246 case 0xd84: /* CSSELR */
1247 return cpu
->env
.v7m
.csselr
[attrs
.secure
];
1248 case 0xd88: /* CPACR */
1249 if (!arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1252 return cpu
->env
.v7m
.cpacr
[attrs
.secure
];
1253 case 0xd8c: /* NSACR */
1254 if (!attrs
.secure
|| !arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1257 return cpu
->env
.v7m
.nsacr
;
1258 /* TODO: Implement debug registers. */
1259 case 0xd90: /* MPU_TYPE */
1260 /* Unified MPU; if the MPU is not present this value is zero */
1261 return cpu
->pmsav7_dregion
<< 8;
1263 case 0xd94: /* MPU_CTRL */
1264 return cpu
->env
.v7m
.mpu_ctrl
[attrs
.secure
];
1265 case 0xd98: /* MPU_RNR */
1266 return cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1267 case 0xd9c: /* MPU_RBAR */
1268 case 0xda4: /* MPU_RBAR_A1 */
1269 case 0xdac: /* MPU_RBAR_A2 */
1270 case 0xdb4: /* MPU_RBAR_A3 */
1272 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1274 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1275 /* PMSAv8M handling of the aliases is different from v7M:
1276 * aliases A1, A2, A3 override the low two bits of the region
1277 * number in MPU_RNR, and there is no 'region' field in the
1280 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
1282 region
= deposit32(region
, 0, 2, aliasno
);
1284 if (region
>= cpu
->pmsav7_dregion
) {
1287 return cpu
->env
.pmsav8
.rbar
[attrs
.secure
][region
];
1290 if (region
>= cpu
->pmsav7_dregion
) {
1293 return (cpu
->env
.pmsav7
.drbar
[region
] & ~0x1f) | (region
& 0xf);
1295 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
1296 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
1297 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
1298 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
1300 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1302 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1303 /* PMSAv8M handling of the aliases is different from v7M:
1304 * aliases A1, A2, A3 override the low two bits of the region
1305 * number in MPU_RNR.
1307 int aliasno
= (offset
- 0xda0) / 8; /* 0..3 */
1309 region
= deposit32(region
, 0, 2, aliasno
);
1311 if (region
>= cpu
->pmsav7_dregion
) {
1314 return cpu
->env
.pmsav8
.rlar
[attrs
.secure
][region
];
1317 if (region
>= cpu
->pmsav7_dregion
) {
1320 return ((cpu
->env
.pmsav7
.dracr
[region
] & 0xffff) << 16) |
1321 (cpu
->env
.pmsav7
.drsr
[region
] & 0xffff);
1323 case 0xdc0: /* MPU_MAIR0 */
1324 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1327 return cpu
->env
.pmsav8
.mair0
[attrs
.secure
];
1328 case 0xdc4: /* MPU_MAIR1 */
1329 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1332 return cpu
->env
.pmsav8
.mair1
[attrs
.secure
];
1333 case 0xdd0: /* SAU_CTRL */
1334 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1337 if (!attrs
.secure
) {
1340 return cpu
->env
.sau
.ctrl
;
1341 case 0xdd4: /* SAU_TYPE */
1342 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1345 if (!attrs
.secure
) {
1348 return cpu
->sau_sregion
;
1349 case 0xdd8: /* SAU_RNR */
1350 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1353 if (!attrs
.secure
) {
1356 return cpu
->env
.sau
.rnr
;
1357 case 0xddc: /* SAU_RBAR */
1359 int region
= cpu
->env
.sau
.rnr
;
1361 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1364 if (!attrs
.secure
) {
1367 if (region
>= cpu
->sau_sregion
) {
1370 return cpu
->env
.sau
.rbar
[region
];
1372 case 0xde0: /* SAU_RLAR */
1374 int region
= cpu
->env
.sau
.rnr
;
1376 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1379 if (!attrs
.secure
) {
1382 if (region
>= cpu
->sau_sregion
) {
1385 return cpu
->env
.sau
.rlar
[region
];
1387 case 0xde4: /* SFSR */
1388 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1391 if (!attrs
.secure
) {
1394 return cpu
->env
.v7m
.sfsr
;
1395 case 0xde8: /* SFAR */
1396 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1399 if (!attrs
.secure
) {
1402 return cpu
->env
.v7m
.sfar
;
1403 case 0xf34: /* FPCCR */
1404 if (!arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1408 return cpu
->env
.v7m
.fpccr
[M_REG_S
];
1411 * NS can read LSPEN, CLRONRET and MONRDY. It can read
1412 * BFRDY and HFRDY if AIRCR.BFHFNMINS != 0;
1413 * other non-banked bits RAZ.
1414 * TODO: MONRDY should RAZ/WI if DEMCR.SDME is set.
1416 uint32_t value
= cpu
->env
.v7m
.fpccr
[M_REG_S
];
1417 uint32_t mask
= R_V7M_FPCCR_LSPEN_MASK
|
1418 R_V7M_FPCCR_CLRONRET_MASK
|
1419 R_V7M_FPCCR_MONRDY_MASK
;
1421 if (s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
1422 mask
|= R_V7M_FPCCR_BFRDY_MASK
| R_V7M_FPCCR_HFRDY_MASK
;
1427 value
|= cpu
->env
.v7m
.fpccr
[M_REG_NS
];
1430 case 0xf38: /* FPCAR */
1431 if (!arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1434 return cpu
->env
.v7m
.fpcar
[attrs
.secure
];
1435 case 0xf3c: /* FPDSCR */
1436 if (!arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1439 return cpu
->env
.v7m
.fpdscr
[attrs
.secure
];
1440 case 0xf40: /* MVFR0 */
1441 return cpu
->isar
.mvfr0
;
1442 case 0xf44: /* MVFR1 */
1443 return cpu
->isar
.mvfr1
;
1444 case 0xf48: /* MVFR2 */
1445 return cpu
->isar
.mvfr2
;
1448 qemu_log_mask(LOG_GUEST_ERROR
, "NVIC: Bad read offset 0x%x\n", offset
);
1453 static void nvic_writel(NVICState
*s
, uint32_t offset
, uint32_t value
,
1456 ARMCPU
*cpu
= s
->cpu
;
1459 case 0xc: /* CPPWR */
1460 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1463 /* Make the IMPDEF choice to RAZ/WI this. */
1465 case 0x380 ... 0x3bf: /* NVIC_ITNS<n> */
1467 int startvec
= 8 * (offset
- 0x380) + NVIC_FIRST_IRQ
;
1470 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1473 if (!attrs
.secure
) {
1476 for (i
= 0; i
< 32 && startvec
+ i
< s
->num_irq
; i
++) {
1477 s
->itns
[startvec
+ i
] = (value
>> i
) & 1;
1482 case 0xd04: /* Interrupt Control State (ICSR) */
1483 if (attrs
.secure
|| cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
1484 if (value
& (1 << 31)) {
1485 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_NMI
, false);
1486 } else if (value
& (1 << 30) &&
1487 arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1488 /* PENDNMICLR didn't exist in v7M */
1489 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_NMI
, false);
1492 if (value
& (1 << 28)) {
1493 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_PENDSV
, attrs
.secure
);
1494 } else if (value
& (1 << 27)) {
1495 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_PENDSV
, attrs
.secure
);
1497 if (value
& (1 << 26)) {
1498 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_SYSTICK
, attrs
.secure
);
1499 } else if (value
& (1 << 25)) {
1500 armv7m_nvic_clear_pending(s
, ARMV7M_EXCP_SYSTICK
, attrs
.secure
);
1503 case 0xd08: /* Vector Table Offset. */
1504 cpu
->env
.v7m
.vecbase
[attrs
.secure
] = value
& 0xffffff80;
1506 case 0xd0c: /* Application Interrupt/Reset Control (AIRCR) */
1507 if ((value
>> R_V7M_AIRCR_VECTKEY_SHIFT
) == 0x05fa) {
1508 if (value
& R_V7M_AIRCR_SYSRESETREQ_MASK
) {
1510 !(cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_SYSRESETREQS_MASK
)) {
1511 qemu_irq_pulse(s
->sysresetreq
);
1514 if (value
& R_V7M_AIRCR_VECTCLRACTIVE_MASK
) {
1515 qemu_log_mask(LOG_GUEST_ERROR
,
1516 "Setting VECTCLRACTIVE when not in DEBUG mode "
1517 "is UNPREDICTABLE\n");
1519 if (value
& R_V7M_AIRCR_VECTRESET_MASK
) {
1520 /* NB: this bit is RES0 in v8M */
1521 qemu_log_mask(LOG_GUEST_ERROR
,
1522 "Setting VECTRESET when not in DEBUG mode "
1523 "is UNPREDICTABLE\n");
1525 if (arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1526 s
->prigroup
[attrs
.secure
] =
1528 R_V7M_AIRCR_PRIGROUP_SHIFT
,
1529 R_V7M_AIRCR_PRIGROUP_LENGTH
);
1532 /* These bits are only writable by secure */
1533 cpu
->env
.v7m
.aircr
= value
&
1534 (R_V7M_AIRCR_SYSRESETREQS_MASK
|
1535 R_V7M_AIRCR_BFHFNMINS_MASK
|
1536 R_V7M_AIRCR_PRIS_MASK
);
1537 /* BFHFNMINS changes the priority of Secure HardFault, and
1538 * allows a pending Non-secure HardFault to preempt (which
1539 * we implement by marking it enabled).
1541 if (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) {
1542 s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
= -3;
1543 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 1;
1545 s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
= -1;
1546 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 0;
1552 case 0xd10: /* System Control. */
1553 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1556 /* We don't implement deep-sleep so these bits are RAZ/WI.
1557 * The other bits in the register are banked.
1558 * QEMU's implementation ignores SEVONPEND and SLEEPONEXIT, which
1559 * is architecturally permitted.
1561 value
&= ~(R_V7M_SCR_SLEEPDEEP_MASK
| R_V7M_SCR_SLEEPDEEPS_MASK
);
1562 cpu
->env
.v7m
.scr
[attrs
.secure
] = value
;
1564 case 0xd14: /* Configuration Control. */
1565 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1569 /* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
1570 value
&= (R_V7M_CCR_STKALIGN_MASK
|
1571 R_V7M_CCR_BFHFNMIGN_MASK
|
1572 R_V7M_CCR_DIV_0_TRP_MASK
|
1573 R_V7M_CCR_UNALIGN_TRP_MASK
|
1574 R_V7M_CCR_USERSETMPEND_MASK
|
1575 R_V7M_CCR_NONBASETHRDENA_MASK
);
1577 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1578 /* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
1579 value
|= R_V7M_CCR_NONBASETHRDENA_MASK
1580 | R_V7M_CCR_STKALIGN_MASK
;
1583 /* the BFHFNMIGN bit is not banked; keep that in the NS copy */
1584 cpu
->env
.v7m
.ccr
[M_REG_NS
] =
1585 (cpu
->env
.v7m
.ccr
[M_REG_NS
] & ~R_V7M_CCR_BFHFNMIGN_MASK
)
1586 | (value
& R_V7M_CCR_BFHFNMIGN_MASK
);
1587 value
&= ~R_V7M_CCR_BFHFNMIGN_MASK
;
1590 cpu
->env
.v7m
.ccr
[attrs
.secure
] = value
;
1592 case 0xd24: /* System Handler Control and State (SHCSR) */
1593 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V7
)) {
1597 s
->sec_vectors
[ARMV7M_EXCP_MEM
].active
= (value
& (1 << 0)) != 0;
1598 /* Secure HardFault active bit cannot be written */
1599 s
->sec_vectors
[ARMV7M_EXCP_USAGE
].active
= (value
& (1 << 3)) != 0;
1600 s
->sec_vectors
[ARMV7M_EXCP_SVC
].active
= (value
& (1 << 7)) != 0;
1601 s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].active
=
1602 (value
& (1 << 10)) != 0;
1603 s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].active
=
1604 (value
& (1 << 11)) != 0;
1605 s
->sec_vectors
[ARMV7M_EXCP_USAGE
].pending
=
1606 (value
& (1 << 12)) != 0;
1607 s
->sec_vectors
[ARMV7M_EXCP_MEM
].pending
= (value
& (1 << 13)) != 0;
1608 s
->sec_vectors
[ARMV7M_EXCP_SVC
].pending
= (value
& (1 << 15)) != 0;
1609 s
->sec_vectors
[ARMV7M_EXCP_MEM
].enabled
= (value
& (1 << 16)) != 0;
1610 s
->sec_vectors
[ARMV7M_EXCP_BUS
].enabled
= (value
& (1 << 17)) != 0;
1611 s
->sec_vectors
[ARMV7M_EXCP_USAGE
].enabled
=
1612 (value
& (1 << 18)) != 0;
1613 s
->sec_vectors
[ARMV7M_EXCP_HARD
].pending
= (value
& (1 << 21)) != 0;
1614 /* SecureFault not banked, but RAZ/WI to NS */
1615 s
->vectors
[ARMV7M_EXCP_SECURE
].active
= (value
& (1 << 4)) != 0;
1616 s
->vectors
[ARMV7M_EXCP_SECURE
].enabled
= (value
& (1 << 19)) != 0;
1617 s
->vectors
[ARMV7M_EXCP_SECURE
].pending
= (value
& (1 << 20)) != 0;
1619 s
->vectors
[ARMV7M_EXCP_MEM
].active
= (value
& (1 << 0)) != 0;
1620 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1621 /* HARDFAULTPENDED is not present in v7M */
1622 s
->vectors
[ARMV7M_EXCP_HARD
].pending
= (value
& (1 << 21)) != 0;
1624 s
->vectors
[ARMV7M_EXCP_USAGE
].active
= (value
& (1 << 3)) != 0;
1625 s
->vectors
[ARMV7M_EXCP_SVC
].active
= (value
& (1 << 7)) != 0;
1626 s
->vectors
[ARMV7M_EXCP_PENDSV
].active
= (value
& (1 << 10)) != 0;
1627 s
->vectors
[ARMV7M_EXCP_SYSTICK
].active
= (value
& (1 << 11)) != 0;
1628 s
->vectors
[ARMV7M_EXCP_USAGE
].pending
= (value
& (1 << 12)) != 0;
1629 s
->vectors
[ARMV7M_EXCP_MEM
].pending
= (value
& (1 << 13)) != 0;
1630 s
->vectors
[ARMV7M_EXCP_SVC
].pending
= (value
& (1 << 15)) != 0;
1631 s
->vectors
[ARMV7M_EXCP_MEM
].enabled
= (value
& (1 << 16)) != 0;
1632 s
->vectors
[ARMV7M_EXCP_USAGE
].enabled
= (value
& (1 << 18)) != 0;
1634 if (attrs
.secure
|| (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
1635 s
->vectors
[ARMV7M_EXCP_BUS
].active
= (value
& (1 << 1)) != 0;
1636 s
->vectors
[ARMV7M_EXCP_BUS
].pending
= (value
& (1 << 14)) != 0;
1637 s
->vectors
[ARMV7M_EXCP_BUS
].enabled
= (value
& (1 << 17)) != 0;
1639 /* NMIACT can only be written if the write is of a zero, with
1640 * BFHFNMINS 1, and by the CPU in secure state via the NS alias.
1642 if (!attrs
.secure
&& cpu
->env
.v7m
.secure
&&
1643 (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) &&
1644 (value
& (1 << 5)) == 0) {
1645 s
->vectors
[ARMV7M_EXCP_NMI
].active
= 0;
1647 /* HARDFAULTACT can only be written if the write is of a zero
1648 * to the non-secure HardFault state by the CPU in secure state.
1649 * The only case where we can be targeting the non-secure HF state
1650 * when in secure state is if this is a write via the NS alias
1651 * and BFHFNMINS is 1.
1653 if (!attrs
.secure
&& cpu
->env
.v7m
.secure
&&
1654 (cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
) &&
1655 (value
& (1 << 2)) == 0) {
1656 s
->vectors
[ARMV7M_EXCP_HARD
].active
= 0;
1659 /* TODO: this is RAZ/WI from NS if DEMCR.SDME is set */
1660 s
->vectors
[ARMV7M_EXCP_DEBUG
].active
= (value
& (1 << 8)) != 0;
1663 case 0xd2c: /* Hard Fault Status. */
1664 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1667 cpu
->env
.v7m
.hfsr
&= ~value
; /* W1C */
1669 case 0xd30: /* Debug Fault Status. */
1670 cpu
->env
.v7m
.dfsr
&= ~value
; /* W1C */
1672 case 0xd34: /* Mem Manage Address. */
1673 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1676 cpu
->env
.v7m
.mmfar
[attrs
.secure
] = value
;
1678 case 0xd38: /* Bus Fault Address. */
1679 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1682 if (!attrs
.secure
&&
1683 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
1686 cpu
->env
.v7m
.bfar
= value
;
1688 case 0xd3c: /* Aux Fault Status. */
1689 qemu_log_mask(LOG_UNIMP
,
1690 "NVIC: Aux fault status registers unimplemented\n");
1692 case 0xd84: /* CSSELR */
1693 if (!arm_v7m_csselr_razwi(cpu
)) {
1694 cpu
->env
.v7m
.csselr
[attrs
.secure
] = value
& R_V7M_CSSELR_INDEX_MASK
;
1697 case 0xd88: /* CPACR */
1698 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1699 /* We implement only the Floating Point extension's CP10/CP11 */
1700 cpu
->env
.v7m
.cpacr
[attrs
.secure
] = value
& (0xf << 20);
1703 case 0xd8c: /* NSACR */
1704 if (attrs
.secure
&& arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1705 /* We implement only the Floating Point extension's CP10/CP11 */
1706 cpu
->env
.v7m
.nsacr
= value
& (3 << 10);
1709 case 0xd90: /* MPU_TYPE */
1711 case 0xd94: /* MPU_CTRL */
1713 (R_V7M_MPU_CTRL_HFNMIENA_MASK
| R_V7M_MPU_CTRL_ENABLE_MASK
))
1714 == R_V7M_MPU_CTRL_HFNMIENA_MASK
) {
1715 qemu_log_mask(LOG_GUEST_ERROR
, "MPU_CTRL: HFNMIENA and !ENABLE is "
1718 cpu
->env
.v7m
.mpu_ctrl
[attrs
.secure
]
1719 = value
& (R_V7M_MPU_CTRL_ENABLE_MASK
|
1720 R_V7M_MPU_CTRL_HFNMIENA_MASK
|
1721 R_V7M_MPU_CTRL_PRIVDEFENA_MASK
);
1722 tlb_flush(CPU(cpu
));
1724 case 0xd98: /* MPU_RNR */
1725 if (value
>= cpu
->pmsav7_dregion
) {
1726 qemu_log_mask(LOG_GUEST_ERROR
, "MPU region out of range %"
1727 PRIu32
"/%" PRIu32
"\n",
1728 value
, cpu
->pmsav7_dregion
);
1730 cpu
->env
.pmsav7
.rnr
[attrs
.secure
] = value
;
1733 case 0xd9c: /* MPU_RBAR */
1734 case 0xda4: /* MPU_RBAR_A1 */
1735 case 0xdac: /* MPU_RBAR_A2 */
1736 case 0xdb4: /* MPU_RBAR_A3 */
1740 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1741 /* PMSAv8M handling of the aliases is different from v7M:
1742 * aliases A1, A2, A3 override the low two bits of the region
1743 * number in MPU_RNR, and there is no 'region' field in the
1746 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
1748 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1750 region
= deposit32(region
, 0, 2, aliasno
);
1752 if (region
>= cpu
->pmsav7_dregion
) {
1755 cpu
->env
.pmsav8
.rbar
[attrs
.secure
][region
] = value
;
1756 tlb_flush(CPU(cpu
));
1760 if (value
& (1 << 4)) {
1761 /* VALID bit means use the region number specified in this
1762 * value and also update MPU_RNR.REGION with that value.
1764 region
= extract32(value
, 0, 4);
1765 if (region
>= cpu
->pmsav7_dregion
) {
1766 qemu_log_mask(LOG_GUEST_ERROR
,
1767 "MPU region out of range %u/%" PRIu32
"\n",
1768 region
, cpu
->pmsav7_dregion
);
1771 cpu
->env
.pmsav7
.rnr
[attrs
.secure
] = region
;
1773 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1776 if (region
>= cpu
->pmsav7_dregion
) {
1780 cpu
->env
.pmsav7
.drbar
[region
] = value
& ~0x1f;
1781 tlb_flush(CPU(cpu
));
1784 case 0xda0: /* MPU_RASR (v7M), MPU_RLAR (v8M) */
1785 case 0xda8: /* MPU_RASR_A1 (v7M), MPU_RLAR_A1 (v8M) */
1786 case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */
1787 case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */
1789 int region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1791 if (arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1792 /* PMSAv8M handling of the aliases is different from v7M:
1793 * aliases A1, A2, A3 override the low two bits of the region
1794 * number in MPU_RNR.
1796 int aliasno
= (offset
- 0xd9c) / 8; /* 0..3 */
1798 region
= cpu
->env
.pmsav7
.rnr
[attrs
.secure
];
1800 region
= deposit32(region
, 0, 2, aliasno
);
1802 if (region
>= cpu
->pmsav7_dregion
) {
1805 cpu
->env
.pmsav8
.rlar
[attrs
.secure
][region
] = value
;
1806 tlb_flush(CPU(cpu
));
1810 if (region
>= cpu
->pmsav7_dregion
) {
1814 cpu
->env
.pmsav7
.drsr
[region
] = value
& 0xff3f;
1815 cpu
->env
.pmsav7
.dracr
[region
] = (value
>> 16) & 0x173f;
1816 tlb_flush(CPU(cpu
));
1819 case 0xdc0: /* MPU_MAIR0 */
1820 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1823 if (cpu
->pmsav7_dregion
) {
1824 /* Register is RES0 if no MPU regions are implemented */
1825 cpu
->env
.pmsav8
.mair0
[attrs
.secure
] = value
;
1827 /* We don't need to do anything else because memory attributes
1828 * only affect cacheability, and we don't implement caching.
1831 case 0xdc4: /* MPU_MAIR1 */
1832 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1835 if (cpu
->pmsav7_dregion
) {
1836 /* Register is RES0 if no MPU regions are implemented */
1837 cpu
->env
.pmsav8
.mair1
[attrs
.secure
] = value
;
1839 /* We don't need to do anything else because memory attributes
1840 * only affect cacheability, and we don't implement caching.
1843 case 0xdd0: /* SAU_CTRL */
1844 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1847 if (!attrs
.secure
) {
1850 cpu
->env
.sau
.ctrl
= value
& 3;
1852 case 0xdd4: /* SAU_TYPE */
1853 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1857 case 0xdd8: /* SAU_RNR */
1858 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1861 if (!attrs
.secure
) {
1864 if (value
>= cpu
->sau_sregion
) {
1865 qemu_log_mask(LOG_GUEST_ERROR
, "SAU region out of range %"
1866 PRIu32
"/%" PRIu32
"\n",
1867 value
, cpu
->sau_sregion
);
1869 cpu
->env
.sau
.rnr
= value
;
1872 case 0xddc: /* SAU_RBAR */
1874 int region
= cpu
->env
.sau
.rnr
;
1876 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1879 if (!attrs
.secure
) {
1882 if (region
>= cpu
->sau_sregion
) {
1885 cpu
->env
.sau
.rbar
[region
] = value
& ~0x1f;
1886 tlb_flush(CPU(cpu
));
1889 case 0xde0: /* SAU_RLAR */
1891 int region
= cpu
->env
.sau
.rnr
;
1893 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1896 if (!attrs
.secure
) {
1899 if (region
>= cpu
->sau_sregion
) {
1902 cpu
->env
.sau
.rlar
[region
] = value
& ~0x1c;
1903 tlb_flush(CPU(cpu
));
1906 case 0xde4: /* SFSR */
1907 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1910 if (!attrs
.secure
) {
1913 cpu
->env
.v7m
.sfsr
&= ~value
; /* W1C */
1915 case 0xde8: /* SFAR */
1916 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1919 if (!attrs
.secure
) {
1922 cpu
->env
.v7m
.sfsr
= value
;
1924 case 0xf00: /* Software Triggered Interrupt Register */
1926 int excnum
= (value
& 0x1ff) + NVIC_FIRST_IRQ
;
1928 if (!arm_feature(&cpu
->env
, ARM_FEATURE_M_MAIN
)) {
1932 if (excnum
< s
->num_irq
) {
1933 armv7m_nvic_set_pending(s
, excnum
, false);
1937 case 0xf34: /* FPCCR */
1938 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1939 /* Not all bits here are banked. */
1942 if (!arm_feature(&cpu
->env
, ARM_FEATURE_V8
)) {
1943 /* Don't allow setting of bits not present in v7M */
1944 value
&= (R_V7M_FPCCR_LSPACT_MASK
|
1945 R_V7M_FPCCR_USER_MASK
|
1946 R_V7M_FPCCR_THREAD_MASK
|
1947 R_V7M_FPCCR_HFRDY_MASK
|
1948 R_V7M_FPCCR_MMRDY_MASK
|
1949 R_V7M_FPCCR_BFRDY_MASK
|
1950 R_V7M_FPCCR_MONRDY_MASK
|
1951 R_V7M_FPCCR_LSPEN_MASK
|
1952 R_V7M_FPCCR_ASPEN_MASK
);
1954 value
&= ~R_V7M_FPCCR_RES0_MASK
;
1956 if (!attrs
.secure
) {
1957 /* Some non-banked bits are configurably writable by NS */
1958 fpccr_s
= cpu
->env
.v7m
.fpccr
[M_REG_S
];
1959 if (!(fpccr_s
& R_V7M_FPCCR_LSPENS_MASK
)) {
1960 uint32_t lspen
= FIELD_EX32(value
, V7M_FPCCR
, LSPEN
);
1961 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, LSPEN
, lspen
);
1963 if (!(fpccr_s
& R_V7M_FPCCR_CLRONRETS_MASK
)) {
1964 uint32_t cor
= FIELD_EX32(value
, V7M_FPCCR
, CLRONRET
);
1965 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, CLRONRET
, cor
);
1967 if ((s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
1968 uint32_t hfrdy
= FIELD_EX32(value
, V7M_FPCCR
, HFRDY
);
1969 uint32_t bfrdy
= FIELD_EX32(value
, V7M_FPCCR
, BFRDY
);
1970 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, HFRDY
, hfrdy
);
1971 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, BFRDY
, bfrdy
);
1973 /* TODO MONRDY should RAZ/WI if DEMCR.SDME is set */
1975 uint32_t monrdy
= FIELD_EX32(value
, V7M_FPCCR
, MONRDY
);
1976 fpccr_s
= FIELD_DP32(fpccr_s
, V7M_FPCCR
, MONRDY
, monrdy
);
1980 * All other non-banked bits are RAZ/WI from NS; write
1981 * just the banked bits to fpccr[M_REG_NS].
1983 value
&= R_V7M_FPCCR_BANKED_MASK
;
1984 cpu
->env
.v7m
.fpccr
[M_REG_NS
] = value
;
1988 cpu
->env
.v7m
.fpccr
[M_REG_S
] = fpccr_s
;
1991 case 0xf38: /* FPCAR */
1992 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1994 cpu
->env
.v7m
.fpcar
[attrs
.secure
] = value
;
1997 case 0xf3c: /* FPDSCR */
1998 if (arm_feature(&cpu
->env
, ARM_FEATURE_VFP
)) {
1999 value
&= 0x07c00000;
2000 cpu
->env
.v7m
.fpdscr
[attrs
.secure
] = value
;
2003 case 0xf50: /* ICIALLU */
2004 case 0xf58: /* ICIMVAU */
2005 case 0xf5c: /* DCIMVAC */
2006 case 0xf60: /* DCISW */
2007 case 0xf64: /* DCCMVAU */
2008 case 0xf68: /* DCCMVAC */
2009 case 0xf6c: /* DCCSW */
2010 case 0xf70: /* DCCIMVAC */
2011 case 0xf74: /* DCCISW */
2012 case 0xf78: /* BPIALL */
2013 /* Cache and branch predictor maintenance: for QEMU these always NOP */
2017 qemu_log_mask(LOG_GUEST_ERROR
,
2018 "NVIC: Bad write offset 0x%x\n", offset
);
2022 static bool nvic_user_access_ok(NVICState
*s
, hwaddr offset
, MemTxAttrs attrs
)
2024 /* Return true if unprivileged access to this register is permitted. */
2026 case 0xf00: /* STIR: accessible only if CCR.USERSETMPEND permits */
2027 /* For access via STIR_NS it is the NS CCR.USERSETMPEND that
2028 * controls access even though the CPU is in Secure state (I_QDKX).
2030 return s
->cpu
->env
.v7m
.ccr
[attrs
.secure
] & R_V7M_CCR_USERSETMPEND_MASK
;
2032 /* All other user accesses cause a BusFault unconditionally */
2037 static int shpr_bank(NVICState
*s
, int exc
, MemTxAttrs attrs
)
2039 /* Behaviour for the SHPR register field for this exception:
2040 * return M_REG_NS to use the nonsecure vector (including for
2041 * non-banked exceptions), M_REG_S for the secure version of
2042 * a banked exception, and -1 if this field should RAZ/WI.
2045 case ARMV7M_EXCP_MEM
:
2046 case ARMV7M_EXCP_USAGE
:
2047 case ARMV7M_EXCP_SVC
:
2048 case ARMV7M_EXCP_PENDSV
:
2049 case ARMV7M_EXCP_SYSTICK
:
2050 /* Banked exceptions */
2051 return attrs
.secure
;
2052 case ARMV7M_EXCP_BUS
:
2053 /* Not banked, RAZ/WI from nonsecure if BFHFNMINS is zero */
2054 if (!attrs
.secure
&&
2055 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
2059 case ARMV7M_EXCP_SECURE
:
2060 /* Not banked, RAZ/WI from nonsecure */
2061 if (!attrs
.secure
) {
2065 case ARMV7M_EXCP_DEBUG
:
2066 /* Not banked. TODO should RAZ/WI if DEMCR.SDME is set */
2073 /* Not reachable due to decode of SHPR register addresses */
2074 g_assert_not_reached();
2078 static MemTxResult
nvic_sysreg_read(void *opaque
, hwaddr addr
,
2079 uint64_t *data
, unsigned size
,
2082 NVICState
*s
= (NVICState
*)opaque
;
2083 uint32_t offset
= addr
;
2084 unsigned i
, startvec
, end
;
2087 if (attrs
.user
&& !nvic_user_access_ok(s
, addr
, attrs
)) {
2088 /* Generate BusFault for unprivileged accesses */
2093 /* reads of set and clear both return the status */
2094 case 0x100 ... 0x13f: /* NVIC Set enable */
2097 case 0x180 ... 0x1bf: /* NVIC Clear enable */
2099 startvec
= 8 * (offset
- 0x180) + NVIC_FIRST_IRQ
; /* vector # */
2101 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
2102 if (s
->vectors
[startvec
+ i
].enabled
&&
2103 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
2108 case 0x200 ... 0x23f: /* NVIC Set pend */
2111 case 0x280 ... 0x2bf: /* NVIC Clear pend */
2113 startvec
= 8 * (offset
- 0x280) + NVIC_FIRST_IRQ
; /* vector # */
2114 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
2115 if (s
->vectors
[startvec
+ i
].pending
&&
2116 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
2121 case 0x300 ... 0x33f: /* NVIC Active */
2124 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_V7
)) {
2128 startvec
= 8 * (offset
- 0x300) + NVIC_FIRST_IRQ
; /* vector # */
2130 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
2131 if (s
->vectors
[startvec
+ i
].active
&&
2132 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
2137 case 0x400 ... 0x5ef: /* NVIC Priority */
2139 startvec
= offset
- 0x400 + NVIC_FIRST_IRQ
; /* vector # */
2141 for (i
= 0; i
< size
&& startvec
+ i
< s
->num_irq
; i
++) {
2142 if (attrs
.secure
|| s
->itns
[startvec
+ i
]) {
2143 val
|= s
->vectors
[startvec
+ i
].prio
<< (8 * i
);
2147 case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
2148 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_MAIN
)) {
2153 case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */
2155 for (i
= 0; i
< size
; i
++) {
2156 unsigned hdlidx
= (offset
- 0xd14) + i
;
2157 int sbank
= shpr_bank(s
, hdlidx
, attrs
);
2162 val
= deposit32(val
, i
* 8, 8, get_prio(s
, hdlidx
, sbank
));
2165 case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
2166 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_MAIN
)) {
2171 * The BFSR bits [15:8] are shared between security states
2172 * and we store them in the NS copy. They are RAZ/WI for
2173 * NS code if AIRCR.BFHFNMINS is 0.
2175 val
= s
->cpu
->env
.v7m
.cfsr
[attrs
.secure
];
2176 if (!attrs
.secure
&&
2177 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
2178 val
&= ~R_V7M_CFSR_BFSR_MASK
;
2180 val
|= s
->cpu
->env
.v7m
.cfsr
[M_REG_NS
] & R_V7M_CFSR_BFSR_MASK
;
2182 val
= extract32(val
, (offset
- 0xd28) * 8, size
* 8);
2184 case 0xfe0 ... 0xfff: /* ID. */
2188 val
= nvic_id
[(offset
- 0xfe0) >> 2];
2193 val
= nvic_readl(s
, offset
, attrs
);
2195 qemu_log_mask(LOG_GUEST_ERROR
,
2196 "NVIC: Bad read of size %d at offset 0x%x\n",
2202 trace_nvic_sysreg_read(addr
, val
, size
);
2207 static MemTxResult
nvic_sysreg_write(void *opaque
, hwaddr addr
,
2208 uint64_t value
, unsigned size
,
2211 NVICState
*s
= (NVICState
*)opaque
;
2212 uint32_t offset
= addr
;
2213 unsigned i
, startvec
, end
;
2214 unsigned setval
= 0;
2216 trace_nvic_sysreg_write(addr
, value
, size
);
2218 if (attrs
.user
&& !nvic_user_access_ok(s
, addr
, attrs
)) {
2219 /* Generate BusFault for unprivileged accesses */
2224 case 0x100 ... 0x13f: /* NVIC Set enable */
2228 case 0x180 ... 0x1bf: /* NVIC Clear enable */
2229 startvec
= 8 * (offset
- 0x180) + NVIC_FIRST_IRQ
;
2231 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
2232 if (value
& (1 << i
) &&
2233 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
2234 s
->vectors
[startvec
+ i
].enabled
= setval
;
2239 case 0x200 ... 0x23f: /* NVIC Set pend */
2240 /* the special logic in armv7m_nvic_set_pending()
2241 * is not needed since IRQs are never escalated
2246 case 0x280 ... 0x2bf: /* NVIC Clear pend */
2247 startvec
= 8 * (offset
- 0x280) + NVIC_FIRST_IRQ
; /* vector # */
2249 for (i
= 0, end
= size
* 8; i
< end
&& startvec
+ i
< s
->num_irq
; i
++) {
2250 if (value
& (1 << i
) &&
2251 (attrs
.secure
|| s
->itns
[startvec
+ i
])) {
2252 s
->vectors
[startvec
+ i
].pending
= setval
;
2257 case 0x300 ... 0x33f: /* NVIC Active */
2258 return MEMTX_OK
; /* R/O */
2259 case 0x400 ... 0x5ef: /* NVIC Priority */
2260 startvec
= (offset
- 0x400) + NVIC_FIRST_IRQ
; /* vector # */
2262 for (i
= 0; i
< size
&& startvec
+ i
< s
->num_irq
; i
++) {
2263 if (attrs
.secure
|| s
->itns
[startvec
+ i
]) {
2264 set_prio(s
, startvec
+ i
, false, (value
>> (i
* 8)) & 0xff);
2269 case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
2270 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_MAIN
)) {
2274 case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */
2275 for (i
= 0; i
< size
; i
++) {
2276 unsigned hdlidx
= (offset
- 0xd14) + i
;
2277 int newprio
= extract32(value
, i
* 8, 8);
2278 int sbank
= shpr_bank(s
, hdlidx
, attrs
);
2283 set_prio(s
, hdlidx
, sbank
, newprio
);
2287 case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
2288 if (!arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_MAIN
)) {
2291 /* All bits are W1C, so construct 32 bit value with 0s in
2292 * the parts not written by the access size
2294 value
<<= ((offset
- 0xd28) * 8);
2296 if (!attrs
.secure
&&
2297 !(s
->cpu
->env
.v7m
.aircr
& R_V7M_AIRCR_BFHFNMINS_MASK
)) {
2298 /* BFSR bits are RAZ/WI for NS if BFHFNMINS is set */
2299 value
&= ~R_V7M_CFSR_BFSR_MASK
;
2302 s
->cpu
->env
.v7m
.cfsr
[attrs
.secure
] &= ~value
;
2304 /* The BFSR bits [15:8] are shared between security states
2305 * and we store them in the NS copy.
2307 s
->cpu
->env
.v7m
.cfsr
[M_REG_NS
] &= ~(value
& R_V7M_CFSR_BFSR_MASK
);
2312 nvic_writel(s
, offset
, value
, attrs
);
2315 qemu_log_mask(LOG_GUEST_ERROR
,
2316 "NVIC: Bad write of size %d at offset 0x%x\n", size
, offset
);
2317 /* This is UNPREDICTABLE; treat as RAZ/WI */
2321 static const MemoryRegionOps nvic_sysreg_ops
= {
2322 .read_with_attrs
= nvic_sysreg_read
,
2323 .write_with_attrs
= nvic_sysreg_write
,
2324 .endianness
= DEVICE_NATIVE_ENDIAN
,
2327 static MemTxResult
nvic_sysreg_ns_write(void *opaque
, hwaddr addr
,
2328 uint64_t value
, unsigned size
,
2331 MemoryRegion
*mr
= opaque
;
2334 /* S accesses to the alias act like NS accesses to the real region */
2336 return memory_region_dispatch_write(mr
, addr
, value
, size
, attrs
);
2338 /* NS attrs are RAZ/WI for privileged, and BusFault for user */
2346 static MemTxResult
nvic_sysreg_ns_read(void *opaque
, hwaddr addr
,
2347 uint64_t *data
, unsigned size
,
2350 MemoryRegion
*mr
= opaque
;
2353 /* S accesses to the alias act like NS accesses to the real region */
2355 return memory_region_dispatch_read(mr
, addr
, data
, size
, attrs
);
2357 /* NS attrs are RAZ/WI for privileged, and BusFault for user */
2366 static const MemoryRegionOps nvic_sysreg_ns_ops
= {
2367 .read_with_attrs
= nvic_sysreg_ns_read
,
2368 .write_with_attrs
= nvic_sysreg_ns_write
,
2369 .endianness
= DEVICE_NATIVE_ENDIAN
,
2372 static MemTxResult
nvic_systick_write(void *opaque
, hwaddr addr
,
2373 uint64_t value
, unsigned size
,
2376 NVICState
*s
= opaque
;
2379 /* Direct the access to the correct systick */
2380 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->systick
[attrs
.secure
]), 0);
2381 return memory_region_dispatch_write(mr
, addr
, value
, size
, attrs
);
2384 static MemTxResult
nvic_systick_read(void *opaque
, hwaddr addr
,
2385 uint64_t *data
, unsigned size
,
2388 NVICState
*s
= opaque
;
2391 /* Direct the access to the correct systick */
2392 mr
= sysbus_mmio_get_region(SYS_BUS_DEVICE(&s
->systick
[attrs
.secure
]), 0);
2393 return memory_region_dispatch_read(mr
, addr
, data
, size
, attrs
);
2396 static const MemoryRegionOps nvic_systick_ops
= {
2397 .read_with_attrs
= nvic_systick_read
,
2398 .write_with_attrs
= nvic_systick_write
,
2399 .endianness
= DEVICE_NATIVE_ENDIAN
,
2402 static int nvic_post_load(void *opaque
, int version_id
)
2404 NVICState
*s
= opaque
;
2408 /* Check for out of range priority settings */
2409 resetprio
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
) ? -4 : -3;
2411 if (s
->vectors
[ARMV7M_EXCP_RESET
].prio
!= resetprio
||
2412 s
->vectors
[ARMV7M_EXCP_NMI
].prio
!= -2 ||
2413 s
->vectors
[ARMV7M_EXCP_HARD
].prio
!= -1) {
2416 for (i
= ARMV7M_EXCP_MEM
; i
< s
->num_irq
; i
++) {
2417 if (s
->vectors
[i
].prio
& ~0xff) {
2422 nvic_recompute_state(s
);
2427 static const VMStateDescription vmstate_VecInfo
= {
2428 .name
= "armv7m_nvic_info",
2430 .minimum_version_id
= 1,
2431 .fields
= (VMStateField
[]) {
2432 VMSTATE_INT16(prio
, VecInfo
),
2433 VMSTATE_UINT8(enabled
, VecInfo
),
2434 VMSTATE_UINT8(pending
, VecInfo
),
2435 VMSTATE_UINT8(active
, VecInfo
),
2436 VMSTATE_UINT8(level
, VecInfo
),
2437 VMSTATE_END_OF_LIST()
2441 static bool nvic_security_needed(void *opaque
)
2443 NVICState
*s
= opaque
;
2445 return arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
);
2448 static int nvic_security_post_load(void *opaque
, int version_id
)
2450 NVICState
*s
= opaque
;
2453 /* Check for out of range priority settings */
2454 if (s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
!= -1
2455 && s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
!= -3) {
2456 /* We can't cross-check against AIRCR.BFHFNMINS as we don't know
2457 * if the CPU state has been migrated yet; a mismatch won't
2458 * cause the emulation to blow up, though.
2462 for (i
= ARMV7M_EXCP_MEM
; i
< ARRAY_SIZE(s
->sec_vectors
); i
++) {
2463 if (s
->sec_vectors
[i
].prio
& ~0xff) {
2470 static const VMStateDescription vmstate_nvic_security
= {
2471 .name
= "armv7m_nvic/m-security",
2473 .minimum_version_id
= 1,
2474 .needed
= nvic_security_needed
,
2475 .post_load
= &nvic_security_post_load
,
2476 .fields
= (VMStateField
[]) {
2477 VMSTATE_STRUCT_ARRAY(sec_vectors
, NVICState
, NVIC_INTERNAL_VECTORS
, 1,
2478 vmstate_VecInfo
, VecInfo
),
2479 VMSTATE_UINT32(prigroup
[M_REG_S
], NVICState
),
2480 VMSTATE_BOOL_ARRAY(itns
, NVICState
, NVIC_MAX_VECTORS
),
2481 VMSTATE_END_OF_LIST()
2485 static const VMStateDescription vmstate_nvic
= {
2486 .name
= "armv7m_nvic",
2488 .minimum_version_id
= 4,
2489 .post_load
= &nvic_post_load
,
2490 .fields
= (VMStateField
[]) {
2491 VMSTATE_STRUCT_ARRAY(vectors
, NVICState
, NVIC_MAX_VECTORS
, 1,
2492 vmstate_VecInfo
, VecInfo
),
2493 VMSTATE_UINT32(prigroup
[M_REG_NS
], NVICState
),
2494 VMSTATE_END_OF_LIST()
2496 .subsections
= (const VMStateDescription
*[]) {
2497 &vmstate_nvic_security
,
2502 static Property props_nvic
[] = {
2503 /* Number of external IRQ lines (so excluding the 16 internal exceptions) */
2504 DEFINE_PROP_UINT32("num-irq", NVICState
, num_irq
, 64),
2505 DEFINE_PROP_END_OF_LIST()
2508 static void armv7m_nvic_reset(DeviceState
*dev
)
2511 NVICState
*s
= NVIC(dev
);
2513 memset(s
->vectors
, 0, sizeof(s
->vectors
));
2514 memset(s
->sec_vectors
, 0, sizeof(s
->sec_vectors
));
2515 s
->prigroup
[M_REG_NS
] = 0;
2516 s
->prigroup
[M_REG_S
] = 0;
2518 s
->vectors
[ARMV7M_EXCP_NMI
].enabled
= 1;
2519 /* MEM, BUS, and USAGE are enabled through
2520 * the System Handler Control register
2522 s
->vectors
[ARMV7M_EXCP_SVC
].enabled
= 1;
2523 s
->vectors
[ARMV7M_EXCP_PENDSV
].enabled
= 1;
2524 s
->vectors
[ARMV7M_EXCP_SYSTICK
].enabled
= 1;
2526 /* DebugMonitor is enabled via DEMCR.MON_EN */
2527 s
->vectors
[ARMV7M_EXCP_DEBUG
].enabled
= 0;
2529 resetprio
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
) ? -4 : -3;
2530 s
->vectors
[ARMV7M_EXCP_RESET
].prio
= resetprio
;
2531 s
->vectors
[ARMV7M_EXCP_NMI
].prio
= -2;
2532 s
->vectors
[ARMV7M_EXCP_HARD
].prio
= -1;
2534 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
2535 s
->sec_vectors
[ARMV7M_EXCP_HARD
].enabled
= 1;
2536 s
->sec_vectors
[ARMV7M_EXCP_SVC
].enabled
= 1;
2537 s
->sec_vectors
[ARMV7M_EXCP_PENDSV
].enabled
= 1;
2538 s
->sec_vectors
[ARMV7M_EXCP_SYSTICK
].enabled
= 1;
2540 /* AIRCR.BFHFNMINS resets to 0 so Secure HF is priority -1 (R_CMTC) */
2541 s
->sec_vectors
[ARMV7M_EXCP_HARD
].prio
= -1;
2542 /* If AIRCR.BFHFNMINS is 0 then NS HF is (effectively) disabled */
2543 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 0;
2545 s
->vectors
[ARMV7M_EXCP_HARD
].enabled
= 1;
2548 /* Strictly speaking the reset handler should be enabled.
2549 * However, we don't simulate soft resets through the NVIC,
2550 * and the reset vector should never be pended.
2551 * So we leave it disabled to catch logic errors.
2554 s
->exception_prio
= NVIC_NOEXC_PRIO
;
2556 s
->vectpending_is_s_banked
= false;
2557 s
->vectpending_prio
= NVIC_NOEXC_PRIO
;
2559 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
2560 memset(s
->itns
, 0, sizeof(s
->itns
));
2562 /* This state is constant and not guest accessible in a non-security
2563 * NVIC; we set the bits to true to avoid having to do a feature
2564 * bit check in the NVIC enable/pend/etc register accessors.
2568 for (i
= NVIC_FIRST_IRQ
; i
< ARRAY_SIZE(s
->itns
); i
++) {
2574 static void nvic_systick_trigger(void *opaque
, int n
, int level
)
2576 NVICState
*s
= opaque
;
2579 /* SysTick just asked us to pend its exception.
2580 * (This is different from an external interrupt line's
2582 * n == 0 : NonSecure systick
2583 * n == 1 : Secure systick
2585 armv7m_nvic_set_pending(s
, ARMV7M_EXCP_SYSTICK
, n
);
2589 static void armv7m_nvic_realize(DeviceState
*dev
, Error
**errp
)
2591 NVICState
*s
= NVIC(dev
);
2595 /* The armv7m container object will have set our CPU pointer */
2596 if (!s
->cpu
|| !arm_feature(&s
->cpu
->env
, ARM_FEATURE_M
)) {
2597 error_setg(errp
, "The NVIC can only be used with a Cortex-M CPU");
2601 if (s
->num_irq
> NVIC_MAX_IRQ
) {
2602 error_setg(errp
, "num-irq %d exceeds NVIC maximum", s
->num_irq
);
2606 qdev_init_gpio_in(dev
, set_irq_level
, s
->num_irq
);
2608 /* include space for internal exception vectors */
2609 s
->num_irq
+= NVIC_FIRST_IRQ
;
2611 s
->num_prio_bits
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V7
) ? 8 : 2;
2613 object_property_set_bool(OBJECT(&s
->systick
[M_REG_NS
]), true,
2616 error_propagate(errp
, err
);
2619 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->systick
[M_REG_NS
]), 0,
2620 qdev_get_gpio_in_named(dev
, "systick-trigger",
2623 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_M_SECURITY
)) {
2624 /* We couldn't init the secure systick device in instance_init
2625 * as we didn't know then if the CPU had the security extensions;
2626 * so we have to do it here.
2628 sysbus_init_child_obj(OBJECT(dev
), "systick-reg-s",
2629 &s
->systick
[M_REG_S
],
2630 sizeof(s
->systick
[M_REG_S
]), TYPE_SYSTICK
);
2632 object_property_set_bool(OBJECT(&s
->systick
[M_REG_S
]), true,
2635 error_propagate(errp
, err
);
2638 sysbus_connect_irq(SYS_BUS_DEVICE(&s
->systick
[M_REG_S
]), 0,
2639 qdev_get_gpio_in_named(dev
, "systick-trigger",
2643 /* The NVIC and System Control Space (SCS) starts at 0xe000e000
2644 * and looks like this:
2646 * 0x010 - 0xff - systick
2647 * 0x100..0x7ec - NVIC
2648 * 0x7f0..0xcff - Reserved
2649 * 0xd00..0xd3c - SCS registers
2650 * 0xd40..0xeff - Reserved or Not implemented
2653 * Some registers within this space are banked between security states.
2654 * In v8M there is a second range 0xe002e000..0xe002efff which is the
2655 * NonSecure alias SCS; secure accesses to this behave like NS accesses
2656 * to the main SCS range, and non-secure accesses (including when
2657 * the security extension is not implemented) are RAZ/WI.
2658 * Note that both the main SCS range and the alias range are defined
2659 * to be exempt from memory attribution (R_BLJT) and so the memory
2660 * transaction attribute always matches the current CPU security
2661 * state (attrs.secure == env->v7m.secure). In the nvic_sysreg_ns_ops
2662 * wrappers we change attrs.secure to indicate the NS access; so
2663 * generally code determining which banked register to use should
2664 * use attrs.secure; code determining actual behaviour of the system
2665 * should use env->v7m.secure.
2667 regionlen
= arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
) ? 0x21000 : 0x1000;
2668 memory_region_init(&s
->container
, OBJECT(s
), "nvic", regionlen
);
2669 /* The system register region goes at the bottom of the priority
2670 * stack as it covers the whole page.
2672 memory_region_init_io(&s
->sysregmem
, OBJECT(s
), &nvic_sysreg_ops
, s
,
2673 "nvic_sysregs", 0x1000);
2674 memory_region_add_subregion(&s
->container
, 0, &s
->sysregmem
);
2676 memory_region_init_io(&s
->systickmem
, OBJECT(s
),
2677 &nvic_systick_ops
, s
,
2678 "nvic_systick", 0xe0);
2680 memory_region_add_subregion_overlap(&s
->container
, 0x10,
2683 if (arm_feature(&s
->cpu
->env
, ARM_FEATURE_V8
)) {
2684 memory_region_init_io(&s
->sysreg_ns_mem
, OBJECT(s
),
2685 &nvic_sysreg_ns_ops
, &s
->sysregmem
,
2686 "nvic_sysregs_ns", 0x1000);
2687 memory_region_add_subregion(&s
->container
, 0x20000, &s
->sysreg_ns_mem
);
2688 memory_region_init_io(&s
->systick_ns_mem
, OBJECT(s
),
2689 &nvic_sysreg_ns_ops
, &s
->systickmem
,
2690 "nvic_systick_ns", 0xe0);
2691 memory_region_add_subregion_overlap(&s
->container
, 0x20010,
2692 &s
->systick_ns_mem
, 1);
2695 sysbus_init_mmio(SYS_BUS_DEVICE(dev
), &s
->container
);
2698 static void armv7m_nvic_instance_init(Object
*obj
)
2700 /* We have a different default value for the num-irq property
2701 * than our superclass. This function runs after qdev init
2702 * has set the defaults from the Property array and before
2703 * any user-specified property setting, so just modify the
2704 * value in the GICState struct.
2706 DeviceState
*dev
= DEVICE(obj
);
2707 NVICState
*nvic
= NVIC(obj
);
2708 SysBusDevice
*sbd
= SYS_BUS_DEVICE(obj
);
2710 sysbus_init_child_obj(obj
, "systick-reg-ns", &nvic
->systick
[M_REG_NS
],
2711 sizeof(nvic
->systick
[M_REG_NS
]), TYPE_SYSTICK
);
2712 /* We can't initialize the secure systick here, as we don't know
2713 * yet if we need it.
2716 sysbus_init_irq(sbd
, &nvic
->excpout
);
2717 qdev_init_gpio_out_named(dev
, &nvic
->sysresetreq
, "SYSRESETREQ", 1);
2718 qdev_init_gpio_in_named(dev
, nvic_systick_trigger
, "systick-trigger",
2720 qdev_init_gpio_in_named(dev
, nvic_nmi_trigger
, "NMI", 1);
2723 static void armv7m_nvic_class_init(ObjectClass
*klass
, void *data
)
2725 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2727 dc
->vmsd
= &vmstate_nvic
;
2728 dc
->props
= props_nvic
;
2729 dc
->reset
= armv7m_nvic_reset
;
2730 dc
->realize
= armv7m_nvic_realize
;
2733 static const TypeInfo armv7m_nvic_info
= {
2735 .parent
= TYPE_SYS_BUS_DEVICE
,
2736 .instance_init
= armv7m_nvic_instance_init
,
2737 .instance_size
= sizeof(NVICState
),
2738 .class_init
= armv7m_nvic_class_init
,
2739 .class_size
= sizeof(SysBusDeviceClass
),
2742 static void armv7m_nvic_register_types(void)
2744 type_register_static(&armv7m_nvic_info
);
2747 type_init(armv7m_nvic_register_types
)