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1 /*
2 * ARM Nested Vectored Interrupt Controller
3 *
4 * Copyright (c) 2006-2007 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GPL.
8 *
9 * The ARMv7M System controller is fairly tightly tied in with the
10 * NVIC. Much of that is also implemented here.
11 */
12
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "qemu-common.h"
16 #include "cpu.h"
17 #include "hw/sysbus.h"
18 #include "qemu/timer.h"
19 #include "hw/arm/arm.h"
20 #include "exec/address-spaces.h"
21 #include "gic_internal.h"
22
23 typedef struct {
24 GICState gic;
25 struct {
26 uint32_t control;
27 uint32_t reload;
28 int64_t tick;
29 QEMUTimer *timer;
30 } systick;
31 MemoryRegion sysregmem;
32 MemoryRegion gic_iomem_alias;
33 MemoryRegion container;
34 uint32_t num_irq;
35 qemu_irq sysresetreq;
36 } nvic_state;
37
38 #define TYPE_NVIC "armv7m_nvic"
39 /**
40 * NVICClass:
41 * @parent_reset: the parent class' reset handler.
42 *
43 * A model of the v7M NVIC and System Controller
44 */
45 typedef struct NVICClass {
46 /*< private >*/
47 ARMGICClass parent_class;
48 /*< public >*/
49 DeviceRealize parent_realize;
50 void (*parent_reset)(DeviceState *dev);
51 } NVICClass;
52
53 #define NVIC_CLASS(klass) \
54 OBJECT_CLASS_CHECK(NVICClass, (klass), TYPE_NVIC)
55 #define NVIC_GET_CLASS(obj) \
56 OBJECT_GET_CLASS(NVICClass, (obj), TYPE_NVIC)
57 #define NVIC(obj) \
58 OBJECT_CHECK(nvic_state, (obj), TYPE_NVIC)
59
60 static const uint8_t nvic_id[] = {
61 0x00, 0xb0, 0x1b, 0x00, 0x0d, 0xe0, 0x05, 0xb1
62 };
63
64 /* qemu timers run at 1GHz. We want something closer to 1MHz. */
65 #define SYSTICK_SCALE 1000ULL
66
67 #define SYSTICK_ENABLE (1 << 0)
68 #define SYSTICK_TICKINT (1 << 1)
69 #define SYSTICK_CLKSOURCE (1 << 2)
70 #define SYSTICK_COUNTFLAG (1 << 16)
71
72 int system_clock_scale;
73
74 /* Conversion factor from qemu timer to SysTick frequencies. */
75 static inline int64_t systick_scale(nvic_state *s)
76 {
77 if (s->systick.control & SYSTICK_CLKSOURCE)
78 return system_clock_scale;
79 else
80 return 1000;
81 }
82
83 static void systick_reload(nvic_state *s, int reset)
84 {
85 /* The Cortex-M3 Devices Generic User Guide says that "When the
86 * ENABLE bit is set to 1, the counter loads the RELOAD value from the
87 * SYST RVR register and then counts down". So, we need to check the
88 * ENABLE bit before reloading the value.
89 */
90 if ((s->systick.control & SYSTICK_ENABLE) == 0) {
91 return;
92 }
93
94 if (reset)
95 s->systick.tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
96 s->systick.tick += (s->systick.reload + 1) * systick_scale(s);
97 timer_mod(s->systick.timer, s->systick.tick);
98 }
99
100 static void systick_timer_tick(void * opaque)
101 {
102 nvic_state *s = (nvic_state *)opaque;
103 s->systick.control |= SYSTICK_COUNTFLAG;
104 if (s->systick.control & SYSTICK_TICKINT) {
105 /* Trigger the interrupt. */
106 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
107 }
108 if (s->systick.reload == 0) {
109 s->systick.control &= ~SYSTICK_ENABLE;
110 } else {
111 systick_reload(s, 0);
112 }
113 }
114
115 static void systick_reset(nvic_state *s)
116 {
117 s->systick.control = 0;
118 s->systick.reload = 0;
119 s->systick.tick = 0;
120 timer_del(s->systick.timer);
121 }
122
123 /* The external routines use the hardware vector numbering, ie. the first
124 IRQ is #16. The internal GIC routines use #32 as the first IRQ. */
125 void armv7m_nvic_set_pending(void *opaque, int irq)
126 {
127 nvic_state *s = (nvic_state *)opaque;
128 if (irq >= 16)
129 irq += 16;
130 gic_set_pending_private(&s->gic, 0, irq);
131 }
132
133 /* Make pending IRQ active. */
134 int armv7m_nvic_acknowledge_irq(void *opaque)
135 {
136 nvic_state *s = (nvic_state *)opaque;
137 uint32_t irq;
138
139 irq = gic_acknowledge_irq(&s->gic, 0, MEMTXATTRS_UNSPECIFIED);
140 if (irq == 1023)
141 hw_error("Interrupt but no vector\n");
142 if (irq >= 32)
143 irq -= 16;
144 return irq;
145 }
146
147 void armv7m_nvic_complete_irq(void *opaque, int irq)
148 {
149 nvic_state *s = (nvic_state *)opaque;
150 if (irq >= 16)
151 irq += 16;
152 gic_complete_irq(&s->gic, 0, irq, MEMTXATTRS_UNSPECIFIED);
153 }
154
155 static uint32_t nvic_readl(nvic_state *s, uint32_t offset)
156 {
157 ARMCPU *cpu;
158 uint32_t val;
159 int irq;
160
161 switch (offset) {
162 case 4: /* Interrupt Control Type. */
163 return (s->num_irq / 32) - 1;
164 case 0x10: /* SysTick Control and Status. */
165 val = s->systick.control;
166 s->systick.control &= ~SYSTICK_COUNTFLAG;
167 return val;
168 case 0x14: /* SysTick Reload Value. */
169 return s->systick.reload;
170 case 0x18: /* SysTick Current Value. */
171 {
172 int64_t t;
173 if ((s->systick.control & SYSTICK_ENABLE) == 0)
174 return 0;
175 t = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
176 if (t >= s->systick.tick)
177 return 0;
178 val = ((s->systick.tick - (t + 1)) / systick_scale(s)) + 1;
179 /* The interrupt in triggered when the timer reaches zero.
180 However the counter is not reloaded until the next clock
181 tick. This is a hack to return zero during the first tick. */
182 if (val > s->systick.reload)
183 val = 0;
184 return val;
185 }
186 case 0x1c: /* SysTick Calibration Value. */
187 return 10000;
188 case 0xd00: /* CPUID Base. */
189 cpu = ARM_CPU(current_cpu);
190 return cpu->midr;
191 case 0xd04: /* Interrupt Control State. */
192 /* VECTACTIVE */
193 cpu = ARM_CPU(current_cpu);
194 val = cpu->env.v7m.exception;
195 if (val == 1023) {
196 val = 0;
197 } else if (val >= 32) {
198 val -= 16;
199 }
200 /* VECTPENDING */
201 if (s->gic.current_pending[0] != 1023)
202 val |= (s->gic.current_pending[0] << 12);
203 /* ISRPENDING and RETTOBASE */
204 for (irq = 32; irq < s->num_irq; irq++) {
205 if (s->gic.irq_state[irq].pending) {
206 val |= (1 << 22);
207 break;
208 }
209 if (irq != cpu->env.v7m.exception && s->gic.irq_state[irq].active) {
210 val |= (1 << 11);
211 }
212 }
213 /* PENDSTSET */
214 if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending)
215 val |= (1 << 26);
216 /* PENDSVSET */
217 if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending)
218 val |= (1 << 28);
219 /* NMIPENDSET */
220 if (s->gic.irq_state[ARMV7M_EXCP_NMI].pending)
221 val |= (1 << 31);
222 return val;
223 case 0xd08: /* Vector Table Offset. */
224 cpu = ARM_CPU(current_cpu);
225 return cpu->env.v7m.vecbase;
226 case 0xd0c: /* Application Interrupt/Reset Control. */
227 return 0xfa050000;
228 case 0xd10: /* System Control. */
229 /* TODO: Implement SLEEPONEXIT. */
230 return 0;
231 case 0xd14: /* Configuration Control. */
232 /* TODO: Implement Configuration Control bits. */
233 return 0;
234 case 0xd24: /* System Handler Status. */
235 val = 0;
236 if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
237 if (s->gic.irq_state[ARMV7M_EXCP_BUS].active) val |= (1 << 1);
238 if (s->gic.irq_state[ARMV7M_EXCP_USAGE].active) val |= (1 << 3);
239 if (s->gic.irq_state[ARMV7M_EXCP_SVC].active) val |= (1 << 7);
240 if (s->gic.irq_state[ARMV7M_EXCP_DEBUG].active) val |= (1 << 8);
241 if (s->gic.irq_state[ARMV7M_EXCP_PENDSV].active) val |= (1 << 10);
242 if (s->gic.irq_state[ARMV7M_EXCP_SYSTICK].active) val |= (1 << 11);
243 if (s->gic.irq_state[ARMV7M_EXCP_USAGE].pending) val |= (1 << 12);
244 if (s->gic.irq_state[ARMV7M_EXCP_MEM].pending) val |= (1 << 13);
245 if (s->gic.irq_state[ARMV7M_EXCP_BUS].pending) val |= (1 << 14);
246 if (s->gic.irq_state[ARMV7M_EXCP_SVC].pending) val |= (1 << 15);
247 if (s->gic.irq_state[ARMV7M_EXCP_MEM].enabled) val |= (1 << 16);
248 if (s->gic.irq_state[ARMV7M_EXCP_BUS].enabled) val |= (1 << 17);
249 if (s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled) val |= (1 << 18);
250 return val;
251 case 0xd28: /* Configurable Fault Status. */
252 /* TODO: Implement Fault Status. */
253 qemu_log_mask(LOG_UNIMP, "Configurable Fault Status unimplemented\n");
254 return 0;
255 case 0xd2c: /* Hard Fault Status. */
256 case 0xd30: /* Debug Fault Status. */
257 case 0xd34: /* Mem Manage Address. */
258 case 0xd38: /* Bus Fault Address. */
259 case 0xd3c: /* Aux Fault Status. */
260 /* TODO: Implement fault status registers. */
261 qemu_log_mask(LOG_UNIMP, "Fault status registers unimplemented\n");
262 return 0;
263 case 0xd40: /* PFR0. */
264 return 0x00000030;
265 case 0xd44: /* PRF1. */
266 return 0x00000200;
267 case 0xd48: /* DFR0. */
268 return 0x00100000;
269 case 0xd4c: /* AFR0. */
270 return 0x00000000;
271 case 0xd50: /* MMFR0. */
272 return 0x00000030;
273 case 0xd54: /* MMFR1. */
274 return 0x00000000;
275 case 0xd58: /* MMFR2. */
276 return 0x00000000;
277 case 0xd5c: /* MMFR3. */
278 return 0x00000000;
279 case 0xd60: /* ISAR0. */
280 return 0x01141110;
281 case 0xd64: /* ISAR1. */
282 return 0x02111000;
283 case 0xd68: /* ISAR2. */
284 return 0x21112231;
285 case 0xd6c: /* ISAR3. */
286 return 0x01111110;
287 case 0xd70: /* ISAR4. */
288 return 0x01310102;
289 /* TODO: Implement debug registers. */
290 default:
291 qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset);
292 return 0;
293 }
294 }
295
296 static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value)
297 {
298 ARMCPU *cpu;
299 uint32_t oldval;
300 switch (offset) {
301 case 0x10: /* SysTick Control and Status. */
302 oldval = s->systick.control;
303 s->systick.control &= 0xfffffff8;
304 s->systick.control |= value & 7;
305 if ((oldval ^ value) & SYSTICK_ENABLE) {
306 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
307 if (value & SYSTICK_ENABLE) {
308 if (s->systick.tick) {
309 s->systick.tick += now;
310 timer_mod(s->systick.timer, s->systick.tick);
311 } else {
312 systick_reload(s, 1);
313 }
314 } else {
315 timer_del(s->systick.timer);
316 s->systick.tick -= now;
317 if (s->systick.tick < 0)
318 s->systick.tick = 0;
319 }
320 } else if ((oldval ^ value) & SYSTICK_CLKSOURCE) {
321 /* This is a hack. Force the timer to be reloaded
322 when the reference clock is changed. */
323 systick_reload(s, 1);
324 }
325 break;
326 case 0x14: /* SysTick Reload Value. */
327 s->systick.reload = value;
328 break;
329 case 0x18: /* SysTick Current Value. Writes reload the timer. */
330 systick_reload(s, 1);
331 s->systick.control &= ~SYSTICK_COUNTFLAG;
332 break;
333 case 0xd04: /* Interrupt Control State. */
334 if (value & (1 << 31)) {
335 armv7m_nvic_set_pending(s, ARMV7M_EXCP_NMI);
336 }
337 if (value & (1 << 28)) {
338 armv7m_nvic_set_pending(s, ARMV7M_EXCP_PENDSV);
339 } else if (value & (1 << 27)) {
340 s->gic.irq_state[ARMV7M_EXCP_PENDSV].pending = 0;
341 gic_update(&s->gic);
342 }
343 if (value & (1 << 26)) {
344 armv7m_nvic_set_pending(s, ARMV7M_EXCP_SYSTICK);
345 } else if (value & (1 << 25)) {
346 s->gic.irq_state[ARMV7M_EXCP_SYSTICK].pending = 0;
347 gic_update(&s->gic);
348 }
349 break;
350 case 0xd08: /* Vector Table Offset. */
351 cpu = ARM_CPU(current_cpu);
352 cpu->env.v7m.vecbase = value & 0xffffff80;
353 break;
354 case 0xd0c: /* Application Interrupt/Reset Control. */
355 if ((value >> 16) == 0x05fa) {
356 if (value & 4) {
357 qemu_irq_pulse(s->sysresetreq);
358 }
359 if (value & 2) {
360 qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n");
361 }
362 if (value & 1) {
363 qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n");
364 }
365 if (value & 0x700) {
366 qemu_log_mask(LOG_UNIMP, "PRIGROUP unimplemented\n");
367 }
368 }
369 break;
370 case 0xd10: /* System Control. */
371 case 0xd14: /* Configuration Control. */
372 /* TODO: Implement control registers. */
373 qemu_log_mask(LOG_UNIMP, "NVIC: SCR and CCR unimplemented\n");
374 break;
375 case 0xd24: /* System Handler Control. */
376 /* TODO: Real hardware allows you to set/clear the active bits
377 under some circumstances. We don't implement this. */
378 s->gic.irq_state[ARMV7M_EXCP_MEM].enabled = (value & (1 << 16)) != 0;
379 s->gic.irq_state[ARMV7M_EXCP_BUS].enabled = (value & (1 << 17)) != 0;
380 s->gic.irq_state[ARMV7M_EXCP_USAGE].enabled = (value & (1 << 18)) != 0;
381 break;
382 case 0xd28: /* Configurable Fault Status. */
383 case 0xd2c: /* Hard Fault Status. */
384 case 0xd30: /* Debug Fault Status. */
385 case 0xd34: /* Mem Manage Address. */
386 case 0xd38: /* Bus Fault Address. */
387 case 0xd3c: /* Aux Fault Status. */
388 qemu_log_mask(LOG_UNIMP,
389 "NVIC: fault status registers unimplemented\n");
390 break;
391 case 0xf00: /* Software Triggered Interrupt Register */
392 if ((value & 0x1ff) < s->num_irq) {
393 gic_set_pending_private(&s->gic, 0, value & 0x1ff);
394 }
395 break;
396 default:
397 qemu_log_mask(LOG_GUEST_ERROR,
398 "NVIC: Bad write offset 0x%x\n", offset);
399 }
400 }
401
402 static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr,
403 unsigned size)
404 {
405 nvic_state *s = (nvic_state *)opaque;
406 uint32_t offset = addr;
407 int i;
408 uint32_t val;
409
410 switch (offset) {
411 case 0xd18 ... 0xd23: /* System Handler Priority. */
412 val = 0;
413 for (i = 0; i < size; i++) {
414 val |= s->gic.priority1[(offset - 0xd14) + i][0] << (i * 8);
415 }
416 return val;
417 case 0xfe0 ... 0xfff: /* ID. */
418 if (offset & 3) {
419 return 0;
420 }
421 return nvic_id[(offset - 0xfe0) >> 2];
422 }
423 if (size == 4) {
424 return nvic_readl(s, offset);
425 }
426 qemu_log_mask(LOG_GUEST_ERROR,
427 "NVIC: Bad read of size %d at offset 0x%x\n", size, offset);
428 return 0;
429 }
430
431 static void nvic_sysreg_write(void *opaque, hwaddr addr,
432 uint64_t value, unsigned size)
433 {
434 nvic_state *s = (nvic_state *)opaque;
435 uint32_t offset = addr;
436 int i;
437
438 switch (offset) {
439 case 0xd18 ... 0xd23: /* System Handler Priority. */
440 for (i = 0; i < size; i++) {
441 s->gic.priority1[(offset - 0xd14) + i][0] =
442 (value >> (i * 8)) & 0xff;
443 }
444 gic_update(&s->gic);
445 return;
446 }
447 if (size == 4) {
448 nvic_writel(s, offset, value);
449 return;
450 }
451 qemu_log_mask(LOG_GUEST_ERROR,
452 "NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
453 }
454
455 static const MemoryRegionOps nvic_sysreg_ops = {
456 .read = nvic_sysreg_read,
457 .write = nvic_sysreg_write,
458 .endianness = DEVICE_NATIVE_ENDIAN,
459 };
460
461 static const VMStateDescription vmstate_nvic = {
462 .name = "armv7m_nvic",
463 .version_id = 1,
464 .minimum_version_id = 1,
465 .fields = (VMStateField[]) {
466 VMSTATE_UINT32(systick.control, nvic_state),
467 VMSTATE_UINT32(systick.reload, nvic_state),
468 VMSTATE_INT64(systick.tick, nvic_state),
469 VMSTATE_TIMER_PTR(systick.timer, nvic_state),
470 VMSTATE_END_OF_LIST()
471 }
472 };
473
474 static void armv7m_nvic_reset(DeviceState *dev)
475 {
476 nvic_state *s = NVIC(dev);
477 NVICClass *nc = NVIC_GET_CLASS(s);
478 nc->parent_reset(dev);
479 /* Common GIC reset resets to disabled; the NVIC doesn't have
480 * per-CPU interfaces so mark our non-existent CPU interface
481 * as enabled by default, and with a priority mask which allows
482 * all interrupts through.
483 */
484 s->gic.cpu_ctlr[0] = GICC_CTLR_EN_GRP0;
485 s->gic.priority_mask[0] = 0x100;
486 /* The NVIC as a whole is always enabled. */
487 s->gic.ctlr = 1;
488 systick_reset(s);
489 }
490
491 static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
492 {
493 nvic_state *s = NVIC(dev);
494 NVICClass *nc = NVIC_GET_CLASS(s);
495 Error *local_err = NULL;
496
497 /* The NVIC always has only one CPU */
498 s->gic.num_cpu = 1;
499 /* Tell the common code we're an NVIC */
500 s->gic.revision = 0xffffffff;
501 s->num_irq = s->gic.num_irq;
502 nc->parent_realize(dev, &local_err);
503 if (local_err) {
504 error_propagate(errp, local_err);
505 return;
506 }
507 gic_init_irqs_and_distributor(&s->gic);
508 /* The NVIC and system controller register area looks like this:
509 * 0..0xff : system control registers, including systick
510 * 0x100..0xcff : GIC-like registers
511 * 0xd00..0xfff : system control registers
512 * We use overlaying to put the GIC like registers
513 * over the top of the system control register region.
514 */
515 memory_region_init(&s->container, OBJECT(s), "nvic", 0x1000);
516 /* The system register region goes at the bottom of the priority
517 * stack as it covers the whole page.
518 */
519 memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
520 "nvic_sysregs", 0x1000);
521 memory_region_add_subregion(&s->container, 0, &s->sysregmem);
522 /* Alias the GIC region so we can get only the section of it
523 * we need, and layer it on top of the system register region.
524 */
525 memory_region_init_alias(&s->gic_iomem_alias, OBJECT(s),
526 "nvic-gic", &s->gic.iomem,
527 0x100, 0xc00);
528 memory_region_add_subregion_overlap(&s->container, 0x100,
529 &s->gic_iomem_alias, 1);
530 /* Map the whole thing into system memory at the location required
531 * by the v7M architecture.
532 */
533 memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->container);
534 s->systick.timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, systick_timer_tick, s);
535 }
536
537 static void armv7m_nvic_instance_init(Object *obj)
538 {
539 /* We have a different default value for the num-irq property
540 * than our superclass. This function runs after qdev init
541 * has set the defaults from the Property array and before
542 * any user-specified property setting, so just modify the
543 * value in the GICState struct.
544 */
545 GICState *s = ARM_GIC_COMMON(obj);
546 DeviceState *dev = DEVICE(obj);
547 nvic_state *nvic = NVIC(obj);
548 /* The ARM v7m may have anything from 0 to 496 external interrupt
549 * IRQ lines. We default to 64. Other boards may differ and should
550 * set the num-irq property appropriately.
551 */
552 s->num_irq = 64;
553 qdev_init_gpio_out_named(dev, &nvic->sysresetreq, "SYSRESETREQ", 1);
554 }
555
556 static void armv7m_nvic_class_init(ObjectClass *klass, void *data)
557 {
558 NVICClass *nc = NVIC_CLASS(klass);
559 DeviceClass *dc = DEVICE_CLASS(klass);
560
561 nc->parent_reset = dc->reset;
562 nc->parent_realize = dc->realize;
563 dc->vmsd = &vmstate_nvic;
564 dc->reset = armv7m_nvic_reset;
565 dc->realize = armv7m_nvic_realize;
566 }
567
568 static const TypeInfo armv7m_nvic_info = {
569 .name = TYPE_NVIC,
570 .parent = TYPE_ARM_GIC_COMMON,
571 .instance_init = armv7m_nvic_instance_init,
572 .instance_size = sizeof(nvic_state),
573 .class_init = armv7m_nvic_class_init,
574 .class_size = sizeof(NVICClass),
575 };
576
577 static void armv7m_nvic_register_types(void)
578 {
579 type_register_static(&armv7m_nvic_info);
580 }
581
582 type_init(armv7m_nvic_register_types)