hw/intc/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/intc/i8259.h"
  27 #include "hw/irq.h"
  28 #include "hw/isa/isa.h"
  29 #include "qemu/timer.h"
  30 #include "qemu/log.h"
  31 #include "hw/isa/i8259_internal.h"
  32 #include "trace.h"
  33 #include "qom/object.h"
  34
  35 /* debug PIC */
  36 //#define DEBUG_PIC
  37
  38 //#define DEBUG_IRQ_LATENCY
  39
  40 #define TYPE_I8259 "isa-i8259"
  41 typedef struct PICClass PICClass;
  42 DECLARE_CLASS_CHECKERS(PICClass, PIC,
  43                        TYPE_I8259)
  44
  45 /**
  46  * PICClass:
  47  * @parent_realize: The parent's realizefn.
  48  */
  49 struct PICClass {
  50     PICCommonClass parent_class;
  51
  52     DeviceRealize parent_realize;
  53 };
  54
  55 #ifdef DEBUG_IRQ_LATENCY
  56 static int64_t irq_time[16];
  57 #endif
  58 PICCommonState *isa_pic;
  59 static PICCommonState *slave_pic;
  60
  61 /* return the highest priority found in mask (highest = smallest
  62    number). Return 8 if no irq */
  63 static int get_priority(PICCommonState *s, int mask)
  64 {
  65     int priority;
  66
  67     if (mask == 0) {
  68         return 8;
  69     }
  70     priority = 0;
  71     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) {
  72         priority++;
  73     }
  74     return priority;
  75 }
  76
  77 /* return the pic wanted interrupt. return -1 if none */
  78 static int pic_get_irq(PICCommonState *s)
  79 {
  80     int mask, cur_priority, priority;
  81
  82     mask = s->irr & ~s->imr;
  83     priority = get_priority(s, mask);
  84     if (priority == 8) {
  85         return -1;
  86     }
  87     /* compute current priority. If special fully nested mode on the
  88        master, the IRQ coming from the slave is not taken into account
  89        for the priority computation. */
  90     mask = s->isr;
  91     if (s->special_mask) {
  92         mask &= ~s->imr;
  93     }
  94     if (s->special_fully_nested_mode && s->master) {
  95         mask &= ~(1 << 2);
  96     }
  97     cur_priority = get_priority(s, mask);
  98     if (priority < cur_priority) {
  99         /* higher priority found: an irq should be generated */
 100         return (priority + s->priority_add) & 7;
 101     } else {
 102         return -1;
 103     }
 104 }
 105
 106 /* Update INT output. Must be called every time the output may have changed. */
 107 static void pic_update_irq(PICCommonState *s)
 108 {
 109     int irq;
 110
 111     irq = pic_get_irq(s);
 112     if (irq >= 0) {
 113         trace_pic_update_irq(s->master, s->imr, s->irr, s->priority_add);
 114         qemu_irq_raise(s->int_out[0]);
 115     } else {
 116         qemu_irq_lower(s->int_out[0]);
 117     }
 118 }
 119
 120 /* set irq level. If an edge is detected, then the IRR is set to 1 */
 121 static void pic_set_irq(void *opaque, int irq, int level)
 122 {
 123     PICCommonState *s = opaque;
 124     int mask = 1 << irq;
 125     int irq_index = s->master ? irq : irq + 8;
 126
 127     trace_pic_set_irq(s->master, irq, level);
 128     pic_stat_update_irq(irq_index, level);
 129
 130 #ifdef DEBUG_IRQ_LATENCY
 131     if (level) {
 132         irq_time[irq_index] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 133     }
 134 #endif
 135
 136     if (s->elcr & mask) {
 137         /* level triggered */
 138         if (level) {
 139             s->irr |= mask;
 140             s->last_irr |= mask;
 141         } else {
 142             s->irr &= ~mask;
 143             s->last_irr &= ~mask;
 144         }
 145     } else {
 146         /* edge triggered */
 147         if (level) {
 148             if ((s->last_irr & mask) == 0) {
 149                 s->irr |= mask;
 150             }
 151             s->last_irr |= mask;
 152         } else {
 153             s->last_irr &= ~mask;
 154         }
 155     }
 156     pic_update_irq(s);
 157 }
 158
 159 /* acknowledge interrupt 'irq' */
 160 static void pic_intack(PICCommonState *s, int irq)
 161 {
 162     if (s->auto_eoi) {
 163         if (s->rotate_on_auto_eoi) {
 164             s->priority_add = (irq + 1) & 7;
 165         }
 166     } else {
 167         s->isr |= (1 << irq);
 168     }
 169     /* We don't clear a level sensitive interrupt here */
 170     if (!(s->elcr & (1 << irq))) {
 171         s->irr &= ~(1 << irq);
 172     }
 173     pic_update_irq(s);
 174 }
 175
 176 int pic_read_irq(PICCommonState *s)
 177 {
 178     int irq, intno;
 179
 180     irq = pic_get_irq(s);
 181     if (irq >= 0) {
 182         int irq2;
 183
 184         if (irq == 2) {
 185             irq2 = pic_get_irq(slave_pic);
 186             if (irq2 >= 0) {
 187                 pic_intack(slave_pic, irq2);
 188             } else {
 189                 /* spurious IRQ on slave controller */
 190                 irq2 = 7;
 191             }
 192             intno = slave_pic->irq_base + irq2;
 193             pic_intack(s, irq);
 194             irq = irq2 + 8;
 195         } else {
 196             intno = s->irq_base + irq;
 197             pic_intack(s, irq);
 198         }
 199     } else {
 200         /* spurious IRQ on host controller */
 201         irq = 7;
 202         intno = s->irq_base + irq;
 203     }
 204
 205 #ifdef DEBUG_IRQ_LATENCY
 206     printf("IRQ%d latency=%0.3fus\n",
 207            irq,
 208            (double)(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) -
 209                     irq_time[irq]) * 1000000.0 / NANOSECONDS_PER_SECOND);
 210 #endif
 211
 212     trace_pic_interrupt(irq, intno);
 213     return intno;
 214 }
 215
 216 static void pic_init_reset(PICCommonState *s)
 217 {
 218     pic_reset_common(s);
 219     pic_update_irq(s);
 220 }
 221
 222 static void pic_reset(DeviceState *dev)
 223 {
 224     PICCommonState *s = PIC_COMMON(dev);
 225
 226     s->elcr = 0;
 227     pic_init_reset(s);
 228 }
 229
 230 static void pic_ioport_write(void *opaque, hwaddr addr64,
 231                              uint64_t val64, unsigned size)
 232 {
 233     PICCommonState *s = opaque;
 234     uint32_t addr = addr64;
 235     uint32_t val = val64;
 236     int priority, cmd, irq;
 237
 238     trace_pic_ioport_write(s->master, addr, val);
 239
 240     if (addr == 0) {
 241         if (val & 0x10) {
 242             pic_init_reset(s);
 243             s->init_state = 1;
 244             s->init4 = val & 1;
 245             s->single_mode = val & 2;
 246             if (val & 0x08) {
 247                 qemu_log_mask(LOG_UNIMP,
 248                               "i8259: level sensitive irq not supported\n");
 249             }
 250         } else if (val & 0x08) {
 251             if (val & 0x04) {
 252                 s->poll = 1;
 253             }
 254             if (val & 0x02) {
 255                 s->read_reg_select = val & 1;
 256             }
 257             if (val & 0x40) {
 258                 s->special_mask = (val >> 5) & 1;
 259             }
 260         } else {
 261             cmd = val >> 5;
 262             switch (cmd) {
 263             case 0:
 264             case 4:
 265                 s->rotate_on_auto_eoi = cmd >> 2;
 266                 break;
 267             case 1: /* end of interrupt */
 268             case 5:
 269                 priority = get_priority(s, s->isr);
 270                 if (priority != 8) {
 271                     irq = (priority + s->priority_add) & 7;
 272                     s->isr &= ~(1 << irq);
 273                     if (cmd == 5) {
 274                         s->priority_add = (irq + 1) & 7;
 275                     }
 276                     pic_update_irq(s);
 277                 }
 278                 break;
 279             case 3:
 280                 irq = val & 7;
 281                 s->isr &= ~(1 << irq);
 282                 pic_update_irq(s);
 283                 break;
 284             case 6:
 285                 s->priority_add = (val + 1) & 7;
 286                 pic_update_irq(s);
 287                 break;
 288             case 7:
 289                 irq = val & 7;
 290                 s->isr &= ~(1 << irq);
 291                 s->priority_add = (irq + 1) & 7;
 292                 pic_update_irq(s);
 293                 break;
 294             default:
 295                 /* no operation */
 296                 break;
 297             }
 298         }
 299     } else {
 300         switch (s->init_state) {
 301         case 0:
 302             /* normal mode */
 303             s->imr = val;
 304             pic_update_irq(s);
 305             break;
 306         case 1:
 307             s->irq_base = val & 0xf8;
 308             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 309             break;
 310         case 2:
 311             if (s->init4) {
 312                 s->init_state = 3;
 313             } else {
 314                 s->init_state = 0;
 315             }
 316             break;
 317         case 3:
 318             s->special_fully_nested_mode = (val >> 4) & 1;
 319             s->auto_eoi = (val >> 1) & 1;
 320             s->init_state = 0;
 321             break;
 322         }
 323     }
 324 }
 325
 326 static uint64_t pic_ioport_read(void *opaque, hwaddr addr,
 327                                 unsigned size)
 328 {
 329     PICCommonState *s = opaque;
 330     int ret;
 331
 332     if (s->poll) {
 333         ret = pic_get_irq(s);
 334         if (ret >= 0) {
 335             pic_intack(s, ret);
 336             ret |= 0x80;
 337         } else {
 338             ret = 0;
 339         }
 340         s->poll = 0;
 341     } else {
 342         if (addr == 0) {
 343             if (s->read_reg_select) {
 344                 ret = s->isr;
 345             } else {
 346                 ret = s->irr;
 347             }
 348         } else {
 349             ret = s->imr;
 350         }
 351     }
 352     trace_pic_ioport_read(s->master, addr, ret);
 353     return ret;
 354 }
 355
 356 int pic_get_output(PICCommonState *s)
 357 {
 358     return (pic_get_irq(s) >= 0);
 359 }
 360
 361 static void elcr_ioport_write(void *opaque, hwaddr addr,
 362                               uint64_t val, unsigned size)
 363 {
 364     PICCommonState *s = opaque;
 365     s->elcr = val & s->elcr_mask;
 366 }
 367
 368 static uint64_t elcr_ioport_read(void *opaque, hwaddr addr,
 369                                  unsigned size)
 370 {
 371     PICCommonState *s = opaque;
 372     return s->elcr;
 373 }
 374
 375 static const MemoryRegionOps pic_base_ioport_ops = {
 376     .read = pic_ioport_read,
 377     .write = pic_ioport_write,
 378     .impl = {
 379         .min_access_size = 1,
 380         .max_access_size = 1,
 381     },
 382 };
 383
 384 static const MemoryRegionOps pic_elcr_ioport_ops = {
 385     .read = elcr_ioport_read,
 386     .write = elcr_ioport_write,
 387     .impl = {
 388         .min_access_size = 1,
 389         .max_access_size = 1,
 390     },
 391 };
 392
 393 static void pic_realize(DeviceState *dev, Error **errp)
 394 {
 395     PICCommonState *s = PIC_COMMON(dev);
 396     PICClass *pc = PIC_GET_CLASS(dev);
 397
 398     memory_region_init_io(&s->base_io, OBJECT(s), &pic_base_ioport_ops, s,
 399                           "pic", 2);
 400     memory_region_init_io(&s->elcr_io, OBJECT(s), &pic_elcr_ioport_ops, s,
 401                           "elcr", 1);
 402
 403     qdev_init_gpio_out(dev, s->int_out, ARRAY_SIZE(s->int_out));
 404     qdev_init_gpio_in(dev, pic_set_irq, 8);
 405
 406     pc->parent_realize(dev, errp);
 407 }
 408
 409 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq)
 410 {
 411     qemu_irq *irq_set;
 412     DeviceState *dev;
 413     ISADevice *isadev;
 414     int i;
 415
 416     irq_set = g_new0(qemu_irq, ISA_NUM_IRQS);
 417
 418     isadev = i8259_init_chip(TYPE_I8259, bus, true);
 419     dev = DEVICE(isadev);
 420
 421     qdev_connect_gpio_out(dev, 0, parent_irq);
 422     for (i = 0 ; i < 8; i++) {
 423         irq_set[i] = qdev_get_gpio_in(dev, i);
 424     }
 425
 426     isa_pic = PIC_COMMON(dev);
 427
 428     isadev = i8259_init_chip(TYPE_I8259, bus, false);
 429     dev = DEVICE(isadev);
 430
 431     qdev_connect_gpio_out(dev, 0, irq_set[2]);
 432     for (i = 0 ; i < 8; i++) {
 433         irq_set[i + 8] = qdev_get_gpio_in(dev, i);
 434     }
 435
 436     slave_pic = PIC_COMMON(dev);
 437
 438     return irq_set;
 439 }
 440
 441 static void i8259_class_init(ObjectClass *klass, void *data)
 442 {
 443     PICClass *k = PIC_CLASS(klass);
 444     DeviceClass *dc = DEVICE_CLASS(klass);
 445
 446     device_class_set_parent_realize(dc, pic_realize, &k->parent_realize);
 447     dc->reset = pic_reset;
 448 }
 449
 450 static const TypeInfo i8259_info = {
 451     .name       = TYPE_I8259,
 452     .instance_size = sizeof(PICCommonState),
 453     .parent     = TYPE_PIC_COMMON,
 454     .class_init = i8259_class_init,
 455     .class_size = sizeof(PICClass),
 456 };
 457
 458 static void pic_register_types(void)
 459 {
 460     type_register_static(&i8259_info);
 461 }
 462
 463 type_init(pic_register_types)