hw/intc/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "monitor/monitor.h"
  25 #include "hw/hw.h"
  26 #include "hw/i386/pc.h"
  27 #include "hw/i386/apic.h"
  28 #include "hw/i386/ioapic.h"
  29 #include "hw/i386/ioapic_internal.h"
  30 #include "include/hw/pci/msi.h"
  31 #include "sysemu/kvm.h"
  32 #include "target-i386/cpu.h"
  33 #include "hw/i386/apic-msidef.h"
  34 #include "hw/i386/x86-iommu.h"
  35
  36 //#define DEBUG_IOAPIC
  37
  38 #ifdef DEBUG_IOAPIC
  39 #define DPRINTF(fmt, ...)                                       \
  40     do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
  41 #else
  42 #define DPRINTF(fmt, ...)
  43 #endif
  44
  45 #define APIC_DELIVERY_MODE_SHIFT 8
  46 #define APIC_POLARITY_SHIFT 14
  47 #define APIC_TRIG_MODE_SHIFT 15
  48
  49 static IOAPICCommonState *ioapics[MAX_IOAPICS];
  50
  51 /* global variable from ioapic_common.c */
  52 extern int ioapic_no;
  53
  54 struct ioapic_entry_info {
  55     /* fields parsed from IOAPIC entries */
  56     uint8_t masked;
  57     uint8_t trig_mode;
  58     uint16_t dest_idx;
  59     uint8_t dest_mode;
  60     uint8_t delivery_mode;
  61     uint8_t vector;
  62
  63     /* MSI message generated from above parsed fields */
  64     uint32_t addr;
  65     uint32_t data;
  66 };
  67
  68 static void ioapic_entry_parse(uint64_t entry, struct ioapic_entry_info *info)
  69 {
  70     memset(info, 0, sizeof(*info));
  71     info->masked = (entry >> IOAPIC_LVT_MASKED_SHIFT) & 1;
  72     info->trig_mode = (entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1;
  73     /*
  74      * By default, this would be dest_id[8] + reserved[8]. When IR
  75      * is enabled, this would be interrupt_index[15] +
  76      * interrupt_format[1]. This field never means anything, but
  77      * only used to generate corresponding MSI.
  78      */
  79     info->dest_idx = (entry >> IOAPIC_LVT_DEST_IDX_SHIFT) & 0xffff;
  80     info->dest_mode = (entry >> IOAPIC_LVT_DEST_MODE_SHIFT) & 1;
  81     info->delivery_mode = (entry >> IOAPIC_LVT_DELIV_MODE_SHIFT) \
  82         & IOAPIC_DM_MASK;
  83     if (info->delivery_mode == IOAPIC_DM_EXTINT) {
  84         info->vector = pic_read_irq(isa_pic);
  85     } else {
  86         info->vector = entry & IOAPIC_VECTOR_MASK;
  87     }
  88
  89     info->addr = APIC_DEFAULT_ADDRESS | \
  90         (info->dest_idx << MSI_ADDR_DEST_IDX_SHIFT) | \
  91         (info->dest_mode << MSI_ADDR_DEST_MODE_SHIFT);
  92     info->data = (info->vector << MSI_DATA_VECTOR_SHIFT) | \
  93         (info->trig_mode << MSI_DATA_TRIGGER_SHIFT) | \
  94         (info->delivery_mode << MSI_DATA_DELIVERY_MODE_SHIFT);
  95 }
  96
  97 static void ioapic_service(IOAPICCommonState *s)
  98 {
  99     AddressSpace *ioapic_as = PC_MACHINE(qdev_get_machine())->ioapic_as;
 100     struct ioapic_entry_info info;
 101     uint8_t i;
 102     uint32_t mask;
 103     uint64_t entry;
 104
 105     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 106         mask = 1 << i;
 107         if (s->irr & mask) {
 108             int coalesce = 0;
 109
 110             entry = s->ioredtbl[i];
 111             ioapic_entry_parse(entry, &info);
 112             if (!info.masked) {
 113                 if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
 114                     s->irr &= ~mask;
 115                 } else {
 116                     coalesce = s->ioredtbl[i] & IOAPIC_LVT_REMOTE_IRR;
 117                     s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
 118                 }
 119
 120 #ifdef CONFIG_KVM
 121                 if (kvm_irqchip_is_split()) {
 122                     if (info.trig_mode == IOAPIC_TRIGGER_EDGE) {
 123                         kvm_set_irq(kvm_state, i, 1);
 124                         kvm_set_irq(kvm_state, i, 0);
 125                     } else {
 126                         if (!coalesce) {
 127                             kvm_set_irq(kvm_state, i, 1);
 128                         }
 129                     }
 130                     continue;
 131                 }
 132 #else
 133                 (void)coalesce;
 134 #endif
 135                 /* No matter whether IR is enabled, we translate
 136                  * the IOAPIC message into a MSI one, and its
 137                  * address space will decide whether we need a
 138                  * translation. */
 139                 stl_le_phys(ioapic_as, info.addr, info.data);
 140             }
 141         }
 142     }
 143 }
 144
 145 static void ioapic_set_irq(void *opaque, int vector, int level)
 146 {
 147     IOAPICCommonState *s = opaque;
 148
 149     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
 150      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
 151      * the cleanest way of doing it but it should work. */
 152
 153     DPRINTF("%s: %s vec %x\n", __func__, level ? "raise" : "lower", vector);
 154     if (vector == 0) {
 155         vector = 2;
 156     }
 157     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 158         uint32_t mask = 1 << vector;
 159         uint64_t entry = s->ioredtbl[vector];
 160
 161         if (((entry >> IOAPIC_LVT_TRIGGER_MODE_SHIFT) & 1) ==
 162             IOAPIC_TRIGGER_LEVEL) {
 163             /* level triggered */
 164             if (level) {
 165                 s->irr |= mask;
 166                 if (!(entry & IOAPIC_LVT_REMOTE_IRR)) {
 167                     ioapic_service(s);
 168                 }
 169             } else {
 170                 s->irr &= ~mask;
 171             }
 172         } else {
 173             /* According to the 82093AA manual, we must ignore edge requests
 174              * if the input pin is masked. */
 175             if (level && !(entry & IOAPIC_LVT_MASKED)) {
 176                 s->irr |= mask;
 177                 ioapic_service(s);
 178             }
 179         }
 180     }
 181 }
 182
 183 static void ioapic_update_kvm_routes(IOAPICCommonState *s)
 184 {
 185 #ifdef CONFIG_KVM
 186     int i;
 187
 188     if (kvm_irqchip_is_split()) {
 189         for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 190             MSIMessage msg;
 191             struct ioapic_entry_info info;
 192             ioapic_entry_parse(s->ioredtbl[i], &info);
 193             msg.address = info.addr;
 194             msg.data = info.data;
 195             kvm_irqchip_update_msi_route(kvm_state, i, msg, NULL);
 196         }
 197         kvm_irqchip_commit_routes(kvm_state);
 198     }
 199 #endif
 200 }
 201
 202 #ifdef CONFIG_KVM
 203 static void ioapic_iec_notifier(void *private, bool global,
 204                                 uint32_t index, uint32_t mask)
 205 {
 206     IOAPICCommonState *s = (IOAPICCommonState *)private;
 207     /* For simplicity, we just update all the routes */
 208     ioapic_update_kvm_routes(s);
 209 }
 210 #endif
 211
 212 void ioapic_eoi_broadcast(int vector)
 213 {
 214     IOAPICCommonState *s;
 215     uint64_t entry;
 216     int i, n;
 217
 218     for (i = 0; i < MAX_IOAPICS; i++) {
 219         s = ioapics[i];
 220         if (!s) {
 221             continue;
 222         }
 223         for (n = 0; n < IOAPIC_NUM_PINS; n++) {
 224             entry = s->ioredtbl[n];
 225             if ((entry & IOAPIC_LVT_REMOTE_IRR)
 226                 && (entry & IOAPIC_VECTOR_MASK) == vector) {
 227                 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
 228                 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
 229                     ioapic_service(s);
 230                 }
 231             }
 232         }
 233     }
 234 }
 235
 236 void ioapic_dump_state(Monitor *mon, const QDict *qdict)
 237 {
 238     int i;
 239
 240     for (i = 0; i < MAX_IOAPICS; i++) {
 241         if (ioapics[i] != 0) {
 242             ioapic_print_redtbl(mon, ioapics[i]);
 243         }
 244     }
 245 }
 246
 247 static uint64_t
 248 ioapic_mem_read(void *opaque, hwaddr addr, unsigned int size)
 249 {
 250     IOAPICCommonState *s = opaque;
 251     int index;
 252     uint32_t val = 0;
 253
 254     switch (addr & 0xff) {
 255     case IOAPIC_IOREGSEL:
 256         val = s->ioregsel;
 257         break;
 258     case IOAPIC_IOWIN:
 259         if (size != 4) {
 260             break;
 261         }
 262         switch (s->ioregsel) {
 263         case IOAPIC_REG_ID:
 264         case IOAPIC_REG_ARB:
 265             val = s->id << IOAPIC_ID_SHIFT;
 266             break;
 267         case IOAPIC_REG_VER:
 268             val = IOAPIC_VERSION |
 269                 ((IOAPIC_NUM_PINS - 1) << IOAPIC_VER_ENTRIES_SHIFT);
 270             break;
 271         default:
 272             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 273             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 274                 if (s->ioregsel & 1) {
 275                     val = s->ioredtbl[index] >> 32;
 276                 } else {
 277                     val = s->ioredtbl[index] & 0xffffffff;
 278                 }
 279             }
 280         }
 281         DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
 282         break;
 283     }
 284     return val;
 285 }
 286
 287 /*
 288  * This is to satisfy the hack in Linux kernel. One hack of it is to
 289  * simulate clearing the Remote IRR bit of IOAPIC entry using the
 290  * following:
 291  *
 292  * "For IO-APIC's with EOI register, we use that to do an explicit EOI.
 293  * Otherwise, we simulate the EOI message manually by changing the trigger
 294  * mode to edge and then back to level, with RTE being masked during
 295  * this."
 296  *
 297  * (See linux kernel __eoi_ioapic_pin() comment in commit c0205701)
 298  *
 299  * This is based on the assumption that, Remote IRR bit will be
 300  * cleared by IOAPIC hardware when configured as edge-triggered
 301  * interrupts.
 302  *
 303  * Without this, level-triggered interrupts in IR mode might fail to
 304  * work correctly.
 305  */
 306 static inline void
 307 ioapic_fix_edge_remote_irr(uint64_t *entry)
 308 {
 309     if (!(*entry & IOAPIC_LVT_TRIGGER_MODE)) {
 310         /* Edge-triggered interrupts, make sure remote IRR is zero */
 311         *entry &= ~((uint64_t)IOAPIC_LVT_REMOTE_IRR);
 312     }
 313 }
 314
 315 static void
 316 ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
 317                  unsigned int size)
 318 {
 319     IOAPICCommonState *s = opaque;
 320     int index;
 321
 322     switch (addr & 0xff) {
 323     case IOAPIC_IOREGSEL:
 324         s->ioregsel = val;
 325         break;
 326     case IOAPIC_IOWIN:
 327         if (size != 4) {
 328             break;
 329         }
 330         DPRINTF("write: %08x = %08" PRIx64 "\n", s->ioregsel, val);
 331         switch (s->ioregsel) {
 332         case IOAPIC_REG_ID:
 333             s->id = (val >> IOAPIC_ID_SHIFT) & IOAPIC_ID_MASK;
 334             break;
 335         case IOAPIC_REG_VER:
 336         case IOAPIC_REG_ARB:
 337             break;
 338         default:
 339             index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
 340             if (index >= 0 && index < IOAPIC_NUM_PINS) {
 341                 uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS;
 342                 if (s->ioregsel & 1) {
 343                     s->ioredtbl[index] &= 0xffffffff;
 344                     s->ioredtbl[index] |= (uint64_t)val << 32;
 345                 } else {
 346                     s->ioredtbl[index] &= ~0xffffffffULL;
 347                     s->ioredtbl[index] |= val;
 348                 }
 349                 /* restore RO bits */
 350                 s->ioredtbl[index] &= IOAPIC_RW_BITS;
 351                 s->ioredtbl[index] |= ro_bits;
 352                 ioapic_fix_edge_remote_irr(&s->ioredtbl[index]);
 353                 ioapic_service(s);
 354             }
 355         }
 356         break;
 357     }
 358
 359     ioapic_update_kvm_routes(s);
 360 }
 361
 362 static const MemoryRegionOps ioapic_io_ops = {
 363     .read = ioapic_mem_read,
 364     .write = ioapic_mem_write,
 365     .endianness = DEVICE_NATIVE_ENDIAN,
 366 };
 367
 368 static void ioapic_machine_done_notify(Notifier *notifier, void *data)
 369 {
 370 #ifdef CONFIG_KVM
 371     IOAPICCommonState *s = container_of(notifier, IOAPICCommonState,
 372                                         machine_done);
 373
 374     if (kvm_irqchip_is_split()) {
 375         X86IOMMUState *iommu = x86_iommu_get_default();
 376         if (iommu) {
 377             /* Register this IOAPIC with IOMMU IEC notifier, so that
 378              * when there are IR invalidates, we can be notified to
 379              * update kernel IR cache. */
 380             x86_iommu_iec_register_notifier(iommu, ioapic_iec_notifier, s);
 381         }
 382     }
 383 #endif
 384 }
 385
 386 static void ioapic_realize(DeviceState *dev, Error **errp)
 387 {
 388     IOAPICCommonState *s = IOAPIC_COMMON(dev);
 389
 390     memory_region_init_io(&s->io_memory, OBJECT(s), &ioapic_io_ops, s,
 391                           "ioapic", 0x1000);
 392
 393     qdev_init_gpio_in(dev, ioapic_set_irq, IOAPIC_NUM_PINS);
 394
 395     ioapics[ioapic_no] = s;
 396     s->machine_done.notify = ioapic_machine_done_notify;
 397     qemu_add_machine_init_done_notifier(&s->machine_done);
 398 }
 399
 400 static void ioapic_class_init(ObjectClass *klass, void *data)
 401 {
 402     IOAPICCommonClass *k = IOAPIC_COMMON_CLASS(klass);
 403     DeviceClass *dc = DEVICE_CLASS(klass);
 404
 405     k->realize = ioapic_realize;
 406     dc->reset = ioapic_reset_common;
 407 }
 408
 409 static const TypeInfo ioapic_info = {
 410     .name          = "ioapic",
 411     .parent        = TYPE_IOAPIC_COMMON,
 412     .instance_size = sizeof(IOAPICCommonState),
 413     .class_init    = ioapic_class_init,
 414 };
 415
 416 static void ioapic_register_types(void)
 417 {
 418     type_register_static(&ioapic_info);
 419 }
 420
 421 type_init(ioapic_register_types)