hw/intc/ioapic_common.c

   1 /*
   2  *  IOAPIC emulation logic - common bits of emulated and KVM kernel model
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2009      Xiantao Zhang, Intel
   6  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   7  *
   8  * This library is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU Lesser General Public
  10  * License as published by the Free Software Foundation; either
  11  * version 2 of the License, or (at your option) any later version.
  12  *
  13  * This library is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * Lesser General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU Lesser General Public
  19  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "qapi/error.h"
  24 #include "monitor/monitor.h"
  25 #include "hw/i386/ioapic.h"
  26 #include "hw/i386/ioapic_internal.h"
  27 #include "hw/intc/intc.h"
  28 #include "hw/sysbus.h"
  29
  30 /* ioapic_no count start from 0 to MAX_IOAPICS,
  31  * remove as static variable from ioapic_common_init.
  32  * now as a global variable, let child to increase the counter
  33  * then we can drop the 'instance_no' argument
  34  * and convert to our QOM's realize function
  35  */
  36 int ioapic_no;
  37
  38 void ioapic_stat_update_irq(IOAPICCommonState *s, int irq, int level)
  39 {
  40     if (level != s->irq_level[irq]) {
  41         s->irq_level[irq] = level;
  42         if (level == 1) {
  43             s->irq_count[irq]++;
  44         }
  45     }
  46 }
  47
  48 static bool ioapic_get_statistics(InterruptStatsProvider *obj,
  49                                   uint64_t **irq_counts,
  50                                   unsigned int *nb_irqs)
  51 {
  52     IOAPICCommonState *s = IOAPIC_COMMON(obj);
  53
  54     *irq_counts = s->irq_count;
  55     *nb_irqs = IOAPIC_NUM_PINS;
  56
  57     return true;
  58 }
  59
  60 static void ioapic_irr_dump(Monitor *mon, const char *name, uint32_t bitmap)
  61 {
  62     int i;
  63
  64     monitor_printf(mon, "%-10s ", name);
  65     if (bitmap == 0) {
  66         monitor_printf(mon, "(none)\n");
  67         return;
  68     }
  69     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  70         if (bitmap & (1 << i)) {
  71             monitor_printf(mon, "%-2u ", i);
  72         }
  73     }
  74     monitor_printf(mon, "\n");
  75 }
  76
  77 void ioapic_print_redtbl(Monitor *mon, IOAPICCommonState *s)
  78 {
  79     static const char *delm_str[] = {
  80         "fixed", "lowest", "SMI", "...", "NMI", "INIT", "...", "extINT"};
  81     uint32_t remote_irr = 0;
  82     int i;
  83
  84     monitor_printf(mon, "ioapic0: ver=0x%x id=0x%02x sel=0x%02x",
  85                    s->version, s->id, s->ioregsel);
  86     if (s->ioregsel) {
  87         monitor_printf(mon, " (redir[%u])\n",
  88                        (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1);
  89     } else {
  90         monitor_printf(mon, "\n");
  91     }
  92     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  93         uint64_t entry = s->ioredtbl[i];
  94         uint32_t delm = (uint32_t)((entry & IOAPIC_LVT_DELIV_MODE) >>
  95                                    IOAPIC_LVT_DELIV_MODE_SHIFT);
  96         monitor_printf(mon, "  pin %-2u 0x%016"PRIx64" dest=%"PRIx64
  97                        " vec=%-3"PRIu64" %s %-5s %-6s %-6s %s\n",
  98                        i, entry,
  99                        (entry >> IOAPIC_LVT_DEST_SHIFT) &
 100                             (entry & IOAPIC_LVT_DEST_MODE ? 0xff : 0xf),
 101                        entry & IOAPIC_VECTOR_MASK,
 102                        entry & IOAPIC_LVT_POLARITY ? "active-lo" : "active-hi",
 103                        entry & IOAPIC_LVT_TRIGGER_MODE ? "level" : "edge",
 104                        entry & IOAPIC_LVT_MASKED ? "masked" : "",
 105                        delm_str[delm],
 106                        entry & IOAPIC_LVT_DEST_MODE ? "logical" : "physical");
 107
 108         remote_irr |= entry & IOAPIC_LVT_TRIGGER_MODE ?
 109                         (entry & IOAPIC_LVT_REMOTE_IRR ? (1 << i) : 0) : 0;
 110     }
 111     ioapic_irr_dump(mon, "  IRR", s->irr);
 112     ioapic_irr_dump(mon, "  Remote IRR", remote_irr);
 113 }
 114
 115 void ioapic_reset_common(DeviceState *dev)
 116 {
 117     IOAPICCommonState *s = IOAPIC_COMMON(dev);
 118     int i;
 119
 120     s->id = 0;
 121     s->ioregsel = 0;
 122     s->irr = 0;
 123     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 124         s->ioredtbl[i] = 1 << IOAPIC_LVT_MASKED_SHIFT;
 125     }
 126 }
 127
 128 static int ioapic_dispatch_pre_save(void *opaque)
 129 {
 130     IOAPICCommonState *s = IOAPIC_COMMON(opaque);
 131     IOAPICCommonClass *info = IOAPIC_COMMON_GET_CLASS(s);
 132
 133     if (info->pre_save) {
 134         info->pre_save(s);
 135     }
 136
 137     return 0;
 138 }
 139
 140 static int ioapic_dispatch_post_load(void *opaque, int version_id)
 141 {
 142     IOAPICCommonState *s = IOAPIC_COMMON(opaque);
 143     IOAPICCommonClass *info = IOAPIC_COMMON_GET_CLASS(s);
 144
 145     if (info->post_load) {
 146         info->post_load(s);
 147     }
 148     return 0;
 149 }
 150
 151 static void ioapic_common_realize(DeviceState *dev, Error **errp)
 152 {
 153     IOAPICCommonState *s = IOAPIC_COMMON(dev);
 154     IOAPICCommonClass *info;
 155
 156     if (ioapic_no >= MAX_IOAPICS) {
 157         error_setg(errp, "Only %d ioapics allowed", MAX_IOAPICS);
 158         return;
 159     }
 160
 161     info = IOAPIC_COMMON_GET_CLASS(s);
 162     info->realize(dev, errp);
 163
 164     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io_memory);
 165     ioapic_no++;
 166 }
 167
 168 static void ioapic_print_info(InterruptStatsProvider *obj,
 169                               Monitor *mon)
 170 {
 171     IOAPICCommonState *s = IOAPIC_COMMON(obj);
 172
 173     ioapic_dispatch_pre_save(s);
 174     ioapic_print_redtbl(mon, s);
 175 }
 176
 177 static const VMStateDescription vmstate_ioapic_common = {
 178     .name = "ioapic",
 179     .version_id = 3,
 180     .minimum_version_id = 1,
 181     .pre_save = ioapic_dispatch_pre_save,
 182     .post_load = ioapic_dispatch_post_load,
 183     .fields = (VMStateField[]) {
 184         VMSTATE_UINT8(id, IOAPICCommonState),
 185         VMSTATE_UINT8(ioregsel, IOAPICCommonState),
 186         VMSTATE_UNUSED_V(2, 8), /* to account for qemu-kvm's v2 format */
 187         VMSTATE_UINT32_V(irr, IOAPICCommonState, 2),
 188         VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICCommonState, IOAPIC_NUM_PINS),
 189         VMSTATE_END_OF_LIST()
 190     }
 191 };
 192
 193 static void ioapic_common_class_init(ObjectClass *klass, void *data)
 194 {
 195     DeviceClass *dc = DEVICE_CLASS(klass);
 196     InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass);
 197
 198     dc->realize = ioapic_common_realize;
 199     dc->vmsd = &vmstate_ioapic_common;
 200     ic->print_info = ioapic_print_info;
 201     ic->get_statistics = ioapic_get_statistics;
 202 }
 203
 204 static const TypeInfo ioapic_common_type = {
 205     .name = TYPE_IOAPIC_COMMON,
 206     .parent = TYPE_SYS_BUS_DEVICE,
 207     .instance_size = sizeof(IOAPICCommonState),
 208     .class_size = sizeof(IOAPICCommonClass),
 209     .class_init = ioapic_common_class_init,
 210     .abstract = true,
 211     .interfaces = (InterfaceInfo[]) {
 212         { TYPE_INTERRUPT_STATS_PROVIDER },
 213         { }
 214     },
 215 };
 216
 217 static void ioapic_common_register_types(void)
 218 {
 219     type_register_static(&ioapic_common_type);
 220 }
 221
 222 type_init(ioapic_common_register_types)