hw/intc/omap_intc.c

   1 /*
   2  * TI OMAP interrupt controller emulation.
   3  *
   4  * Copyright (C) 2006-2008 Andrzej Zaborowski  <balrog@zabor.org>
   5  * Copyright (C) 2007-2008 Nokia Corporation
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 or
  10  * (at your option) version 3 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/hw.h"
  23 #include "hw/arm/omap.h"
  24 #include "hw/sysbus.h"
  25 #include "qemu/error-report.h"
  26 #include "qemu/module.h"
  27 #include "qapi/error.h"
  28
  29 /* Interrupt Handlers */
  30 struct omap_intr_handler_bank_s {
  31     uint32_t irqs;
  32     uint32_t inputs;
  33     uint32_t mask;
  34     uint32_t fiq;
  35     uint32_t sens_edge;
  36     uint32_t swi;
  37     unsigned char priority[32];
  38 };
  39
  40 #define TYPE_OMAP_INTC "common-omap-intc"
  41 #define OMAP_INTC(obj) \
  42     OBJECT_CHECK(struct omap_intr_handler_s, (obj), TYPE_OMAP_INTC)
  43
  44 struct omap_intr_handler_s {
  45     SysBusDevice parent_obj;
  46
  47     qemu_irq *pins;
  48     qemu_irq parent_intr[2];
  49     MemoryRegion mmio;
  50     void *iclk;
  51     void *fclk;
  52     unsigned char nbanks;
  53     int level_only;
  54     uint32_t size;
  55
  56     uint8_t revision;
  57
  58     /* state */
  59     uint32_t new_agr[2];
  60     int sir_intr[2];
  61     int autoidle;
  62     uint32_t mask;
  63     struct omap_intr_handler_bank_s bank[3];
  64 };
  65
  66 static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
  67 {
  68     int i, j, sir_intr, p_intr, p;
  69     uint32_t level;
  70     sir_intr = 0;
  71     p_intr = 255;
  72
  73     /* Find the interrupt line with the highest dynamic priority.
  74      * Note: 0 denotes the hightest priority.
  75      * If all interrupts have the same priority, the default order is IRQ_N,
  76      * IRQ_N-1,...,IRQ_0. */
  77     for (j = 0; j < s->nbanks; ++j) {
  78         level = s->bank[j].irqs & ~s->bank[j].mask &
  79                 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq);
  80
  81         while (level != 0) {
  82             i = ctz32(level);
  83             p = s->bank[j].priority[i];
  84             if (p <= p_intr) {
  85                 p_intr = p;
  86                 sir_intr = 32 * j + i;
  87             }
  88             level &= level - 1;
  89         }
  90     }
  91     s->sir_intr[is_fiq] = sir_intr;
  92 }
  93
  94 static inline void omap_inth_update(struct omap_intr_handler_s *s, int is_fiq)
  95 {
  96     int i;
  97     uint32_t has_intr = 0;
  98
  99     for (i = 0; i < s->nbanks; ++i)
 100         has_intr |= s->bank[i].irqs & ~s->bank[i].mask &
 101                 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq);
 102
 103     if (s->new_agr[is_fiq] & has_intr & s->mask) {
 104         s->new_agr[is_fiq] = 0;
 105         omap_inth_sir_update(s, is_fiq);
 106         qemu_set_irq(s->parent_intr[is_fiq], 1);
 107     }
 108 }
 109
 110 #define INT_FALLING_EDGE        0
 111 #define INT_LOW_LEVEL           1
 112
 113 static void omap_set_intr(void *opaque, int irq, int req)
 114 {
 115     struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
 116     uint32_t rise;
 117
 118     struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
 119     int n = irq & 31;
 120
 121     if (req) {
 122         rise = ~bank->irqs & (1 << n);
 123         if (~bank->sens_edge & (1 << n))
 124             rise &= ~bank->inputs;
 125
 126         bank->inputs |= (1 << n);
 127         if (rise) {
 128             bank->irqs |= rise;
 129             omap_inth_update(ih, 0);
 130             omap_inth_update(ih, 1);
 131         }
 132     } else {
 133         rise = bank->sens_edge & bank->irqs & (1 << n);
 134         bank->irqs &= ~rise;
 135         bank->inputs &= ~(1 << n);
 136     }
 137 }
 138
 139 /* Simplified version with no edge detection */
 140 static void omap_set_intr_noedge(void *opaque, int irq, int req)
 141 {
 142     struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
 143     uint32_t rise;
 144
 145     struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5];
 146     int n = irq & 31;
 147
 148     if (req) {
 149         rise = ~bank->inputs & (1 << n);
 150         if (rise) {
 151             bank->irqs |= bank->inputs |= rise;
 152             omap_inth_update(ih, 0);
 153             omap_inth_update(ih, 1);
 154         }
 155     } else
 156         bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
 157 }
 158
 159 static uint64_t omap_inth_read(void *opaque, hwaddr addr,
 160                                unsigned size)
 161 {
 162     struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
 163     int i, offset = addr;
 164     int bank_no = offset >> 8;
 165     int line_no;
 166     struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
 167     offset &= 0xff;
 168
 169     switch (offset) {
 170     case 0x00:  /* ITR */
 171         return bank->irqs;
 172
 173     case 0x04:  /* MIR */
 174         return bank->mask;
 175
 176     case 0x10:  /* SIR_IRQ_CODE */
 177     case 0x14:  /* SIR_FIQ_CODE */
 178         if (bank_no != 0)
 179             break;
 180         line_no = s->sir_intr[(offset - 0x10) >> 2];
 181         bank = &s->bank[line_no >> 5];
 182         i = line_no & 31;
 183         if (((bank->sens_edge >> i) & 1) == INT_FALLING_EDGE)
 184             bank->irqs &= ~(1 << i);
 185         return line_no;
 186
 187     case 0x18:  /* CONTROL_REG */
 188         if (bank_no != 0)
 189             break;
 190         return 0;
 191
 192     case 0x1c:  /* ILR0 */
 193     case 0x20:  /* ILR1 */
 194     case 0x24:  /* ILR2 */
 195     case 0x28:  /* ILR3 */
 196     case 0x2c:  /* ILR4 */
 197     case 0x30:  /* ILR5 */
 198     case 0x34:  /* ILR6 */
 199     case 0x38:  /* ILR7 */
 200     case 0x3c:  /* ILR8 */
 201     case 0x40:  /* ILR9 */
 202     case 0x44:  /* ILR10 */
 203     case 0x48:  /* ILR11 */
 204     case 0x4c:  /* ILR12 */
 205     case 0x50:  /* ILR13 */
 206     case 0x54:  /* ILR14 */
 207     case 0x58:  /* ILR15 */
 208     case 0x5c:  /* ILR16 */
 209     case 0x60:  /* ILR17 */
 210     case 0x64:  /* ILR18 */
 211     case 0x68:  /* ILR19 */
 212     case 0x6c:  /* ILR20 */
 213     case 0x70:  /* ILR21 */
 214     case 0x74:  /* ILR22 */
 215     case 0x78:  /* ILR23 */
 216     case 0x7c:  /* ILR24 */
 217     case 0x80:  /* ILR25 */
 218     case 0x84:  /* ILR26 */
 219     case 0x88:  /* ILR27 */
 220     case 0x8c:  /* ILR28 */
 221     case 0x90:  /* ILR29 */
 222     case 0x94:  /* ILR30 */
 223     case 0x98:  /* ILR31 */
 224         i = (offset - 0x1c) >> 2;
 225         return (bank->priority[i] << 2) |
 226                 (((bank->sens_edge >> i) & 1) << 1) |
 227                 ((bank->fiq >> i) & 1);
 228
 229     case 0x9c:  /* ISR */
 230         return 0x00000000;
 231
 232     }
 233     OMAP_BAD_REG(addr);
 234     return 0;
 235 }
 236
 237 static void omap_inth_write(void *opaque, hwaddr addr,
 238                             uint64_t value, unsigned size)
 239 {
 240     struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
 241     int i, offset = addr;
 242     int bank_no = offset >> 8;
 243     struct omap_intr_handler_bank_s *bank = &s->bank[bank_no];
 244     offset &= 0xff;
 245
 246     switch (offset) {
 247     case 0x00:  /* ITR */
 248         /* Important: ignore the clearing if the IRQ is level-triggered and
 249            the input bit is 1 */
 250         bank->irqs &= value | (bank->inputs & bank->sens_edge);
 251         return;
 252
 253     case 0x04:  /* MIR */
 254         bank->mask = value;
 255         omap_inth_update(s, 0);
 256         omap_inth_update(s, 1);
 257         return;
 258
 259     case 0x10:  /* SIR_IRQ_CODE */
 260     case 0x14:  /* SIR_FIQ_CODE */
 261         OMAP_RO_REG(addr);
 262         break;
 263
 264     case 0x18:  /* CONTROL_REG */
 265         if (bank_no != 0)
 266             break;
 267         if (value & 2) {
 268             qemu_set_irq(s->parent_intr[1], 0);
 269             s->new_agr[1] = ~0;
 270             omap_inth_update(s, 1);
 271         }
 272         if (value & 1) {
 273             qemu_set_irq(s->parent_intr[0], 0);
 274             s->new_agr[0] = ~0;
 275             omap_inth_update(s, 0);
 276         }
 277         return;
 278
 279     case 0x1c:  /* ILR0 */
 280     case 0x20:  /* ILR1 */
 281     case 0x24:  /* ILR2 */
 282     case 0x28:  /* ILR3 */
 283     case 0x2c:  /* ILR4 */
 284     case 0x30:  /* ILR5 */
 285     case 0x34:  /* ILR6 */
 286     case 0x38:  /* ILR7 */
 287     case 0x3c:  /* ILR8 */
 288     case 0x40:  /* ILR9 */
 289     case 0x44:  /* ILR10 */
 290     case 0x48:  /* ILR11 */
 291     case 0x4c:  /* ILR12 */
 292     case 0x50:  /* ILR13 */
 293     case 0x54:  /* ILR14 */
 294     case 0x58:  /* ILR15 */
 295     case 0x5c:  /* ILR16 */
 296     case 0x60:  /* ILR17 */
 297     case 0x64:  /* ILR18 */
 298     case 0x68:  /* ILR19 */
 299     case 0x6c:  /* ILR20 */
 300     case 0x70:  /* ILR21 */
 301     case 0x74:  /* ILR22 */
 302     case 0x78:  /* ILR23 */
 303     case 0x7c:  /* ILR24 */
 304     case 0x80:  /* ILR25 */
 305     case 0x84:  /* ILR26 */
 306     case 0x88:  /* ILR27 */
 307     case 0x8c:  /* ILR28 */
 308     case 0x90:  /* ILR29 */
 309     case 0x94:  /* ILR30 */
 310     case 0x98:  /* ILR31 */
 311         i = (offset - 0x1c) >> 2;
 312         bank->priority[i] = (value >> 2) & 0x1f;
 313         bank->sens_edge &= ~(1 << i);
 314         bank->sens_edge |= ((value >> 1) & 1) << i;
 315         bank->fiq &= ~(1 << i);
 316         bank->fiq |= (value & 1) << i;
 317         return;
 318
 319     case 0x9c:  /* ISR */
 320         for (i = 0; i < 32; i ++)
 321             if (value & (1 << i)) {
 322                 omap_set_intr(s, 32 * bank_no + i, 1);
 323                 return;
 324             }
 325         return;
 326     }
 327     OMAP_BAD_REG(addr);
 328 }
 329
 330 static const MemoryRegionOps omap_inth_mem_ops = {
 331     .read = omap_inth_read,
 332     .write = omap_inth_write,
 333     .endianness = DEVICE_NATIVE_ENDIAN,
 334     .valid = {
 335         .min_access_size = 4,
 336         .max_access_size = 4,
 337     },
 338 };
 339
 340 static void omap_inth_reset(DeviceState *dev)
 341 {
 342     struct omap_intr_handler_s *s = OMAP_INTC(dev);
 343     int i;
 344
 345     for (i = 0; i < s->nbanks; ++i){
 346         s->bank[i].irqs = 0x00000000;
 347         s->bank[i].mask = 0xffffffff;
 348         s->bank[i].sens_edge = 0x00000000;
 349         s->bank[i].fiq = 0x00000000;
 350         s->bank[i].inputs = 0x00000000;
 351         s->bank[i].swi = 0x00000000;
 352         memset(s->bank[i].priority, 0, sizeof(s->bank[i].priority));
 353
 354         if (s->level_only)
 355             s->bank[i].sens_edge = 0xffffffff;
 356     }
 357
 358     s->new_agr[0] = ~0;
 359     s->new_agr[1] = ~0;
 360     s->sir_intr[0] = 0;
 361     s->sir_intr[1] = 0;
 362     s->autoidle = 0;
 363     s->mask = ~0;
 364
 365     qemu_set_irq(s->parent_intr[0], 0);
 366     qemu_set_irq(s->parent_intr[1], 0);
 367 }
 368
 369 static void omap_intc_init(Object *obj)
 370 {
 371     DeviceState *dev = DEVICE(obj);
 372     struct omap_intr_handler_s *s = OMAP_INTC(obj);
 373     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 374
 375     s->nbanks = 1;
 376     sysbus_init_irq(sbd, &s->parent_intr[0]);
 377     sysbus_init_irq(sbd, &s->parent_intr[1]);
 378     qdev_init_gpio_in(dev, omap_set_intr, s->nbanks * 32);
 379     memory_region_init_io(&s->mmio, obj, &omap_inth_mem_ops, s,
 380                           "omap-intc", s->size);
 381     sysbus_init_mmio(sbd, &s->mmio);
 382 }
 383
 384 static void omap_intc_realize(DeviceState *dev, Error **errp)
 385 {
 386     struct omap_intr_handler_s *s = OMAP_INTC(dev);
 387
 388     if (!s->iclk) {
 389         error_setg(errp, "omap-intc: clk not connected");
 390     }
 391 }
 392
 393 static Property omap_intc_properties[] = {
 394     DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
 395     DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk),
 396     DEFINE_PROP_END_OF_LIST(),
 397 };
 398
 399 static void omap_intc_class_init(ObjectClass *klass, void *data)
 400 {
 401     DeviceClass *dc = DEVICE_CLASS(klass);
 402
 403     dc->reset = omap_inth_reset;
 404     dc->props = omap_intc_properties;
 405     /* Reason: pointer property "clk" */
 406     dc->user_creatable = false;
 407     dc->realize = omap_intc_realize;
 408 }
 409
 410 static const TypeInfo omap_intc_info = {
 411     .name          = "omap-intc",
 412     .parent        = TYPE_OMAP_INTC,
 413     .instance_init = omap_intc_init,
 414     .class_init    = omap_intc_class_init,
 415 };
 416
 417 static uint64_t omap2_inth_read(void *opaque, hwaddr addr,
 418                                 unsigned size)
 419 {
 420     struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
 421     int offset = addr;
 422     int bank_no, line_no;
 423     struct omap_intr_handler_bank_s *bank = NULL;
 424
 425     if ((offset & 0xf80) == 0x80) {
 426         bank_no = (offset & 0x60) >> 5;
 427         if (bank_no < s->nbanks) {
 428             offset &= ~0x60;
 429             bank = &s->bank[bank_no];
 430         } else {
 431             OMAP_BAD_REG(addr);
 432             return 0;
 433         }
 434     }
 435
 436     switch (offset) {
 437     case 0x00:  /* INTC_REVISION */
 438         return s->revision;
 439
 440     case 0x10:  /* INTC_SYSCONFIG */
 441         return (s->autoidle >> 2) & 1;
 442
 443     case 0x14:  /* INTC_SYSSTATUS */
 444         return 1;                                               /* RESETDONE */
 445
 446     case 0x40:  /* INTC_SIR_IRQ */
 447         return s->sir_intr[0];
 448
 449     case 0x44:  /* INTC_SIR_FIQ */
 450         return s->sir_intr[1];
 451
 452     case 0x48:  /* INTC_CONTROL */
 453         return (!s->mask) << 2;                                 /* GLOBALMASK */
 454
 455     case 0x4c:  /* INTC_PROTECTION */
 456         return 0;
 457
 458     case 0x50:  /* INTC_IDLE */
 459         return s->autoidle & 3;
 460
 461     /* Per-bank registers */
 462     case 0x80:  /* INTC_ITR */
 463         return bank->inputs;
 464
 465     case 0x84:  /* INTC_MIR */
 466         return bank->mask;
 467
 468     case 0x88:  /* INTC_MIR_CLEAR */
 469     case 0x8c:  /* INTC_MIR_SET */
 470         return 0;
 471
 472     case 0x90:  /* INTC_ISR_SET */
 473         return bank->swi;
 474
 475     case 0x94:  /* INTC_ISR_CLEAR */
 476         return 0;
 477
 478     case 0x98:  /* INTC_PENDING_IRQ */
 479         return bank->irqs & ~bank->mask & ~bank->fiq;
 480
 481     case 0x9c:  /* INTC_PENDING_FIQ */
 482         return bank->irqs & ~bank->mask & bank->fiq;
 483
 484     /* Per-line registers */
 485     case 0x100 ... 0x300:       /* INTC_ILR */
 486         bank_no = (offset - 0x100) >> 7;
 487         if (bank_no > s->nbanks)
 488             break;
 489         bank = &s->bank[bank_no];
 490         line_no = (offset & 0x7f) >> 2;
 491         return (bank->priority[line_no] << 2) |
 492                 ((bank->fiq >> line_no) & 1);
 493     }
 494     OMAP_BAD_REG(addr);
 495     return 0;
 496 }
 497
 498 static void omap2_inth_write(void *opaque, hwaddr addr,
 499                              uint64_t value, unsigned size)
 500 {
 501     struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
 502     int offset = addr;
 503     int bank_no, line_no;
 504     struct omap_intr_handler_bank_s *bank = NULL;
 505
 506     if ((offset & 0xf80) == 0x80) {
 507         bank_no = (offset & 0x60) >> 5;
 508         if (bank_no < s->nbanks) {
 509             offset &= ~0x60;
 510             bank = &s->bank[bank_no];
 511         } else {
 512             OMAP_BAD_REG(addr);
 513             return;
 514         }
 515     }
 516
 517     switch (offset) {
 518     case 0x10:  /* INTC_SYSCONFIG */
 519         s->autoidle &= 4;
 520         s->autoidle |= (value & 1) << 2;
 521         if (value & 2) {                                        /* SOFTRESET */
 522             omap_inth_reset(DEVICE(s));
 523         }
 524         return;
 525
 526     case 0x48:  /* INTC_CONTROL */
 527         s->mask = (value & 4) ? 0 : ~0;                         /* GLOBALMASK */
 528         if (value & 2) {                                        /* NEWFIQAGR */
 529             qemu_set_irq(s->parent_intr[1], 0);
 530             s->new_agr[1] = ~0;
 531             omap_inth_update(s, 1);
 532         }
 533         if (value & 1) {                                        /* NEWIRQAGR */
 534             qemu_set_irq(s->parent_intr[0], 0);
 535             s->new_agr[0] = ~0;
 536             omap_inth_update(s, 0);
 537         }
 538         return;
 539
 540     case 0x4c:  /* INTC_PROTECTION */
 541         /* TODO: Make a bitmap (or sizeof(char)map) of access privileges
 542          * for every register, see Chapter 3 and 4 for privileged mode.  */
 543         if (value & 1)
 544             fprintf(stderr, "%s: protection mode enable attempt\n",
 545                             __func__);
 546         return;
 547
 548     case 0x50:  /* INTC_IDLE */
 549         s->autoidle &= ~3;
 550         s->autoidle |= value & 3;
 551         return;
 552
 553     /* Per-bank registers */
 554     case 0x84:  /* INTC_MIR */
 555         bank->mask = value;
 556         omap_inth_update(s, 0);
 557         omap_inth_update(s, 1);
 558         return;
 559
 560     case 0x88:  /* INTC_MIR_CLEAR */
 561         bank->mask &= ~value;
 562         omap_inth_update(s, 0);
 563         omap_inth_update(s, 1);
 564         return;
 565
 566     case 0x8c:  /* INTC_MIR_SET */
 567         bank->mask |= value;
 568         return;
 569
 570     case 0x90:  /* INTC_ISR_SET */
 571         bank->irqs |= bank->swi |= value;
 572         omap_inth_update(s, 0);
 573         omap_inth_update(s, 1);
 574         return;
 575
 576     case 0x94:  /* INTC_ISR_CLEAR */
 577         bank->swi &= ~value;
 578         bank->irqs = bank->swi & bank->inputs;
 579         return;
 580
 581     /* Per-line registers */
 582     case 0x100 ... 0x300:       /* INTC_ILR */
 583         bank_no = (offset - 0x100) >> 7;
 584         if (bank_no > s->nbanks)
 585             break;
 586         bank = &s->bank[bank_no];
 587         line_no = (offset & 0x7f) >> 2;
 588         bank->priority[line_no] = (value >> 2) & 0x3f;
 589         bank->fiq &= ~(1 << line_no);
 590         bank->fiq |= (value & 1) << line_no;
 591         return;
 592
 593     case 0x00:  /* INTC_REVISION */
 594     case 0x14:  /* INTC_SYSSTATUS */
 595     case 0x40:  /* INTC_SIR_IRQ */
 596     case 0x44:  /* INTC_SIR_FIQ */
 597     case 0x80:  /* INTC_ITR */
 598     case 0x98:  /* INTC_PENDING_IRQ */
 599     case 0x9c:  /* INTC_PENDING_FIQ */
 600         OMAP_RO_REG(addr);
 601         return;
 602     }
 603     OMAP_BAD_REG(addr);
 604 }
 605
 606 static const MemoryRegionOps omap2_inth_mem_ops = {
 607     .read = omap2_inth_read,
 608     .write = omap2_inth_write,
 609     .endianness = DEVICE_NATIVE_ENDIAN,
 610     .valid = {
 611         .min_access_size = 4,
 612         .max_access_size = 4,
 613     },
 614 };
 615
 616 static void omap2_intc_init(Object *obj)
 617 {
 618     DeviceState *dev = DEVICE(obj);
 619     struct omap_intr_handler_s *s = OMAP_INTC(obj);
 620     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 621
 622     s->level_only = 1;
 623     s->nbanks = 3;
 624     sysbus_init_irq(sbd, &s->parent_intr[0]);
 625     sysbus_init_irq(sbd, &s->parent_intr[1]);
 626     qdev_init_gpio_in(dev, omap_set_intr_noedge, s->nbanks * 32);
 627     memory_region_init_io(&s->mmio, obj, &omap2_inth_mem_ops, s,
 628                           "omap2-intc", 0x1000);
 629     sysbus_init_mmio(sbd, &s->mmio);
 630 }
 631
 632 static void omap2_intc_realize(DeviceState *dev, Error **errp)
 633 {
 634     struct omap_intr_handler_s *s = OMAP_INTC(dev);
 635
 636     if (!s->iclk) {
 637         error_setg(errp, "omap2-intc: iclk not connected");
 638         return;
 639     }
 640     if (!s->fclk) {
 641         error_setg(errp, "omap2-intc: fclk not connected");
 642         return;
 643     }
 644 }
 645
 646 static Property omap2_intc_properties[] = {
 647     DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
 648     revision, 0x21),
 649     DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk),
 650     DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk),
 651     DEFINE_PROP_END_OF_LIST(),
 652 };
 653
 654 static void omap2_intc_class_init(ObjectClass *klass, void *data)
 655 {
 656     DeviceClass *dc = DEVICE_CLASS(klass);
 657
 658     dc->reset = omap_inth_reset;
 659     dc->props = omap2_intc_properties;
 660     /* Reason: pointer property "iclk", "fclk" */
 661     dc->user_creatable = false;
 662     dc->realize = omap2_intc_realize;
 663 }
 664
 665 static const TypeInfo omap2_intc_info = {
 666     .name          = "omap2-intc",
 667     .parent        = TYPE_OMAP_INTC,
 668     .instance_init = omap2_intc_init,
 669     .class_init    = omap2_intc_class_init,
 670 };
 671
 672 static const TypeInfo omap_intc_type_info = {
 673     .name          = TYPE_OMAP_INTC,
 674     .parent        = TYPE_SYS_BUS_DEVICE,
 675     .instance_size = sizeof(struct omap_intr_handler_s),
 676     .abstract      = true,
 677 };
 678
 679 static void omap_intc_register_types(void)
 680 {
 681     type_register_static(&omap_intc_type_info);
 682     type_register_static(&omap_intc_info);
 683     type_register_static(&omap2_intc_info);
 684 }
 685
 686 type_init(omap_intc_register_types)