2 * QEMU PowerPC XIVE interrupt controller model
4 * Copyright (c) 2017-2019, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "sysemu/dma.h"
17 #include "sysemu/reset.h"
18 #include "monitor/monitor.h"
19 #include "hw/ppc/fdt.h"
20 #include "hw/ppc/pnv.h"
21 #include "hw/ppc/pnv_core.h"
22 #include "hw/ppc/pnv_xscom.h"
23 #include "hw/ppc/pnv_xive.h"
24 #include "hw/ppc/xive_regs.h"
25 #include "hw/qdev-properties.h"
26 #include "hw/ppc/ppc.h"
30 #include "pnv_xive_regs.h"
35 * Virtual structures table (VST)
37 #define SBE_PER_BYTE 4
39 typedef struct XiveVstInfo
{
45 static const XiveVstInfo vst_infos
[] = {
46 [VST_TSEL_IVT
] = { "EAT", sizeof(XiveEAS
), 16 },
47 [VST_TSEL_SBE
] = { "SBE", 1, 16 },
48 [VST_TSEL_EQDT
] = { "ENDT", sizeof(XiveEND
), 16 },
49 [VST_TSEL_VPDT
] = { "VPDT", sizeof(XiveNVT
), 32 },
52 * Interrupt fifo backing store table (not modeled) :
57 * 3 - Second escalate,
59 * 5 - IPI cascaded queue ?
61 [VST_TSEL_IRQ
] = { "IRQ", 1, 6 },
64 #define xive_error(xive, fmt, ...) \
65 qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \
66 (xive)->chip->chip_id, ## __VA_ARGS__);
69 * QEMU version of the GETFIELD/SETFIELD macros
71 * TODO: It might be better to use the existing extract64() and
72 * deposit64() but this means that all the register definitions will
73 * change and become incompatible with the ones found in skiboot.
75 * Keep it as it is for now until we find a common ground.
77 static inline uint64_t GETFIELD(uint64_t mask
, uint64_t word
)
79 return (word
& mask
) >> ctz64(mask
);
82 static inline uint64_t SETFIELD(uint64_t mask
, uint64_t word
,
85 return (word
& ~mask
) | ((value
<< ctz64(mask
)) & mask
);
89 * Remote access to controllers. HW uses MMIOs. For now, a simple scan
90 * of the chips is good enough.
92 * TODO: Block scope support
94 static PnvXive
*pnv_xive_get_ic(uint8_t blk
)
96 PnvMachineState
*pnv
= PNV_MACHINE(qdev_get_machine());
99 for (i
= 0; i
< pnv
->num_chips
; i
++) {
100 Pnv9Chip
*chip9
= PNV9_CHIP(pnv
->chips
[i
]);
101 PnvXive
*xive
= &chip9
->xive
;
103 if (xive
->chip
->chip_id
== blk
) {
111 * VST accessors for SBE, EAT, ENDT, NVT
113 * Indirect VST tables are arrays of VSDs pointing to a page (of same
114 * size). Each page is a direct VST table.
117 #define XIVE_VSD_SIZE 8
119 /* Indirect page size can be 4K, 64K, 2M, 16M. */
120 static uint64_t pnv_xive_vst_page_size_allowed(uint32_t page_shift
)
122 return page_shift
== 12 || page_shift
== 16 ||
123 page_shift
== 21 || page_shift
== 24;
126 static uint64_t pnv_xive_vst_size(uint64_t vsd
)
128 uint64_t vst_tsize
= 1ull << (GETFIELD(VSD_TSIZE
, vsd
) + 12);
131 * Read the first descriptor to get the page size of the indirect
134 if (VSD_INDIRECT
& vsd
) {
135 uint32_t nr_pages
= vst_tsize
/ XIVE_VSD_SIZE
;
138 vsd
= ldq_be_dma(&address_space_memory
, vsd
& VSD_ADDRESS_MASK
);
139 page_shift
= GETFIELD(VSD_TSIZE
, vsd
) + 12;
141 if (!pnv_xive_vst_page_size_allowed(page_shift
)) {
145 return nr_pages
* (1ull << page_shift
);
151 static uint64_t pnv_xive_vst_addr_direct(PnvXive
*xive
, uint32_t type
,
152 uint64_t vsd
, uint32_t idx
)
154 const XiveVstInfo
*info
= &vst_infos
[type
];
155 uint64_t vst_addr
= vsd
& VSD_ADDRESS_MASK
;
157 return vst_addr
+ idx
* info
->size
;
160 static uint64_t pnv_xive_vst_addr_indirect(PnvXive
*xive
, uint32_t type
,
161 uint64_t vsd
, uint32_t idx
)
163 const XiveVstInfo
*info
= &vst_infos
[type
];
167 uint32_t vst_per_page
;
169 /* Get the page size of the indirect table. */
170 vsd_addr
= vsd
& VSD_ADDRESS_MASK
;
171 vsd
= ldq_be_dma(&address_space_memory
, vsd_addr
);
173 if (!(vsd
& VSD_ADDRESS_MASK
)) {
174 xive_error(xive
, "VST: invalid %s entry %x !?", info
->name
, idx
);
178 page_shift
= GETFIELD(VSD_TSIZE
, vsd
) + 12;
180 if (!pnv_xive_vst_page_size_allowed(page_shift
)) {
181 xive_error(xive
, "VST: invalid %s page shift %d", info
->name
,
186 vst_per_page
= (1ull << page_shift
) / info
->size
;
187 vsd_idx
= idx
/ vst_per_page
;
189 /* Load the VSD we are looking for, if not already done */
191 vsd_addr
= vsd_addr
+ vsd_idx
* XIVE_VSD_SIZE
;
192 vsd
= ldq_be_dma(&address_space_memory
, vsd_addr
);
194 if (!(vsd
& VSD_ADDRESS_MASK
)) {
195 xive_error(xive
, "VST: invalid %s entry %x !?", info
->name
, idx
);
200 * Check that the pages have a consistent size across the
203 if (page_shift
!= GETFIELD(VSD_TSIZE
, vsd
) + 12) {
204 xive_error(xive
, "VST: %s entry %x indirect page size differ !?",
210 return pnv_xive_vst_addr_direct(xive
, type
, vsd
, (idx
% vst_per_page
));
213 static uint64_t pnv_xive_vst_addr(PnvXive
*xive
, uint32_t type
, uint8_t blk
,
216 const XiveVstInfo
*info
= &vst_infos
[type
];
220 if (blk
>= info
->max_blocks
) {
221 xive_error(xive
, "VST: invalid block id %d for VST %s %d !?",
222 blk
, info
->name
, idx
);
226 vsd
= xive
->vsds
[type
][blk
];
228 /* Remote VST access */
229 if (GETFIELD(VSD_MODE
, vsd
) == VSD_MODE_FORWARD
) {
230 xive
= pnv_xive_get_ic(blk
);
232 return xive
? pnv_xive_vst_addr(xive
, type
, blk
, idx
) : 0;
235 idx_max
= pnv_xive_vst_size(vsd
) / info
->size
- 1;
238 xive_error(xive
, "VST: %s entry %x/%x out of range [ 0 .. %x ] !?",
239 info
->name
, blk
, idx
, idx_max
);
244 if (VSD_INDIRECT
& vsd
) {
245 return pnv_xive_vst_addr_indirect(xive
, type
, vsd
, idx
);
248 return pnv_xive_vst_addr_direct(xive
, type
, vsd
, idx
);
251 static int pnv_xive_vst_read(PnvXive
*xive
, uint32_t type
, uint8_t blk
,
252 uint32_t idx
, void *data
)
254 const XiveVstInfo
*info
= &vst_infos
[type
];
255 uint64_t addr
= pnv_xive_vst_addr(xive
, type
, blk
, idx
);
261 cpu_physical_memory_read(addr
, data
, info
->size
);
265 #define XIVE_VST_WORD_ALL -1
267 static int pnv_xive_vst_write(PnvXive
*xive
, uint32_t type
, uint8_t blk
,
268 uint32_t idx
, void *data
, uint32_t word_number
)
270 const XiveVstInfo
*info
= &vst_infos
[type
];
271 uint64_t addr
= pnv_xive_vst_addr(xive
, type
, blk
, idx
);
277 if (word_number
== XIVE_VST_WORD_ALL
) {
278 cpu_physical_memory_write(addr
, data
, info
->size
);
280 cpu_physical_memory_write(addr
+ word_number
* 4,
281 data
+ word_number
* 4, 4);
286 static int pnv_xive_get_end(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
289 return pnv_xive_vst_read(PNV_XIVE(xrtr
), VST_TSEL_EQDT
, blk
, idx
, end
);
292 static int pnv_xive_write_end(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
293 XiveEND
*end
, uint8_t word_number
)
295 return pnv_xive_vst_write(PNV_XIVE(xrtr
), VST_TSEL_EQDT
, blk
, idx
, end
,
299 static int pnv_xive_end_update(PnvXive
*xive
)
301 uint8_t blk
= GETFIELD(VC_EQC_CWATCH_BLOCKID
,
302 xive
->regs
[(VC_EQC_CWATCH_SPEC
>> 3)]);
303 uint32_t idx
= GETFIELD(VC_EQC_CWATCH_OFFSET
,
304 xive
->regs
[(VC_EQC_CWATCH_SPEC
>> 3)]);
306 uint64_t eqc_watch
[4];
308 for (i
= 0; i
< ARRAY_SIZE(eqc_watch
); i
++) {
309 eqc_watch
[i
] = cpu_to_be64(xive
->regs
[(VC_EQC_CWATCH_DAT0
>> 3) + i
]);
312 return pnv_xive_vst_write(xive
, VST_TSEL_EQDT
, blk
, idx
, eqc_watch
,
316 static void pnv_xive_end_cache_load(PnvXive
*xive
)
318 uint8_t blk
= GETFIELD(VC_EQC_CWATCH_BLOCKID
,
319 xive
->regs
[(VC_EQC_CWATCH_SPEC
>> 3)]);
320 uint32_t idx
= GETFIELD(VC_EQC_CWATCH_OFFSET
,
321 xive
->regs
[(VC_EQC_CWATCH_SPEC
>> 3)]);
322 uint64_t eqc_watch
[4] = { 0 };
325 if (pnv_xive_vst_read(xive
, VST_TSEL_EQDT
, blk
, idx
, eqc_watch
)) {
326 xive_error(xive
, "VST: no END entry %x/%x !?", blk
, idx
);
329 for (i
= 0; i
< ARRAY_SIZE(eqc_watch
); i
++) {
330 xive
->regs
[(VC_EQC_CWATCH_DAT0
>> 3) + i
] = be64_to_cpu(eqc_watch
[i
]);
334 static int pnv_xive_get_nvt(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
337 return pnv_xive_vst_read(PNV_XIVE(xrtr
), VST_TSEL_VPDT
, blk
, idx
, nvt
);
340 static int pnv_xive_write_nvt(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
341 XiveNVT
*nvt
, uint8_t word_number
)
343 return pnv_xive_vst_write(PNV_XIVE(xrtr
), VST_TSEL_VPDT
, blk
, idx
, nvt
,
347 static int pnv_xive_nvt_update(PnvXive
*xive
)
349 uint8_t blk
= GETFIELD(PC_VPC_CWATCH_BLOCKID
,
350 xive
->regs
[(PC_VPC_CWATCH_SPEC
>> 3)]);
351 uint32_t idx
= GETFIELD(PC_VPC_CWATCH_OFFSET
,
352 xive
->regs
[(PC_VPC_CWATCH_SPEC
>> 3)]);
354 uint64_t vpc_watch
[8];
356 for (i
= 0; i
< ARRAY_SIZE(vpc_watch
); i
++) {
357 vpc_watch
[i
] = cpu_to_be64(xive
->regs
[(PC_VPC_CWATCH_DAT0
>> 3) + i
]);
360 return pnv_xive_vst_write(xive
, VST_TSEL_VPDT
, blk
, idx
, vpc_watch
,
364 static void pnv_xive_nvt_cache_load(PnvXive
*xive
)
366 uint8_t blk
= GETFIELD(PC_VPC_CWATCH_BLOCKID
,
367 xive
->regs
[(PC_VPC_CWATCH_SPEC
>> 3)]);
368 uint32_t idx
= GETFIELD(PC_VPC_CWATCH_OFFSET
,
369 xive
->regs
[(PC_VPC_CWATCH_SPEC
>> 3)]);
370 uint64_t vpc_watch
[8] = { 0 };
373 if (pnv_xive_vst_read(xive
, VST_TSEL_VPDT
, blk
, idx
, vpc_watch
)) {
374 xive_error(xive
, "VST: no NVT entry %x/%x !?", blk
, idx
);
377 for (i
= 0; i
< ARRAY_SIZE(vpc_watch
); i
++) {
378 xive
->regs
[(PC_VPC_CWATCH_DAT0
>> 3) + i
] = be64_to_cpu(vpc_watch
[i
]);
382 static int pnv_xive_get_eas(XiveRouter
*xrtr
, uint8_t blk
, uint32_t idx
,
385 PnvXive
*xive
= PNV_XIVE(xrtr
);
387 if (pnv_xive_get_ic(blk
) != xive
) {
388 xive_error(xive
, "VST: EAS %x is remote !?", XIVE_EAS(blk
, idx
));
392 return pnv_xive_vst_read(xive
, VST_TSEL_IVT
, blk
, idx
, eas
);
395 static XiveTCTX
*pnv_xive_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
)
397 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
398 XiveTCTX
*tctx
= XIVE_TCTX(pnv_cpu_state(cpu
)->intc
);
399 PnvXive
*xive
= NULL
;
400 CPUPPCState
*env
= &cpu
->env
;
401 int pir
= env
->spr_cb
[SPR_PIR
].default_value
;
404 * Perform an extra check on the HW thread enablement.
406 * The TIMA is shared among the chips and to identify the chip
407 * from which the access is being done, we extract the chip id
410 xive
= pnv_xive_get_ic((pir
>> 8) & 0xf);
415 if (!(xive
->regs
[PC_THREAD_EN_REG0
>> 3] & PPC_BIT(pir
& 0x3f))) {
416 xive_error(PNV_XIVE(xrtr
), "IC: CPU %x is not enabled", pir
);
423 * The internal sources (IPIs) of the interrupt controller have no
424 * knowledge of the XIVE chip on which they reside. Encode the block
425 * id in the source interrupt number before forwarding the source
426 * event notification to the Router. This is required on a multichip
429 static void pnv_xive_notify(XiveNotifier
*xn
, uint32_t srcno
)
431 PnvXive
*xive
= PNV_XIVE(xn
);
432 uint8_t blk
= xive
->chip
->chip_id
;
434 xive_router_notify(xn
, XIVE_EAS(blk
, srcno
));
441 static uint64_t pnv_xive_vc_size(PnvXive
*xive
)
443 return (~xive
->regs
[CQ_VC_BARM
>> 3] + 1) & CQ_VC_BARM_MASK
;
446 static uint64_t pnv_xive_edt_shift(PnvXive
*xive
)
448 return ctz64(pnv_xive_vc_size(xive
) / XIVE_TABLE_EDT_MAX
);
451 static uint64_t pnv_xive_pc_size(PnvXive
*xive
)
453 return (~xive
->regs
[CQ_PC_BARM
>> 3] + 1) & CQ_PC_BARM_MASK
;
456 static uint32_t pnv_xive_nr_ipis(PnvXive
*xive
)
458 uint8_t blk
= xive
->chip
->chip_id
;
460 return pnv_xive_vst_size(xive
->vsds
[VST_TSEL_SBE
][blk
]) * SBE_PER_BYTE
;
463 static uint32_t pnv_xive_nr_ends(PnvXive
*xive
)
465 uint8_t blk
= xive
->chip
->chip_id
;
467 return pnv_xive_vst_size(xive
->vsds
[VST_TSEL_EQDT
][blk
])
468 / vst_infos
[VST_TSEL_EQDT
].size
;
474 * The Virtualization Controller MMIO region containing the IPI ESB
475 * pages and END ESB pages is sub-divided into "sets" which map
476 * portions of the VC region to the different ESB pages. It is
477 * configured at runtime through the EDT "Domain Table" to let the
478 * firmware decide how to split the VC address space between IPI ESB
479 * pages and END ESB pages.
483 * Computes the overall size of the IPI or the END ESB pages
485 static uint64_t pnv_xive_edt_size(PnvXive
*xive
, uint64_t type
)
487 uint64_t edt_size
= 1ull << pnv_xive_edt_shift(xive
);
491 for (i
= 0; i
< XIVE_TABLE_EDT_MAX
; i
++) {
492 uint64_t edt_type
= GETFIELD(CQ_TDR_EDT_TYPE
, xive
->edt
[i
]);
494 if (edt_type
== type
) {
503 * Maps an offset of the VC region in the IPI or END region using the
504 * layout defined by the EDT "Domaine Table"
506 static uint64_t pnv_xive_edt_offset(PnvXive
*xive
, uint64_t vc_offset
,
510 uint64_t edt_size
= 1ull << pnv_xive_edt_shift(xive
);
511 uint64_t edt_offset
= vc_offset
;
513 for (i
= 0; i
< XIVE_TABLE_EDT_MAX
&& (i
* edt_size
) < vc_offset
; i
++) {
514 uint64_t edt_type
= GETFIELD(CQ_TDR_EDT_TYPE
, xive
->edt
[i
]);
516 if (edt_type
!= type
) {
517 edt_offset
-= edt_size
;
524 static void pnv_xive_edt_resize(PnvXive
*xive
)
526 uint64_t ipi_edt_size
= pnv_xive_edt_size(xive
, CQ_TDR_EDT_IPI
);
527 uint64_t end_edt_size
= pnv_xive_edt_size(xive
, CQ_TDR_EDT_EQ
);
529 memory_region_set_size(&xive
->ipi_edt_mmio
, ipi_edt_size
);
530 memory_region_add_subregion(&xive
->ipi_mmio
, 0, &xive
->ipi_edt_mmio
);
532 memory_region_set_size(&xive
->end_edt_mmio
, end_edt_size
);
533 memory_region_add_subregion(&xive
->end_mmio
, 0, &xive
->end_edt_mmio
);
537 * XIVE Table configuration. Only EDT is supported.
539 static int pnv_xive_table_set_data(PnvXive
*xive
, uint64_t val
)
541 uint64_t tsel
= xive
->regs
[CQ_TAR
>> 3] & CQ_TAR_TSEL
;
542 uint8_t tsel_index
= GETFIELD(CQ_TAR_TSEL_INDEX
, xive
->regs
[CQ_TAR
>> 3]);
543 uint64_t *xive_table
;
547 case CQ_TAR_TSEL_BLK
:
548 max_index
= ARRAY_SIZE(xive
->blk
);
549 xive_table
= xive
->blk
;
551 case CQ_TAR_TSEL_MIG
:
552 max_index
= ARRAY_SIZE(xive
->mig
);
553 xive_table
= xive
->mig
;
555 case CQ_TAR_TSEL_EDT
:
556 max_index
= ARRAY_SIZE(xive
->edt
);
557 xive_table
= xive
->edt
;
559 case CQ_TAR_TSEL_VDT
:
560 max_index
= ARRAY_SIZE(xive
->vdt
);
561 xive_table
= xive
->vdt
;
564 xive_error(xive
, "IC: invalid table %d", (int) tsel
);
568 if (tsel_index
>= max_index
) {
569 xive_error(xive
, "IC: invalid index %d", (int) tsel_index
);
573 xive_table
[tsel_index
] = val
;
575 if (xive
->regs
[CQ_TAR
>> 3] & CQ_TAR_TBL_AUTOINC
) {
576 xive
->regs
[CQ_TAR
>> 3] =
577 SETFIELD(CQ_TAR_TSEL_INDEX
, xive
->regs
[CQ_TAR
>> 3], ++tsel_index
);
581 * EDT configuration is complete. Resize the MMIO windows exposing
582 * the IPI and the END ESBs in the VC region.
584 if (tsel
== CQ_TAR_TSEL_EDT
&& tsel_index
== ARRAY_SIZE(xive
->edt
)) {
585 pnv_xive_edt_resize(xive
);
592 * Virtual Structure Tables (VST) configuration
594 static void pnv_xive_vst_set_exclusive(PnvXive
*xive
, uint8_t type
,
595 uint8_t blk
, uint64_t vsd
)
597 XiveENDSource
*end_xsrc
= &xive
->end_source
;
598 XiveSource
*xsrc
= &xive
->ipi_source
;
599 const XiveVstInfo
*info
= &vst_infos
[type
];
600 uint32_t page_shift
= GETFIELD(VSD_TSIZE
, vsd
) + 12;
601 uint64_t vst_addr
= vsd
& VSD_ADDRESS_MASK
;
605 if (VSD_INDIRECT
& vsd
) {
606 if (!(xive
->regs
[VC_GLOBAL_CONFIG
>> 3] & VC_GCONF_INDIRECT
)) {
607 xive_error(xive
, "VST: %s indirect tables are not enabled",
612 if (!pnv_xive_vst_page_size_allowed(page_shift
)) {
613 xive_error(xive
, "VST: invalid %s page shift %d", info
->name
,
619 if (!QEMU_IS_ALIGNED(vst_addr
, 1ull << page_shift
)) {
620 xive_error(xive
, "VST: %s table address 0x%"PRIx64
" is not aligned with"
621 " page shift %d", info
->name
, vst_addr
, page_shift
);
625 /* Record the table configuration (in SRAM on HW) */
626 xive
->vsds
[type
][blk
] = vsd
;
628 /* Now tune the models with the configuration provided by the FW */
631 case VST_TSEL_IVT
: /* Nothing to be done */
636 * Backing store pages for the END. Compute the number of ENDs
637 * provisioned by FW and resize the END ESB window accordingly.
639 memory_region_set_size(&end_xsrc
->esb_mmio
, pnv_xive_nr_ends(xive
) *
640 (1ull << (end_xsrc
->esb_shift
+ 1)));
641 memory_region_add_subregion(&xive
->end_edt_mmio
, 0,
642 &end_xsrc
->esb_mmio
);
647 * Backing store pages for the source PQ bits. The model does
648 * not use these PQ bits backed in RAM because the XiveSource
649 * model has its own. Compute the number of IRQs provisioned
650 * by FW and resize the IPI ESB window accordingly.
652 memory_region_set_size(&xsrc
->esb_mmio
, pnv_xive_nr_ipis(xive
) *
653 (1ull << xsrc
->esb_shift
));
654 memory_region_add_subregion(&xive
->ipi_edt_mmio
, 0, &xsrc
->esb_mmio
);
657 case VST_TSEL_VPDT
: /* Not modeled */
658 case VST_TSEL_IRQ
: /* Not modeled */
660 * These tables contains the backing store pages for the
661 * interrupt fifos of the VC sub-engine in case of overflow.
666 g_assert_not_reached();
671 * Both PC and VC sub-engines are configured as each use the Virtual
672 * Structure Tables : SBE, EAS, END and NVT.
674 static void pnv_xive_vst_set_data(PnvXive
*xive
, uint64_t vsd
, bool pc_engine
)
676 uint8_t mode
= GETFIELD(VSD_MODE
, vsd
);
677 uint8_t type
= GETFIELD(VST_TABLE_SELECT
,
678 xive
->regs
[VC_VSD_TABLE_ADDR
>> 3]);
679 uint8_t blk
= GETFIELD(VST_TABLE_BLOCK
,
680 xive
->regs
[VC_VSD_TABLE_ADDR
>> 3]);
681 uint64_t vst_addr
= vsd
& VSD_ADDRESS_MASK
;
683 if (type
> VST_TSEL_IRQ
) {
684 xive_error(xive
, "VST: invalid table type %d", type
);
688 if (blk
>= vst_infos
[type
].max_blocks
) {
689 xive_error(xive
, "VST: invalid block id %d for"
690 " %s table", blk
, vst_infos
[type
].name
);
695 * Only take the VC sub-engine configuration into account because
696 * the XiveRouter model combines both VC and PC sub-engines
703 xive_error(xive
, "VST: invalid %s table address", vst_infos
[type
].name
);
708 case VSD_MODE_FORWARD
:
709 xive
->vsds
[type
][blk
] = vsd
;
712 case VSD_MODE_EXCLUSIVE
:
713 pnv_xive_vst_set_exclusive(xive
, type
, blk
, vsd
);
717 xive_error(xive
, "VST: unsupported table mode %d", mode
);
723 * Interrupt controller MMIO region. The layout is compatible between
726 * Page 0 sub-engine BARs
727 * 0x000 - 0x3FF IC registers
728 * 0x400 - 0x7FF PC registers
729 * 0x800 - 0xFFF VC registers
731 * Page 1 Notify page (writes only)
732 * 0x000 - 0x7FF HW interrupt triggers (PSI, PHB)
733 * 0x800 - 0xFFF forwards and syncs
735 * Page 2 LSI Trigger page (writes only) (not modeled)
736 * Page 3 LSI SB EOI page (reads only) (not modeled)
738 * Page 4-7 indirect TIMA
742 * IC - registers MMIO
744 static void pnv_xive_ic_reg_write(void *opaque
, hwaddr offset
,
745 uint64_t val
, unsigned size
)
747 PnvXive
*xive
= PNV_XIVE(opaque
);
748 MemoryRegion
*sysmem
= get_system_memory();
749 uint32_t reg
= offset
>> 3;
750 bool is_chip0
= xive
->chip
->chip_id
== 0;
755 * XIVE CQ (PowerBus bridge) settings
757 case CQ_MSGSND
: /* msgsnd for doorbells */
758 case CQ_FIRMASK_OR
: /* FIR error reporting */
761 if (val
& CQ_PBI_PC_64K
) {
764 if (val
& CQ_PBI_VC_64K
) {
768 case CQ_CFG_PB_GEN
: /* PowerBus General Configuration */
770 * TODO: CQ_INT_ADDR_OPT for 1-block-per-chip mode
775 * XIVE Virtualization Controller settings
777 case VC_GLOBAL_CONFIG
:
781 * XIVE Presenter Controller settings
783 case PC_GLOBAL_CONFIG
:
785 * PC_GCONF_CHIPID_OVR
786 * Overrides Int command Chip ID with the Chip ID field (DEBUG)
791 * TODO: block group support
793 * PC_TCTXT_CFG_BLKGRP_EN
794 * PC_TCTXT_CFG_HARD_CHIPID_BLK :
795 * Moves the chipid into block field for hardwired CAM compares.
796 * Block offset value is adjusted to 0b0..01 & ThrdId
798 * Will require changes in xive_presenter_tctx_match(). I am
799 * not sure how to handle that yet.
802 /* Overrides hardwired chip ID with the chip ID field */
803 if (val
& PC_TCTXT_CHIPID_OVERRIDE
) {
804 xive
->tctx_chipid
= GETFIELD(PC_TCTXT_CHIPID
, val
);
810 * enable block tracking and exchange of block ownership
811 * information between Interrupt controllers
818 case VC_SBC_CONFIG
: /* Store EOI configuration */
820 * Configure store EOI if required by firwmare (skiboot has removed
821 * support recently though)
823 if (val
& (VC_SBC_CONF_CPLX_CIST
| VC_SBC_CONF_CIST_BOTH
)) {
824 xive
->ipi_source
.esb_flags
|= XIVE_SRC_STORE_EOI
;
828 case VC_EQC_CONFIG
: /* TODO: silent escalation */
829 case VC_AIB_TX_ORDER_TAG2
: /* relax ordering */
833 * XIVE BAR settings (XSCOM only)
836 /* bit4: resets all BAR registers */
839 case CQ_IC_BAR
: /* IC BAR. 8 pages */
840 xive
->ic_shift
= val
& CQ_IC_BAR_64K
? 16 : 12;
841 if (!(val
& CQ_IC_BAR_VALID
)) {
843 if (xive
->regs
[reg
] & CQ_IC_BAR_VALID
) {
844 memory_region_del_subregion(&xive
->ic_mmio
,
846 memory_region_del_subregion(&xive
->ic_mmio
,
847 &xive
->ic_notify_mmio
);
848 memory_region_del_subregion(&xive
->ic_mmio
,
850 memory_region_del_subregion(&xive
->ic_mmio
,
851 &xive
->tm_indirect_mmio
);
853 memory_region_del_subregion(sysmem
, &xive
->ic_mmio
);
856 xive
->ic_base
= val
& ~(CQ_IC_BAR_VALID
| CQ_IC_BAR_64K
);
857 if (!(xive
->regs
[reg
] & CQ_IC_BAR_VALID
)) {
858 memory_region_add_subregion(sysmem
, xive
->ic_base
,
861 memory_region_add_subregion(&xive
->ic_mmio
, 0,
863 memory_region_add_subregion(&xive
->ic_mmio
,
864 1ul << xive
->ic_shift
,
865 &xive
->ic_notify_mmio
);
866 memory_region_add_subregion(&xive
->ic_mmio
,
867 2ul << xive
->ic_shift
,
869 memory_region_add_subregion(&xive
->ic_mmio
,
870 4ull << xive
->ic_shift
,
871 &xive
->tm_indirect_mmio
);
876 case CQ_TM1_BAR
: /* TM BAR. 4 pages. Map only once */
877 case CQ_TM2_BAR
: /* second TM BAR. for hotplug. Not modeled */
878 xive
->tm_shift
= val
& CQ_TM_BAR_64K
? 16 : 12;
879 if (!(val
& CQ_TM_BAR_VALID
)) {
881 if (xive
->regs
[reg
] & CQ_TM_BAR_VALID
&& is_chip0
) {
882 memory_region_del_subregion(sysmem
, &xive
->tm_mmio
);
885 xive
->tm_base
= val
& ~(CQ_TM_BAR_VALID
| CQ_TM_BAR_64K
);
886 if (!(xive
->regs
[reg
] & CQ_TM_BAR_VALID
) && is_chip0
) {
887 memory_region_add_subregion(sysmem
, xive
->tm_base
,
894 xive
->regs
[reg
] = val
;
895 memory_region_set_size(&xive
->pc_mmio
, pnv_xive_pc_size(xive
));
897 case CQ_PC_BAR
: /* From 32M to 512G */
898 if (!(val
& CQ_PC_BAR_VALID
)) {
900 if (xive
->regs
[reg
] & CQ_PC_BAR_VALID
) {
901 memory_region_del_subregion(sysmem
, &xive
->pc_mmio
);
904 xive
->pc_base
= val
& ~(CQ_PC_BAR_VALID
);
905 if (!(xive
->regs
[reg
] & CQ_PC_BAR_VALID
)) {
906 memory_region_add_subregion(sysmem
, xive
->pc_base
,
913 xive
->regs
[reg
] = val
;
914 memory_region_set_size(&xive
->vc_mmio
, pnv_xive_vc_size(xive
));
916 case CQ_VC_BAR
: /* From 64M to 4TB */
917 if (!(val
& CQ_VC_BAR_VALID
)) {
919 if (xive
->regs
[reg
] & CQ_VC_BAR_VALID
) {
920 memory_region_del_subregion(sysmem
, &xive
->vc_mmio
);
923 xive
->vc_base
= val
& ~(CQ_VC_BAR_VALID
);
924 if (!(xive
->regs
[reg
] & CQ_VC_BAR_VALID
)) {
925 memory_region_add_subregion(sysmem
, xive
->vc_base
,
932 * XIVE Table settings.
934 case CQ_TAR
: /* Table Address */
936 case CQ_TDR
: /* Table Data */
937 pnv_xive_table_set_data(xive
, val
);
941 * XIVE VC & PC Virtual Structure Table settings
943 case VC_VSD_TABLE_ADDR
:
944 case PC_VSD_TABLE_ADDR
: /* Virtual table selector */
946 case VC_VSD_TABLE_DATA
: /* Virtual table setting */
947 case PC_VSD_TABLE_DATA
:
948 pnv_xive_vst_set_data(xive
, val
, offset
== PC_VSD_TABLE_DATA
);
952 * Interrupt fifo overflow in memory backing store (Not modeled)
954 case VC_IRQ_CONFIG_IPI
:
955 case VC_IRQ_CONFIG_HW
:
956 case VC_IRQ_CONFIG_CASCADE1
:
957 case VC_IRQ_CONFIG_CASCADE2
:
958 case VC_IRQ_CONFIG_REDIST
:
959 case VC_IRQ_CONFIG_IPI_CASC
:
963 * XIVE hardware thread enablement
965 case PC_THREAD_EN_REG0
: /* Physical Thread Enable */
966 case PC_THREAD_EN_REG1
: /* Physical Thread Enable (fused core) */
969 case PC_THREAD_EN_REG0_SET
:
970 xive
->regs
[PC_THREAD_EN_REG0
>> 3] |= val
;
972 case PC_THREAD_EN_REG1_SET
:
973 xive
->regs
[PC_THREAD_EN_REG1
>> 3] |= val
;
975 case PC_THREAD_EN_REG0_CLR
:
976 xive
->regs
[PC_THREAD_EN_REG0
>> 3] &= ~val
;
978 case PC_THREAD_EN_REG1_CLR
:
979 xive
->regs
[PC_THREAD_EN_REG1
>> 3] &= ~val
;
983 * Indirect TIMA access set up. Defines the PIR of the HW thread
986 case PC_TCTXT_INDIR0
... PC_TCTXT_INDIR3
:
990 * XIVE PC & VC cache updates for EAS, NVT and END
992 case VC_IVC_SCRUB_MASK
:
993 case VC_IVC_SCRUB_TRIG
:
996 case VC_EQC_CWATCH_SPEC
:
997 val
&= ~VC_EQC_CWATCH_CONFLICT
; /* HW resets this bit */
999 case VC_EQC_CWATCH_DAT1
... VC_EQC_CWATCH_DAT3
:
1001 case VC_EQC_CWATCH_DAT0
:
1002 /* writing to DATA0 triggers the cache write */
1003 xive
->regs
[reg
] = val
;
1004 pnv_xive_end_update(xive
);
1006 case VC_EQC_SCRUB_MASK
:
1007 case VC_EQC_SCRUB_TRIG
:
1009 * The scrubbing registers flush the cache in RAM and can also
1014 case PC_VPC_CWATCH_SPEC
:
1015 val
&= ~PC_VPC_CWATCH_CONFLICT
; /* HW resets this bit */
1017 case PC_VPC_CWATCH_DAT1
... PC_VPC_CWATCH_DAT7
:
1019 case PC_VPC_CWATCH_DAT0
:
1020 /* writing to DATA0 triggers the cache write */
1021 xive
->regs
[reg
] = val
;
1022 pnv_xive_nvt_update(xive
);
1024 case PC_VPC_SCRUB_MASK
:
1025 case PC_VPC_SCRUB_TRIG
:
1027 * The scrubbing registers flush the cache in RAM and can also
1034 * XIVE PC & VC cache invalidation
1038 case VC_AT_MACRO_KILL
:
1040 case PC_AT_KILL_MASK
:
1041 case VC_AT_MACRO_KILL_MASK
:
1045 xive_error(xive
, "IC: invalid write to reg=0x%"HWADDR_PRIx
, offset
);
1049 xive
->regs
[reg
] = val
;
1052 static uint64_t pnv_xive_ic_reg_read(void *opaque
, hwaddr offset
, unsigned size
)
1054 PnvXive
*xive
= PNV_XIVE(opaque
);
1056 uint32_t reg
= offset
>> 3;
1072 case PC_TCTXT_TRACK
:
1073 case PC_TCTXT_INDIR0
:
1074 case PC_TCTXT_INDIR1
:
1075 case PC_TCTXT_INDIR2
:
1076 case PC_TCTXT_INDIR3
:
1077 case PC_GLOBAL_CONFIG
:
1079 case PC_VPC_SCRUB_MASK
:
1081 case VC_GLOBAL_CONFIG
:
1082 case VC_AIB_TX_ORDER_TAG2
:
1084 case VC_IRQ_CONFIG_IPI
:
1085 case VC_IRQ_CONFIG_HW
:
1086 case VC_IRQ_CONFIG_CASCADE1
:
1087 case VC_IRQ_CONFIG_CASCADE2
:
1088 case VC_IRQ_CONFIG_REDIST
:
1089 case VC_IRQ_CONFIG_IPI_CASC
:
1091 case VC_EQC_SCRUB_MASK
:
1092 case VC_IVC_SCRUB_MASK
:
1094 case VC_AT_MACRO_KILL_MASK
:
1095 case VC_VSD_TABLE_ADDR
:
1096 case PC_VSD_TABLE_ADDR
:
1097 case VC_VSD_TABLE_DATA
:
1098 case PC_VSD_TABLE_DATA
:
1099 case PC_THREAD_EN_REG0
:
1100 case PC_THREAD_EN_REG1
:
1101 val
= xive
->regs
[reg
];
1105 * XIVE hardware thread enablement
1107 case PC_THREAD_EN_REG0_SET
:
1108 case PC_THREAD_EN_REG0_CLR
:
1109 val
= xive
->regs
[PC_THREAD_EN_REG0
>> 3];
1111 case PC_THREAD_EN_REG1_SET
:
1112 case PC_THREAD_EN_REG1_CLR
:
1113 val
= xive
->regs
[PC_THREAD_EN_REG1
>> 3];
1116 case CQ_MSGSND
: /* Identifies which cores have msgsnd enabled. */
1117 val
= 0xffffff0000000000;
1121 * XIVE PC & VC cache updates for EAS, NVT and END
1123 case VC_EQC_CWATCH_SPEC
:
1124 xive
->regs
[reg
] = ~(VC_EQC_CWATCH_FULL
| VC_EQC_CWATCH_CONFLICT
);
1125 val
= xive
->regs
[reg
];
1127 case VC_EQC_CWATCH_DAT0
:
1129 * Load DATA registers from cache with data requested by the
1132 pnv_xive_end_cache_load(xive
);
1133 val
= xive
->regs
[reg
];
1135 case VC_EQC_CWATCH_DAT1
... VC_EQC_CWATCH_DAT3
:
1136 val
= xive
->regs
[reg
];
1139 case PC_VPC_CWATCH_SPEC
:
1140 xive
->regs
[reg
] = ~(PC_VPC_CWATCH_FULL
| PC_VPC_CWATCH_CONFLICT
);
1141 val
= xive
->regs
[reg
];
1143 case PC_VPC_CWATCH_DAT0
:
1145 * Load DATA registers from cache with data requested by the
1148 pnv_xive_nvt_cache_load(xive
);
1149 val
= xive
->regs
[reg
];
1151 case PC_VPC_CWATCH_DAT1
... PC_VPC_CWATCH_DAT7
:
1152 val
= xive
->regs
[reg
];
1155 case PC_VPC_SCRUB_TRIG
:
1156 case VC_IVC_SCRUB_TRIG
:
1157 case VC_EQC_SCRUB_TRIG
:
1158 xive
->regs
[reg
] &= ~VC_SCRUB_VALID
;
1159 val
= xive
->regs
[reg
];
1163 * XIVE PC & VC cache invalidation
1166 xive
->regs
[reg
] &= ~PC_AT_KILL_VALID
;
1167 val
= xive
->regs
[reg
];
1169 case VC_AT_MACRO_KILL
:
1170 xive
->regs
[reg
] &= ~VC_KILL_VALID
;
1171 val
= xive
->regs
[reg
];
1175 * XIVE synchronisation
1178 val
= VC_EQC_SYNC_MASK
;
1182 xive_error(xive
, "IC: invalid read reg=0x%"HWADDR_PRIx
, offset
);
1188 static const MemoryRegionOps pnv_xive_ic_reg_ops
= {
1189 .read
= pnv_xive_ic_reg_read
,
1190 .write
= pnv_xive_ic_reg_write
,
1191 .endianness
= DEVICE_BIG_ENDIAN
,
1193 .min_access_size
= 8,
1194 .max_access_size
= 8,
1197 .min_access_size
= 8,
1198 .max_access_size
= 8,
1203 * IC - Notify MMIO port page (write only)
1205 #define PNV_XIVE_FORWARD_IPI 0x800 /* Forward IPI */
1206 #define PNV_XIVE_FORWARD_HW 0x880 /* Forward HW */
1207 #define PNV_XIVE_FORWARD_OS_ESC 0x900 /* Forward OS escalation */
1208 #define PNV_XIVE_FORWARD_HW_ESC 0x980 /* Forward Hyp escalation */
1209 #define PNV_XIVE_FORWARD_REDIS 0xa00 /* Forward Redistribution */
1210 #define PNV_XIVE_RESERVED5 0xa80 /* Cache line 5 PowerBUS operation */
1211 #define PNV_XIVE_RESERVED6 0xb00 /* Cache line 6 PowerBUS operation */
1212 #define PNV_XIVE_RESERVED7 0xb80 /* Cache line 7 PowerBUS operation */
1214 /* VC synchronisation */
1215 #define PNV_XIVE_SYNC_IPI 0xc00 /* Sync IPI */
1216 #define PNV_XIVE_SYNC_HW 0xc80 /* Sync HW */
1217 #define PNV_XIVE_SYNC_OS_ESC 0xd00 /* Sync OS escalation */
1218 #define PNV_XIVE_SYNC_HW_ESC 0xd80 /* Sync Hyp escalation */
1219 #define PNV_XIVE_SYNC_REDIS 0xe00 /* Sync Redistribution */
1221 /* PC synchronisation */
1222 #define PNV_XIVE_SYNC_PULL 0xe80 /* Sync pull context */
1223 #define PNV_XIVE_SYNC_PUSH 0xf00 /* Sync push context */
1224 #define PNV_XIVE_SYNC_VPC 0xf80 /* Sync remove VPC store */
1226 static void pnv_xive_ic_hw_trigger(PnvXive
*xive
, hwaddr addr
, uint64_t val
)
1231 if (val
& XIVE_TRIGGER_END
) {
1232 xive_error(xive
, "IC: END trigger at @0x%"HWADDR_PRIx
" data 0x%"PRIx64
,
1238 * Forward the source event notification directly to the Router.
1239 * The source interrupt number should already be correctly encoded
1240 * with the chip block id by the sending device (PHB, PSI).
1242 blk
= XIVE_EAS_BLOCK(val
);
1243 idx
= XIVE_EAS_INDEX(val
);
1245 xive_router_notify(XIVE_NOTIFIER(xive
), XIVE_EAS(blk
, idx
));
1248 static void pnv_xive_ic_notify_write(void *opaque
, hwaddr addr
, uint64_t val
,
1251 PnvXive
*xive
= PNV_XIVE(opaque
);
1253 /* VC: HW triggers */
1255 case 0x000 ... 0x7FF:
1256 pnv_xive_ic_hw_trigger(opaque
, addr
, val
);
1259 /* VC: Forwarded IRQs */
1260 case PNV_XIVE_FORWARD_IPI
:
1261 case PNV_XIVE_FORWARD_HW
:
1262 case PNV_XIVE_FORWARD_OS_ESC
:
1263 case PNV_XIVE_FORWARD_HW_ESC
:
1264 case PNV_XIVE_FORWARD_REDIS
:
1265 /* TODO: forwarded IRQs. Should be like HW triggers */
1266 xive_error(xive
, "IC: forwarded at @0x%"HWADDR_PRIx
" IRQ 0x%"PRIx64
,
1271 case PNV_XIVE_SYNC_IPI
:
1272 case PNV_XIVE_SYNC_HW
:
1273 case PNV_XIVE_SYNC_OS_ESC
:
1274 case PNV_XIVE_SYNC_HW_ESC
:
1275 case PNV_XIVE_SYNC_REDIS
:
1279 case PNV_XIVE_SYNC_PULL
:
1280 case PNV_XIVE_SYNC_PUSH
:
1281 case PNV_XIVE_SYNC_VPC
:
1285 xive_error(xive
, "IC: invalid notify write @%"HWADDR_PRIx
, addr
);
1289 static uint64_t pnv_xive_ic_notify_read(void *opaque
, hwaddr addr
,
1292 PnvXive
*xive
= PNV_XIVE(opaque
);
1294 /* loads are invalid */
1295 xive_error(xive
, "IC: invalid notify read @%"HWADDR_PRIx
, addr
);
1299 static const MemoryRegionOps pnv_xive_ic_notify_ops
= {
1300 .read
= pnv_xive_ic_notify_read
,
1301 .write
= pnv_xive_ic_notify_write
,
1302 .endianness
= DEVICE_BIG_ENDIAN
,
1304 .min_access_size
= 8,
1305 .max_access_size
= 8,
1308 .min_access_size
= 8,
1309 .max_access_size
= 8,
1314 * IC - LSI MMIO handlers (not modeled)
1317 static void pnv_xive_ic_lsi_write(void *opaque
, hwaddr addr
,
1318 uint64_t val
, unsigned size
)
1320 PnvXive
*xive
= PNV_XIVE(opaque
);
1322 xive_error(xive
, "IC: LSI invalid write @%"HWADDR_PRIx
, addr
);
1325 static uint64_t pnv_xive_ic_lsi_read(void *opaque
, hwaddr addr
, unsigned size
)
1327 PnvXive
*xive
= PNV_XIVE(opaque
);
1329 xive_error(xive
, "IC: LSI invalid read @%"HWADDR_PRIx
, addr
);
1333 static const MemoryRegionOps pnv_xive_ic_lsi_ops
= {
1334 .read
= pnv_xive_ic_lsi_read
,
1335 .write
= pnv_xive_ic_lsi_write
,
1336 .endianness
= DEVICE_BIG_ENDIAN
,
1338 .min_access_size
= 8,
1339 .max_access_size
= 8,
1342 .min_access_size
= 8,
1343 .max_access_size
= 8,
1348 * IC - Indirect TIMA MMIO handlers
1352 * When the TIMA is accessed from the indirect page, the thread id
1353 * (PIR) has to be configured in the IC registers before. This is used
1354 * for resets and for debug purpose also.
1356 static XiveTCTX
*pnv_xive_get_indirect_tctx(PnvXive
*xive
)
1358 uint64_t tctxt_indir
= xive
->regs
[PC_TCTXT_INDIR0
>> 3];
1359 PowerPCCPU
*cpu
= NULL
;
1362 if (!(tctxt_indir
& PC_TCTXT_INDIR_VALID
)) {
1363 xive_error(xive
, "IC: no indirect TIMA access in progress");
1367 pir
= GETFIELD(PC_TCTXT_INDIR_THRDID
, tctxt_indir
) & 0xff;
1368 cpu
= ppc_get_vcpu_by_pir(pir
);
1370 xive_error(xive
, "IC: invalid PIR %x for indirect access", pir
);
1374 /* Check that HW thread is XIVE enabled */
1375 if (!(xive
->regs
[PC_THREAD_EN_REG0
>> 3] & PPC_BIT(pir
& 0x3f))) {
1376 xive_error(xive
, "IC: CPU %x is not enabled", pir
);
1379 return XIVE_TCTX(pnv_cpu_state(cpu
)->intc
);
1382 static void xive_tm_indirect_write(void *opaque
, hwaddr offset
,
1383 uint64_t value
, unsigned size
)
1385 XiveTCTX
*tctx
= pnv_xive_get_indirect_tctx(PNV_XIVE(opaque
));
1387 xive_tctx_tm_write(tctx
, offset
, value
, size
);
1390 static uint64_t xive_tm_indirect_read(void *opaque
, hwaddr offset
,
1393 XiveTCTX
*tctx
= pnv_xive_get_indirect_tctx(PNV_XIVE(opaque
));
1395 return xive_tctx_tm_read(tctx
, offset
, size
);
1398 static const MemoryRegionOps xive_tm_indirect_ops
= {
1399 .read
= xive_tm_indirect_read
,
1400 .write
= xive_tm_indirect_write
,
1401 .endianness
= DEVICE_BIG_ENDIAN
,
1403 .min_access_size
= 1,
1404 .max_access_size
= 8,
1407 .min_access_size
= 1,
1408 .max_access_size
= 8,
1413 * Interrupt controller XSCOM region.
1415 static uint64_t pnv_xive_xscom_read(void *opaque
, hwaddr addr
, unsigned size
)
1417 switch (addr
>> 3) {
1418 case X_VC_EQC_CONFIG
:
1419 /* FIXME (skiboot): This is the only XSCOM load. Bizarre. */
1420 return VC_EQC_SYNC_MASK
;
1422 return pnv_xive_ic_reg_read(opaque
, addr
, size
);
1426 static void pnv_xive_xscom_write(void *opaque
, hwaddr addr
,
1427 uint64_t val
, unsigned size
)
1429 pnv_xive_ic_reg_write(opaque
, addr
, val
, size
);
1432 static const MemoryRegionOps pnv_xive_xscom_ops
= {
1433 .read
= pnv_xive_xscom_read
,
1434 .write
= pnv_xive_xscom_write
,
1435 .endianness
= DEVICE_BIG_ENDIAN
,
1437 .min_access_size
= 8,
1438 .max_access_size
= 8,
1441 .min_access_size
= 8,
1442 .max_access_size
= 8,
1447 * Virtualization Controller MMIO region containing the IPI and END ESB pages
1449 static uint64_t pnv_xive_vc_read(void *opaque
, hwaddr offset
,
1452 PnvXive
*xive
= PNV_XIVE(opaque
);
1453 uint64_t edt_index
= offset
>> pnv_xive_edt_shift(xive
);
1454 uint64_t edt_type
= 0;
1455 uint64_t edt_offset
;
1457 AddressSpace
*edt_as
= NULL
;
1460 if (edt_index
< XIVE_TABLE_EDT_MAX
) {
1461 edt_type
= GETFIELD(CQ_TDR_EDT_TYPE
, xive
->edt
[edt_index
]);
1465 case CQ_TDR_EDT_IPI
:
1466 edt_as
= &xive
->ipi_as
;
1469 edt_as
= &xive
->end_as
;
1472 xive_error(xive
, "VC: invalid EDT type for read @%"HWADDR_PRIx
, offset
);
1476 /* Remap the offset for the targeted address space */
1477 edt_offset
= pnv_xive_edt_offset(xive
, offset
, edt_type
);
1479 ret
= address_space_ldq(edt_as
, edt_offset
, MEMTXATTRS_UNSPECIFIED
,
1482 if (result
!= MEMTX_OK
) {
1483 xive_error(xive
, "VC: %s read failed at @0x%"HWADDR_PRIx
" -> @0x%"
1484 HWADDR_PRIx
, edt_type
== CQ_TDR_EDT_IPI
? "IPI" : "END",
1485 offset
, edt_offset
);
1492 static void pnv_xive_vc_write(void *opaque
, hwaddr offset
,
1493 uint64_t val
, unsigned size
)
1495 PnvXive
*xive
= PNV_XIVE(opaque
);
1496 uint64_t edt_index
= offset
>> pnv_xive_edt_shift(xive
);
1497 uint64_t edt_type
= 0;
1498 uint64_t edt_offset
;
1500 AddressSpace
*edt_as
= NULL
;
1502 if (edt_index
< XIVE_TABLE_EDT_MAX
) {
1503 edt_type
= GETFIELD(CQ_TDR_EDT_TYPE
, xive
->edt
[edt_index
]);
1507 case CQ_TDR_EDT_IPI
:
1508 edt_as
= &xive
->ipi_as
;
1511 edt_as
= &xive
->end_as
;
1514 xive_error(xive
, "VC: invalid EDT type for write @%"HWADDR_PRIx
,
1519 /* Remap the offset for the targeted address space */
1520 edt_offset
= pnv_xive_edt_offset(xive
, offset
, edt_type
);
1522 address_space_stq(edt_as
, edt_offset
, val
, MEMTXATTRS_UNSPECIFIED
, &result
);
1523 if (result
!= MEMTX_OK
) {
1524 xive_error(xive
, "VC: write failed at @0x%"HWADDR_PRIx
, edt_offset
);
1528 static const MemoryRegionOps pnv_xive_vc_ops
= {
1529 .read
= pnv_xive_vc_read
,
1530 .write
= pnv_xive_vc_write
,
1531 .endianness
= DEVICE_BIG_ENDIAN
,
1533 .min_access_size
= 8,
1534 .max_access_size
= 8,
1537 .min_access_size
= 8,
1538 .max_access_size
= 8,
1543 * Presenter Controller MMIO region. The Virtualization Controller
1544 * updates the IPB in the NVT table when required. Not modeled.
1546 static uint64_t pnv_xive_pc_read(void *opaque
, hwaddr addr
,
1549 PnvXive
*xive
= PNV_XIVE(opaque
);
1551 xive_error(xive
, "PC: invalid read @%"HWADDR_PRIx
, addr
);
1555 static void pnv_xive_pc_write(void *opaque
, hwaddr addr
,
1556 uint64_t value
, unsigned size
)
1558 PnvXive
*xive
= PNV_XIVE(opaque
);
1560 xive_error(xive
, "PC: invalid write to VC @%"HWADDR_PRIx
, addr
);
1563 static const MemoryRegionOps pnv_xive_pc_ops
= {
1564 .read
= pnv_xive_pc_read
,
1565 .write
= pnv_xive_pc_write
,
1566 .endianness
= DEVICE_BIG_ENDIAN
,
1568 .min_access_size
= 8,
1569 .max_access_size
= 8,
1572 .min_access_size
= 8,
1573 .max_access_size
= 8,
1577 void pnv_xive_pic_print_info(PnvXive
*xive
, Monitor
*mon
)
1579 XiveRouter
*xrtr
= XIVE_ROUTER(xive
);
1580 uint8_t blk
= xive
->chip
->chip_id
;
1581 uint32_t srcno0
= XIVE_EAS(blk
, 0);
1582 uint32_t nr_ipis
= pnv_xive_nr_ipis(xive
);
1583 uint32_t nr_ends
= pnv_xive_nr_ends(xive
);
1588 monitor_printf(mon
, "XIVE[%x] Source %08x .. %08x\n", blk
, srcno0
,
1589 srcno0
+ nr_ipis
- 1);
1590 xive_source_pic_print_info(&xive
->ipi_source
, srcno0
, mon
);
1592 monitor_printf(mon
, "XIVE[%x] EAT %08x .. %08x\n", blk
, srcno0
,
1593 srcno0
+ nr_ipis
- 1);
1594 for (i
= 0; i
< nr_ipis
; i
++) {
1595 if (xive_router_get_eas(xrtr
, blk
, i
, &eas
)) {
1598 if (!xive_eas_is_masked(&eas
)) {
1599 xive_eas_pic_print_info(&eas
, i
, mon
);
1603 monitor_printf(mon
, "XIVE[%x] ENDT %08x .. %08x\n", blk
, 0, nr_ends
- 1);
1604 for (i
= 0; i
< nr_ends
; i
++) {
1605 if (xive_router_get_end(xrtr
, blk
, i
, &end
)) {
1608 xive_end_pic_print_info(&end
, i
, mon
);
1611 monitor_printf(mon
, "XIVE[%x] END Escalation %08x .. %08x\n", blk
, 0,
1613 for (i
= 0; i
< nr_ends
; i
++) {
1614 if (xive_router_get_end(xrtr
, blk
, i
, &end
)) {
1617 xive_end_eas_pic_print_info(&end
, i
, mon
);
1621 static void pnv_xive_reset(void *dev
)
1623 PnvXive
*xive
= PNV_XIVE(dev
);
1624 XiveSource
*xsrc
= &xive
->ipi_source
;
1625 XiveENDSource
*end_xsrc
= &xive
->end_source
;
1628 * Use the PnvChip id to identify the XIVE interrupt controller.
1629 * It can be overriden by configuration at runtime.
1631 xive
->tctx_chipid
= xive
->chip
->chip_id
;
1633 /* Default page size (Should be changed at runtime to 64k) */
1634 xive
->ic_shift
= xive
->vc_shift
= xive
->pc_shift
= 12;
1636 /* Clear subregions */
1637 if (memory_region_is_mapped(&xsrc
->esb_mmio
)) {
1638 memory_region_del_subregion(&xive
->ipi_edt_mmio
, &xsrc
->esb_mmio
);
1641 if (memory_region_is_mapped(&xive
->ipi_edt_mmio
)) {
1642 memory_region_del_subregion(&xive
->ipi_mmio
, &xive
->ipi_edt_mmio
);
1645 if (memory_region_is_mapped(&end_xsrc
->esb_mmio
)) {
1646 memory_region_del_subregion(&xive
->end_edt_mmio
, &end_xsrc
->esb_mmio
);
1649 if (memory_region_is_mapped(&xive
->end_edt_mmio
)) {
1650 memory_region_del_subregion(&xive
->end_mmio
, &xive
->end_edt_mmio
);
1654 static void pnv_xive_init(Object
*obj
)
1656 PnvXive
*xive
= PNV_XIVE(obj
);
1658 object_initialize_child(obj
, "ipi_source", &xive
->ipi_source
,
1659 sizeof(xive
->ipi_source
), TYPE_XIVE_SOURCE
,
1660 &error_abort
, NULL
);
1661 object_initialize_child(obj
, "end_source", &xive
->end_source
,
1662 sizeof(xive
->end_source
), TYPE_XIVE_END_SOURCE
,
1663 &error_abort
, NULL
);
1667 * Maximum number of IRQs and ENDs supported by HW
1669 #define PNV_XIVE_NR_IRQS (PNV9_XIVE_VC_SIZE / (1ull << XIVE_ESB_64K_2PAGE))
1670 #define PNV_XIVE_NR_ENDS (PNV9_XIVE_VC_SIZE / (1ull << XIVE_ESB_64K_2PAGE))
1672 static void pnv_xive_realize(DeviceState
*dev
, Error
**errp
)
1674 PnvXive
*xive
= PNV_XIVE(dev
);
1675 XiveSource
*xsrc
= &xive
->ipi_source
;
1676 XiveENDSource
*end_xsrc
= &xive
->end_source
;
1677 Error
*local_err
= NULL
;
1680 obj
= object_property_get_link(OBJECT(dev
), "chip", &local_err
);
1682 error_propagate(errp
, local_err
);
1683 error_prepend(errp
, "required link 'chip' not found: ");
1687 /* The PnvChip id identifies the XIVE interrupt controller. */
1688 xive
->chip
= PNV_CHIP(obj
);
1691 * The XiveSource and XiveENDSource objects are realized with the
1692 * maximum allowed HW configuration. The ESB MMIO regions will be
1693 * resized dynamically when the controller is configured by the FW
1694 * to limit accesses to resources not provisioned.
1696 object_property_set_int(OBJECT(xsrc
), PNV_XIVE_NR_IRQS
, "nr-irqs",
1698 object_property_set_link(OBJECT(xsrc
), OBJECT(xive
), "xive",
1700 object_property_set_bool(OBJECT(xsrc
), true, "realized", &local_err
);
1702 error_propagate(errp
, local_err
);
1706 object_property_set_int(OBJECT(end_xsrc
), PNV_XIVE_NR_ENDS
, "nr-ends",
1708 object_property_add_const_link(OBJECT(end_xsrc
), "xive", OBJECT(xive
),
1710 object_property_set_bool(OBJECT(end_xsrc
), true, "realized", &local_err
);
1712 error_propagate(errp
, local_err
);
1716 /* Default page size. Generally changed at runtime to 64k */
1717 xive
->ic_shift
= xive
->vc_shift
= xive
->pc_shift
= 12;
1719 /* XSCOM region, used for initial configuration of the BARs */
1720 memory_region_init_io(&xive
->xscom_regs
, OBJECT(dev
), &pnv_xive_xscom_ops
,
1721 xive
, "xscom-xive", PNV9_XSCOM_XIVE_SIZE
<< 3);
1723 /* Interrupt controller MMIO regions */
1724 memory_region_init(&xive
->ic_mmio
, OBJECT(dev
), "xive-ic",
1727 memory_region_init_io(&xive
->ic_reg_mmio
, OBJECT(dev
), &pnv_xive_ic_reg_ops
,
1728 xive
, "xive-ic-reg", 1 << xive
->ic_shift
);
1729 memory_region_init_io(&xive
->ic_notify_mmio
, OBJECT(dev
),
1730 &pnv_xive_ic_notify_ops
,
1731 xive
, "xive-ic-notify", 1 << xive
->ic_shift
);
1733 /* The Pervasive LSI trigger and EOI pages (not modeled) */
1734 memory_region_init_io(&xive
->ic_lsi_mmio
, OBJECT(dev
), &pnv_xive_ic_lsi_ops
,
1735 xive
, "xive-ic-lsi", 2 << xive
->ic_shift
);
1737 /* Thread Interrupt Management Area (Indirect) */
1738 memory_region_init_io(&xive
->tm_indirect_mmio
, OBJECT(dev
),
1739 &xive_tm_indirect_ops
,
1740 xive
, "xive-tima-indirect", PNV9_XIVE_TM_SIZE
);
1742 * Overall Virtualization Controller MMIO region containing the
1743 * IPI ESB pages and END ESB pages. The layout is defined by the
1744 * EDT "Domain table" and the accesses are dispatched using
1745 * address spaces for each.
1747 memory_region_init_io(&xive
->vc_mmio
, OBJECT(xive
), &pnv_xive_vc_ops
, xive
,
1748 "xive-vc", PNV9_XIVE_VC_SIZE
);
1750 memory_region_init(&xive
->ipi_mmio
, OBJECT(xive
), "xive-vc-ipi",
1752 address_space_init(&xive
->ipi_as
, &xive
->ipi_mmio
, "xive-vc-ipi");
1753 memory_region_init(&xive
->end_mmio
, OBJECT(xive
), "xive-vc-end",
1755 address_space_init(&xive
->end_as
, &xive
->end_mmio
, "xive-vc-end");
1758 * The MMIO windows exposing the IPI ESBs and the END ESBs in the
1759 * VC region. Their size is configured by the FW in the EDT table.
1761 memory_region_init(&xive
->ipi_edt_mmio
, OBJECT(xive
), "xive-vc-ipi-edt", 0);
1762 memory_region_init(&xive
->end_edt_mmio
, OBJECT(xive
), "xive-vc-end-edt", 0);
1764 /* Presenter Controller MMIO region (not modeled) */
1765 memory_region_init_io(&xive
->pc_mmio
, OBJECT(xive
), &pnv_xive_pc_ops
, xive
,
1766 "xive-pc", PNV9_XIVE_PC_SIZE
);
1768 /* Thread Interrupt Management Area (Direct) */
1769 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &xive_tm_ops
,
1770 xive
, "xive-tima", PNV9_XIVE_TM_SIZE
);
1772 qemu_register_reset(pnv_xive_reset
, dev
);
1775 static int pnv_xive_dt_xscom(PnvXScomInterface
*dev
, void *fdt
,
1778 const char compat
[] = "ibm,power9-xive-x";
1781 uint32_t lpc_pcba
= PNV9_XSCOM_XIVE_BASE
;
1783 cpu_to_be32(lpc_pcba
),
1784 cpu_to_be32(PNV9_XSCOM_XIVE_SIZE
)
1787 name
= g_strdup_printf("xive@%x", lpc_pcba
);
1788 offset
= fdt_add_subnode(fdt
, xscom_offset
, name
);
1792 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, sizeof(reg
))));
1793 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
,
1798 static Property pnv_xive_properties
[] = {
1799 DEFINE_PROP_UINT64("ic-bar", PnvXive
, ic_base
, 0),
1800 DEFINE_PROP_UINT64("vc-bar", PnvXive
, vc_base
, 0),
1801 DEFINE_PROP_UINT64("pc-bar", PnvXive
, pc_base
, 0),
1802 DEFINE_PROP_UINT64("tm-bar", PnvXive
, tm_base
, 0),
1803 DEFINE_PROP_END_OF_LIST(),
1806 static void pnv_xive_class_init(ObjectClass
*klass
, void *data
)
1808 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1809 PnvXScomInterfaceClass
*xdc
= PNV_XSCOM_INTERFACE_CLASS(klass
);
1810 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
1811 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_CLASS(klass
);
1813 xdc
->dt_xscom
= pnv_xive_dt_xscom
;
1815 dc
->desc
= "PowerNV XIVE Interrupt Controller";
1816 dc
->realize
= pnv_xive_realize
;
1817 dc
->props
= pnv_xive_properties
;
1819 xrc
->get_eas
= pnv_xive_get_eas
;
1820 xrc
->get_end
= pnv_xive_get_end
;
1821 xrc
->write_end
= pnv_xive_write_end
;
1822 xrc
->get_nvt
= pnv_xive_get_nvt
;
1823 xrc
->write_nvt
= pnv_xive_write_nvt
;
1824 xrc
->get_tctx
= pnv_xive_get_tctx
;
1826 xnc
->notify
= pnv_xive_notify
;
1829 static const TypeInfo pnv_xive_info
= {
1830 .name
= TYPE_PNV_XIVE
,
1831 .parent
= TYPE_XIVE_ROUTER
,
1832 .instance_init
= pnv_xive_init
,
1833 .instance_size
= sizeof(PnvXive
),
1834 .class_init
= pnv_xive_class_init
,
1835 .interfaces
= (InterfaceInfo
[]) {
1836 { TYPE_PNV_XSCOM_INTERFACE
},
1841 static void pnv_xive_register_types(void)
1843 type_register_static(&pnv_xive_info
);
1846 type_init(pnv_xive_register_types
)