2 * QEMU PowerPC sPAPR XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "qemu/error-report.h"
15 #include "target/ppc/cpu.h"
16 #include "sysemu/cpus.h"
17 #include "sysemu/reset.h"
18 #include "migration/vmstate.h"
19 #include "monitor/monitor.h"
20 #include "hw/ppc/fdt.h"
21 #include "hw/ppc/spapr.h"
22 #include "hw/ppc/spapr_cpu_core.h"
23 #include "hw/ppc/spapr_xive.h"
24 #include "hw/ppc/xive.h"
25 #include "hw/ppc/xive_regs.h"
26 #include "hw/qdev-properties.h"
29 * XIVE Virtualization Controller BAR and Thread Managment BAR that we
30 * use for the ESB pages and the TIMA pages
32 #define SPAPR_XIVE_VC_BASE 0x0006010000000000ull
33 #define SPAPR_XIVE_TM_BASE 0x0006030203180000ull
36 * The allocation of VP blocks is a complex operation in OPAL and the
37 * VP identifiers have a relation with the number of HW chips, the
38 * size of the VP blocks, VP grouping, etc. The QEMU sPAPR XIVE
39 * controller model does not have the same constraints and can use a
40 * simple mapping scheme of the CPU vcpu_id
42 * These identifiers are never returned to the OS.
45 #define SPAPR_XIVE_NVT_BASE 0x400
48 * sPAPR NVT and END indexing helpers
50 static uint32_t spapr_xive_nvt_to_target(uint8_t nvt_blk
, uint32_t nvt_idx
)
52 return nvt_idx
- SPAPR_XIVE_NVT_BASE
;
55 static void spapr_xive_cpu_to_nvt(PowerPCCPU
*cpu
,
56 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
61 *out_nvt_blk
= SPAPR_XIVE_BLOCK_ID
;
65 *out_nvt_idx
= SPAPR_XIVE_NVT_BASE
+ cpu
->vcpu_id
;
69 static int spapr_xive_target_to_nvt(uint32_t target
,
70 uint8_t *out_nvt_blk
, uint32_t *out_nvt_idx
)
72 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
78 spapr_xive_cpu_to_nvt(cpu
, out_nvt_blk
, out_nvt_idx
);
83 * sPAPR END indexing uses a simple mapping of the CPU vcpu_id, 8
86 int spapr_xive_end_to_target(uint8_t end_blk
, uint32_t end_idx
,
87 uint32_t *out_server
, uint8_t *out_prio
)
90 assert(end_blk
== SPAPR_XIVE_BLOCK_ID
);
93 *out_server
= end_idx
>> 3;
97 *out_prio
= end_idx
& 0x7;
102 static void spapr_xive_cpu_to_end(PowerPCCPU
*cpu
, uint8_t prio
,
103 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
108 *out_end_blk
= SPAPR_XIVE_BLOCK_ID
;
112 *out_end_idx
= (cpu
->vcpu_id
<< 3) + prio
;
116 static int spapr_xive_target_to_end(uint32_t target
, uint8_t prio
,
117 uint8_t *out_end_blk
, uint32_t *out_end_idx
)
119 PowerPCCPU
*cpu
= spapr_find_cpu(target
);
125 spapr_xive_cpu_to_end(cpu
, prio
, out_end_blk
, out_end_idx
);
130 * On sPAPR machines, use a simplified output for the XIVE END
131 * structure dumping only the information related to the OS EQ.
133 static void spapr_xive_end_pic_print_info(SpaprXive
*xive
, XiveEND
*end
,
136 uint64_t qaddr_base
= xive_end_qaddr(end
);
137 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
138 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
139 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
140 uint32_t qentries
= 1 << (qsize
+ 10);
141 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
142 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
144 monitor_printf(mon
, "%3d/%d % 6d/%5d @%"PRIx64
" ^%d",
145 spapr_xive_nvt_to_target(0, nvt
),
146 priority
, qindex
, qentries
, qaddr_base
, qgen
);
148 xive_end_queue_pic_print_info(end
, 6, mon
);
149 monitor_printf(mon
, "]");
152 void spapr_xive_pic_print_info(SpaprXive
*xive
, Monitor
*mon
)
154 XiveSource
*xsrc
= &xive
->source
;
157 if (kvm_irqchip_in_kernel()) {
158 Error
*local_err
= NULL
;
160 kvmppc_xive_synchronize_state(xive
, &local_err
);
162 error_report_err(local_err
);
167 monitor_printf(mon
, " LISN PQ EISN CPU/PRIO EQ\n");
169 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
170 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
171 XiveEAS
*eas
= &xive
->eat
[i
];
173 if (!xive_eas_is_valid(eas
)) {
177 monitor_printf(mon
, " %08x %s %c%c%c %s %08x ", i
,
178 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
179 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
180 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
181 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ',
182 xive_eas_is_masked(eas
) ? "M" : " ",
183 (int) xive_get_field64(EAS_END_DATA
, eas
->w
));
185 if (!xive_eas_is_masked(eas
)) {
186 uint32_t end_idx
= xive_get_field64(EAS_END_INDEX
, eas
->w
);
189 assert(end_idx
< xive
->nr_ends
);
190 end
= &xive
->endt
[end_idx
];
192 if (xive_end_is_valid(end
)) {
193 spapr_xive_end_pic_print_info(xive
, end
, mon
);
196 monitor_printf(mon
, "\n");
200 void spapr_xive_mmio_set_enabled(SpaprXive
*xive
, bool enable
)
202 memory_region_set_enabled(&xive
->source
.esb_mmio
, enable
);
203 memory_region_set_enabled(&xive
->tm_mmio
, enable
);
205 /* Disable the END ESBs until a guest OS makes use of them */
206 memory_region_set_enabled(&xive
->end_source
.esb_mmio
, false);
210 * When a Virtual Processor is scheduled to run on a HW thread, the
211 * hypervisor pushes its identifier in the OS CAM line. Emulate the
212 * same behavior under QEMU.
214 void spapr_xive_set_tctx_os_cam(XiveTCTX
*tctx
)
220 spapr_xive_cpu_to_nvt(POWERPC_CPU(tctx
->cs
), &nvt_blk
, &nvt_idx
);
222 nvt_cam
= cpu_to_be32(TM_QW1W2_VO
| xive_nvt_cam_line(nvt_blk
, nvt_idx
));
223 memcpy(&tctx
->regs
[TM_QW1_OS
+ TM_WORD2
], &nvt_cam
, 4);
226 static void spapr_xive_end_reset(XiveEND
*end
)
228 memset(end
, 0, sizeof(*end
));
230 /* switch off the escalation and notification ESBs */
231 end
->w1
= cpu_to_be32(END_W1_ESe_Q
| END_W1_ESn_Q
);
234 static void spapr_xive_reset(void *dev
)
236 SpaprXive
*xive
= SPAPR_XIVE(dev
);
240 * The XiveSource has its own reset handler, which mask off all
244 /* Mask all valid EASs in the IRQ number space. */
245 for (i
= 0; i
< xive
->nr_irqs
; i
++) {
246 XiveEAS
*eas
= &xive
->eat
[i
];
247 if (xive_eas_is_valid(eas
)) {
248 eas
->w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
255 for (i
= 0; i
< xive
->nr_ends
; i
++) {
256 spapr_xive_end_reset(&xive
->endt
[i
]);
260 static void spapr_xive_instance_init(Object
*obj
)
262 SpaprXive
*xive
= SPAPR_XIVE(obj
);
264 object_initialize_child(obj
, "source", &xive
->source
, sizeof(xive
->source
),
265 TYPE_XIVE_SOURCE
, &error_abort
, NULL
);
267 object_initialize_child(obj
, "end_source", &xive
->end_source
,
268 sizeof(xive
->end_source
), TYPE_XIVE_END_SOURCE
,
271 /* Not connected to the KVM XIVE device */
275 static void spapr_xive_realize(DeviceState
*dev
, Error
**errp
)
277 SpaprXive
*xive
= SPAPR_XIVE(dev
);
278 XiveSource
*xsrc
= &xive
->source
;
279 XiveENDSource
*end_xsrc
= &xive
->end_source
;
280 Error
*local_err
= NULL
;
282 if (!xive
->nr_irqs
) {
283 error_setg(errp
, "Number of interrupt needs to be greater 0");
287 if (!xive
->nr_ends
) {
288 error_setg(errp
, "Number of interrupt needs to be greater 0");
293 * Initialize the internal sources, for IPIs and virtual devices.
295 object_property_set_int(OBJECT(xsrc
), xive
->nr_irqs
, "nr-irqs",
297 object_property_add_const_link(OBJECT(xsrc
), "xive", OBJECT(xive
),
299 object_property_set_bool(OBJECT(xsrc
), true, "realized", &local_err
);
301 error_propagate(errp
, local_err
);
304 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xsrc
->esb_mmio
);
307 * Initialize the END ESB source
309 object_property_set_int(OBJECT(end_xsrc
), xive
->nr_irqs
, "nr-ends",
311 object_property_add_const_link(OBJECT(end_xsrc
), "xive", OBJECT(xive
),
313 object_property_set_bool(OBJECT(end_xsrc
), true, "realized", &local_err
);
315 error_propagate(errp
, local_err
);
318 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &end_xsrc
->esb_mmio
);
320 /* Set the mapping address of the END ESB pages after the source ESBs */
321 xive
->end_base
= xive
->vc_base
+ (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
;
324 * Allocate the routing tables
326 xive
->eat
= g_new0(XiveEAS
, xive
->nr_irqs
);
327 xive
->endt
= g_new0(XiveEND
, xive
->nr_ends
);
329 xive
->nodename
= g_strdup_printf("interrupt-controller@%" PRIx64
,
330 xive
->tm_base
+ XIVE_TM_USER_PAGE
* (1 << TM_SHIFT
));
332 qemu_register_reset(spapr_xive_reset
, dev
);
334 /* TIMA initialization */
335 memory_region_init_io(&xive
->tm_mmio
, OBJECT(xive
), &xive_tm_ops
, xive
,
336 "xive.tima", 4ull << TM_SHIFT
);
337 sysbus_init_mmio(SYS_BUS_DEVICE(xive
), &xive
->tm_mmio
);
340 * Map all regions. These will be enabled or disabled at reset and
341 * can also be overridden by KVM memory regions if active
343 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 0, xive
->vc_base
);
344 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 1, xive
->end_base
);
345 sysbus_mmio_map(SYS_BUS_DEVICE(xive
), 2, xive
->tm_base
);
348 static int spapr_xive_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
,
349 uint32_t eas_idx
, XiveEAS
*eas
)
351 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
353 if (eas_idx
>= xive
->nr_irqs
) {
357 *eas
= xive
->eat
[eas_idx
];
361 static int spapr_xive_get_end(XiveRouter
*xrtr
,
362 uint8_t end_blk
, uint32_t end_idx
, XiveEND
*end
)
364 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
366 if (end_idx
>= xive
->nr_ends
) {
370 memcpy(end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
374 static int spapr_xive_write_end(XiveRouter
*xrtr
, uint8_t end_blk
,
375 uint32_t end_idx
, XiveEND
*end
,
378 SpaprXive
*xive
= SPAPR_XIVE(xrtr
);
380 if (end_idx
>= xive
->nr_ends
) {
384 memcpy(&xive
->endt
[end_idx
], end
, sizeof(XiveEND
));
388 static int spapr_xive_get_nvt(XiveRouter
*xrtr
,
389 uint8_t nvt_blk
, uint32_t nvt_idx
, XiveNVT
*nvt
)
391 uint32_t vcpu_id
= spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
392 PowerPCCPU
*cpu
= spapr_find_cpu(vcpu_id
);
395 /* TODO: should we assert() if we can find a NVT ? */
400 * sPAPR does not maintain a NVT table. Return that the NVT is
401 * valid if we have found a matching CPU
403 nvt
->w0
= cpu_to_be32(NVT_W0_VALID
);
407 static int spapr_xive_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
,
408 uint32_t nvt_idx
, XiveNVT
*nvt
,
412 * We don't need to write back to the NVTs because the sPAPR
413 * machine should never hit a non-scheduled NVT. It should never
416 g_assert_not_reached();
419 static XiveTCTX
*spapr_xive_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
)
421 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
423 return spapr_cpu_state(cpu
)->tctx
;
426 static const VMStateDescription vmstate_spapr_xive_end
= {
427 .name
= TYPE_SPAPR_XIVE
"/end",
429 .minimum_version_id
= 1,
430 .fields
= (VMStateField
[]) {
431 VMSTATE_UINT32(w0
, XiveEND
),
432 VMSTATE_UINT32(w1
, XiveEND
),
433 VMSTATE_UINT32(w2
, XiveEND
),
434 VMSTATE_UINT32(w3
, XiveEND
),
435 VMSTATE_UINT32(w4
, XiveEND
),
436 VMSTATE_UINT32(w5
, XiveEND
),
437 VMSTATE_UINT32(w6
, XiveEND
),
438 VMSTATE_UINT32(w7
, XiveEND
),
439 VMSTATE_END_OF_LIST()
443 static const VMStateDescription vmstate_spapr_xive_eas
= {
444 .name
= TYPE_SPAPR_XIVE
"/eas",
446 .minimum_version_id
= 1,
447 .fields
= (VMStateField
[]) {
448 VMSTATE_UINT64(w
, XiveEAS
),
449 VMSTATE_END_OF_LIST()
453 static int vmstate_spapr_xive_pre_save(void *opaque
)
455 if (kvm_irqchip_in_kernel()) {
456 return kvmppc_xive_pre_save(SPAPR_XIVE(opaque
));
463 * Called by the sPAPR IRQ backend 'post_load' method at the machine
466 int spapr_xive_post_load(SpaprXive
*xive
, int version_id
)
468 if (kvm_irqchip_in_kernel()) {
469 return kvmppc_xive_post_load(xive
, version_id
);
475 static const VMStateDescription vmstate_spapr_xive
= {
476 .name
= TYPE_SPAPR_XIVE
,
478 .minimum_version_id
= 1,
479 .pre_save
= vmstate_spapr_xive_pre_save
,
480 .post_load
= NULL
, /* handled at the machine level */
481 .fields
= (VMStateField
[]) {
482 VMSTATE_UINT32_EQUAL(nr_irqs
, SpaprXive
, NULL
),
483 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(eat
, SpaprXive
, nr_irqs
,
484 vmstate_spapr_xive_eas
, XiveEAS
),
485 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(endt
, SpaprXive
, nr_ends
,
486 vmstate_spapr_xive_end
, XiveEND
),
487 VMSTATE_END_OF_LIST()
491 static Property spapr_xive_properties
[] = {
492 DEFINE_PROP_UINT32("nr-irqs", SpaprXive
, nr_irqs
, 0),
493 DEFINE_PROP_UINT32("nr-ends", SpaprXive
, nr_ends
, 0),
494 DEFINE_PROP_UINT64("vc-base", SpaprXive
, vc_base
, SPAPR_XIVE_VC_BASE
),
495 DEFINE_PROP_UINT64("tm-base", SpaprXive
, tm_base
, SPAPR_XIVE_TM_BASE
),
496 DEFINE_PROP_END_OF_LIST(),
499 static void spapr_xive_class_init(ObjectClass
*klass
, void *data
)
501 DeviceClass
*dc
= DEVICE_CLASS(klass
);
502 XiveRouterClass
*xrc
= XIVE_ROUTER_CLASS(klass
);
504 dc
->desc
= "sPAPR XIVE Interrupt Controller";
505 dc
->props
= spapr_xive_properties
;
506 dc
->realize
= spapr_xive_realize
;
507 dc
->vmsd
= &vmstate_spapr_xive
;
509 xrc
->get_eas
= spapr_xive_get_eas
;
510 xrc
->get_end
= spapr_xive_get_end
;
511 xrc
->write_end
= spapr_xive_write_end
;
512 xrc
->get_nvt
= spapr_xive_get_nvt
;
513 xrc
->write_nvt
= spapr_xive_write_nvt
;
514 xrc
->get_tctx
= spapr_xive_get_tctx
;
517 static const TypeInfo spapr_xive_info
= {
518 .name
= TYPE_SPAPR_XIVE
,
519 .parent
= TYPE_XIVE_ROUTER
,
520 .instance_init
= spapr_xive_instance_init
,
521 .instance_size
= sizeof(SpaprXive
),
522 .class_init
= spapr_xive_class_init
,
525 static void spapr_xive_register_types(void)
527 type_register_static(&spapr_xive_info
);
530 type_init(spapr_xive_register_types
)
532 bool spapr_xive_irq_claim(SpaprXive
*xive
, uint32_t lisn
, bool lsi
)
534 XiveSource
*xsrc
= &xive
->source
;
536 if (lisn
>= xive
->nr_irqs
) {
540 xive
->eat
[lisn
].w
|= cpu_to_be64(EAS_VALID
);
542 xive_source_irq_set_lsi(xsrc
, lisn
);
545 if (kvm_irqchip_in_kernel()) {
546 Error
*local_err
= NULL
;
548 kvmppc_xive_source_reset_one(xsrc
, lisn
, &local_err
);
550 error_report_err(local_err
);
558 bool spapr_xive_irq_free(SpaprXive
*xive
, uint32_t lisn
)
560 if (lisn
>= xive
->nr_irqs
) {
564 xive
->eat
[lisn
].w
&= cpu_to_be64(~EAS_VALID
);
571 * The terminology used by the XIVE hcalls is the following :
574 * EQ Event Queue assigned by OS to receive event data
575 * ESB page for source interrupt management
576 * LISN Logical Interrupt Source Number identifying a source in the
578 * EISN Effective Interrupt Source Number used by guest OS to
579 * identify source in the guest
581 * The EAS, END, NVT structures are not exposed.
585 * Linux hosts under OPAL reserve priority 7 for their own escalation
586 * interrupts (DD2.X POWER9). So we only allow the guest to use
589 static bool spapr_xive_priority_is_reserved(uint8_t priority
)
594 case 7: /* OPAL escalation queue */
601 * The H_INT_GET_SOURCE_INFO hcall() is used to obtain the logical
602 * real address of the MMIO page through which the Event State Buffer
603 * entry associated with the value of the "lisn" parameter is managed.
609 * - R5: "lisn" is per "interrupts", "interrupt-map", or
610 * "ibm,xive-lisn-ranges" properties, or as returned by the
611 * ibm,query-interrupt-source-number RTAS call, or as returned
612 * by the H_ALLOCATE_VAS_WINDOW hcall
616 * Bits 0-59: Reserved
617 * Bit 60: H_INT_ESB must be used for Event State Buffer
619 * Bit 61: 1 == LSI 0 == MSI
620 * Bit 62: the full function page supports trigger
621 * Bit 63: Store EOI Supported
622 * - R5: Logical Real address of full function Event State Buffer
623 * management page, -1 if H_INT_ESB hcall flag is set to 1.
624 * - R6: Logical Real Address of trigger only Event State Buffer
625 * management page or -1.
626 * - R7: Power of 2 page size for the ESB management pages returned in
630 #define SPAPR_XIVE_SRC_H_INT_ESB PPC_BIT(60) /* ESB manage with H_INT_ESB */
631 #define SPAPR_XIVE_SRC_LSI PPC_BIT(61) /* Virtual LSI type */
632 #define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
634 #define SPAPR_XIVE_SRC_STORE_EOI PPC_BIT(63) /* Store EOI support */
636 static target_ulong
h_int_get_source_info(PowerPCCPU
*cpu
,
637 SpaprMachineState
*spapr
,
641 SpaprXive
*xive
= spapr
->xive
;
642 XiveSource
*xsrc
= &xive
->source
;
643 target_ulong flags
= args
[0];
644 target_ulong lisn
= args
[1];
646 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
654 if (lisn
>= xive
->nr_irqs
) {
655 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
660 if (!xive_eas_is_valid(&xive
->eat
[lisn
])) {
661 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
667 * All sources are emulated under the main XIVE object and share
668 * the same characteristics.
671 if (!xive_source_esb_has_2page(xsrc
)) {
672 args
[0] |= SPAPR_XIVE_SRC_TRIGGER
;
674 if (xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
) {
675 args
[0] |= SPAPR_XIVE_SRC_STORE_EOI
;
679 * Force the use of the H_INT_ESB hcall in case of an LSI
680 * interrupt. This is necessary under KVM to re-trigger the
681 * interrupt if the level is still asserted
683 if (xive_source_irq_is_lsi(xsrc
, lisn
)) {
684 args
[0] |= SPAPR_XIVE_SRC_H_INT_ESB
| SPAPR_XIVE_SRC_LSI
;
687 if (!(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
688 args
[1] = xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
);
693 if (xive_source_esb_has_2page(xsrc
) &&
694 !(args
[0] & SPAPR_XIVE_SRC_H_INT_ESB
)) {
695 args
[2] = xive
->vc_base
+ xive_source_esb_page(xsrc
, lisn
);
700 if (xive_source_esb_has_2page(xsrc
)) {
701 args
[3] = xsrc
->esb_shift
- 1;
703 args
[3] = xsrc
->esb_shift
;
710 * The H_INT_SET_SOURCE_CONFIG hcall() is used to assign a Logical
711 * Interrupt Source to a target. The Logical Interrupt Source is
712 * designated with the "lisn" parameter and the target is designated
713 * with the "target" and "priority" parameters. Upon return from the
714 * hcall(), no additional interrupts will be directed to the old EQ.
719 * Bits 0-61: Reserved
720 * Bit 62: set the "eisn" in the EAS
721 * Bit 63: masks the interrupt source in the hardware interrupt
722 * control structure. An interrupt masked by this mechanism will
723 * be dropped, but it's source state bits will still be
724 * set. There is no race-free way of unmasking and restoring the
725 * source. Thus this should only be used in interrupts that are
726 * also masked at the source, and only in cases where the
727 * interrupt is not meant to be used for a large amount of time
728 * because no valid target exists for it for example
729 * - R5: "lisn" is per "interrupts", "interrupt-map", or
730 * "ibm,xive-lisn-ranges" properties, or as returned by the
731 * ibm,query-interrupt-source-number RTAS call, or as returned by
732 * the H_ALLOCATE_VAS_WINDOW hcall
733 * - R6: "target" is per "ibm,ppc-interrupt-server#s" or
734 * "ibm,ppc-interrupt-gserver#s"
735 * - R7: "priority" is a valid priority not in
736 * "ibm,plat-res-int-priorities"
737 * - R8: "eisn" is the guest EISN associated with the "lisn"
743 #define SPAPR_XIVE_SRC_SET_EISN PPC_BIT(62)
744 #define SPAPR_XIVE_SRC_MASK PPC_BIT(63)
746 static target_ulong
h_int_set_source_config(PowerPCCPU
*cpu
,
747 SpaprMachineState
*spapr
,
751 SpaprXive
*xive
= spapr
->xive
;
752 XiveEAS eas
, new_eas
;
753 target_ulong flags
= args
[0];
754 target_ulong lisn
= args
[1];
755 target_ulong target
= args
[2];
756 target_ulong priority
= args
[3];
757 target_ulong eisn
= args
[4];
761 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
765 if (flags
& ~(SPAPR_XIVE_SRC_SET_EISN
| SPAPR_XIVE_SRC_MASK
)) {
769 if (lisn
>= xive
->nr_irqs
) {
770 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
775 eas
= xive
->eat
[lisn
];
776 if (!xive_eas_is_valid(&eas
)) {
777 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
782 /* priority 0xff is used to reset the EAS */
783 if (priority
== 0xff) {
784 new_eas
.w
= cpu_to_be64(EAS_VALID
| EAS_MASKED
);
788 if (flags
& SPAPR_XIVE_SRC_MASK
) {
789 new_eas
.w
= eas
.w
| cpu_to_be64(EAS_MASKED
);
791 new_eas
.w
= eas
.w
& cpu_to_be64(~EAS_MASKED
);
794 if (spapr_xive_priority_is_reserved(priority
)) {
795 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
796 " is reserved\n", priority
);
801 * Validate that "target" is part of the list of threads allocated
802 * to the partition. For that, find the END corresponding to the
805 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
809 new_eas
.w
= xive_set_field64(EAS_END_BLOCK
, new_eas
.w
, end_blk
);
810 new_eas
.w
= xive_set_field64(EAS_END_INDEX
, new_eas
.w
, end_idx
);
812 if (flags
& SPAPR_XIVE_SRC_SET_EISN
) {
813 new_eas
.w
= xive_set_field64(EAS_END_DATA
, new_eas
.w
, eisn
);
816 if (kvm_irqchip_in_kernel()) {
817 Error
*local_err
= NULL
;
819 kvmppc_xive_set_source_config(xive
, lisn
, &new_eas
, &local_err
);
821 error_report_err(local_err
);
827 xive
->eat
[lisn
] = new_eas
;
832 * The H_INT_GET_SOURCE_CONFIG hcall() is used to determine to which
833 * target/priority pair is assigned to the specified Logical Interrupt
840 * - R5: "lisn" is per "interrupts", "interrupt-map", or
841 * "ibm,xive-lisn-ranges" properties, or as returned by the
842 * ibm,query-interrupt-source-number RTAS call, or as
843 * returned by the H_ALLOCATE_VAS_WINDOW hcall
846 * - R4: Target to which the specified Logical Interrupt Source is
848 * - R5: Priority to which the specified Logical Interrupt Source is
850 * - R6: EISN for the specified Logical Interrupt Source (this will be
851 * equivalent to the LISN if not changed by H_INT_SET_SOURCE_CONFIG)
853 static target_ulong
h_int_get_source_config(PowerPCCPU
*cpu
,
854 SpaprMachineState
*spapr
,
858 SpaprXive
*xive
= spapr
->xive
;
859 target_ulong flags
= args
[0];
860 target_ulong lisn
= args
[1];
864 uint32_t end_idx
, nvt_idx
;
866 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
874 if (lisn
>= xive
->nr_irqs
) {
875 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
880 eas
= xive
->eat
[lisn
];
881 if (!xive_eas_is_valid(&eas
)) {
882 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
887 /* EAS_END_BLOCK is unused on sPAPR */
888 end_idx
= xive_get_field64(EAS_END_INDEX
, eas
.w
);
890 assert(end_idx
< xive
->nr_ends
);
891 end
= &xive
->endt
[end_idx
];
893 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
894 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
895 args
[0] = spapr_xive_nvt_to_target(nvt_blk
, nvt_idx
);
897 if (xive_eas_is_masked(&eas
)) {
900 args
[1] = xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
903 args
[2] = xive_get_field64(EAS_END_DATA
, eas
.w
);
909 * The H_INT_GET_QUEUE_INFO hcall() is used to get the logical real
910 * address of the notification management page associated with the
911 * specified target and priority.
917 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
918 * "ibm,ppc-interrupt-gserver#s"
919 * - R6: "priority" is a valid priority not in
920 * "ibm,plat-res-int-priorities"
923 * - R4: Logical real address of notification page
924 * - R5: Power of 2 page size of the notification page
926 static target_ulong
h_int_get_queue_info(PowerPCCPU
*cpu
,
927 SpaprMachineState
*spapr
,
931 SpaprXive
*xive
= spapr
->xive
;
932 XiveENDSource
*end_xsrc
= &xive
->end_source
;
933 target_ulong flags
= args
[0];
934 target_ulong target
= args
[1];
935 target_ulong priority
= args
[2];
940 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
949 * H_STATE should be returned if a H_INT_RESET is in progress.
950 * This is not needed when running the emulation under QEMU
953 if (spapr_xive_priority_is_reserved(priority
)) {
954 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
955 " is reserved\n", priority
);
960 * Validate that "target" is part of the list of threads allocated
961 * to the partition. For that, find the END corresponding to the
964 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
968 assert(end_idx
< xive
->nr_ends
);
969 end
= &xive
->endt
[end_idx
];
971 args
[0] = xive
->end_base
+ (1ull << (end_xsrc
->esb_shift
+ 1)) * end_idx
;
972 if (xive_end_is_enqueue(end
)) {
973 args
[1] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
982 * The H_INT_SET_QUEUE_CONFIG hcall() is used to set or reset a EQ for
983 * a given "target" and "priority". It is also used to set the
984 * notification config associated with the EQ. An EQ size of 0 is
985 * used to reset the EQ config for a given target and priority. If
986 * resetting the EQ config, the END associated with the given "target"
987 * and "priority" will be changed to disable queueing.
989 * Upon return from the hcall(), no additional interrupts will be
990 * directed to the old EQ (if one was set). The old EQ (if one was
991 * set) should be investigated for interrupts that occurred prior to
992 * or during the hcall().
997 * Bits 0-62: Reserved
998 * Bit 63: Unconditional Notify (n) per the XIVE spec
999 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1000 * "ibm,ppc-interrupt-gserver#s"
1001 * - R6: "priority" is a valid priority not in
1002 * "ibm,plat-res-int-priorities"
1003 * - R7: "eventQueue": The logical real address of the start of the EQ
1004 * - R8: "eventQueueSize": The power of 2 EQ size per "ibm,xive-eq-sizes"
1010 #define SPAPR_XIVE_END_ALWAYS_NOTIFY PPC_BIT(63)
1012 static target_ulong
h_int_set_queue_config(PowerPCCPU
*cpu
,
1013 SpaprMachineState
*spapr
,
1014 target_ulong opcode
,
1017 SpaprXive
*xive
= spapr
->xive
;
1018 target_ulong flags
= args
[0];
1019 target_ulong target
= args
[1];
1020 target_ulong priority
= args
[2];
1021 target_ulong qpage
= args
[3];
1022 target_ulong qsize
= args
[4];
1024 uint8_t end_blk
, nvt_blk
;
1025 uint32_t end_idx
, nvt_idx
;
1027 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1031 if (flags
& ~SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1036 * H_STATE should be returned if a H_INT_RESET is in progress.
1037 * This is not needed when running the emulation under QEMU
1040 if (spapr_xive_priority_is_reserved(priority
)) {
1041 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1042 " is reserved\n", priority
);
1047 * Validate that "target" is part of the list of threads allocated
1048 * to the partition. For that, find the END corresponding to the
1052 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1056 assert(end_idx
< xive
->nr_ends
);
1057 memcpy(&end
, &xive
->endt
[end_idx
], sizeof(XiveEND
));
1064 if (!QEMU_IS_ALIGNED(qpage
, 1ul << qsize
)) {
1065 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: EQ @0x%" HWADDR_PRIx
1066 " is not naturally aligned with %" HWADDR_PRIx
"\n",
1067 qpage
, (hwaddr
)1 << qsize
);
1070 end
.w2
= cpu_to_be32((qpage
>> 32) & 0x0fffffff);
1071 end
.w3
= cpu_to_be32(qpage
& 0xffffffff);
1072 end
.w0
|= cpu_to_be32(END_W0_ENQUEUE
);
1073 end
.w0
= xive_set_field32(END_W0_QSIZE
, end
.w0
, qsize
- 12);
1076 /* reset queue and disable queueing */
1077 spapr_xive_end_reset(&end
);
1081 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid EQ size %"PRIx64
"\n",
1087 hwaddr plen
= 1 << qsize
;
1091 * Validate the guest EQ. We should also check that the queue
1092 * has been zeroed by the OS.
1094 eq
= address_space_map(CPU(cpu
)->as
, qpage
, &plen
, true,
1095 MEMTXATTRS_UNSPECIFIED
);
1096 if (plen
!= 1 << qsize
) {
1097 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to map EQ @0x%"
1098 HWADDR_PRIx
"\n", qpage
);
1101 address_space_unmap(CPU(cpu
)->as
, eq
, plen
, true, plen
);
1104 /* "target" should have been validated above */
1105 if (spapr_xive_target_to_nvt(target
, &nvt_blk
, &nvt_idx
)) {
1106 g_assert_not_reached();
1110 * Ensure the priority and target are correctly set (they will not
1111 * be right after allocation)
1113 end
.w6
= xive_set_field32(END_W6_NVT_BLOCK
, 0ul, nvt_blk
) |
1114 xive_set_field32(END_W6_NVT_INDEX
, 0ul, nvt_idx
);
1115 end
.w7
= xive_set_field32(END_W7_F0_PRIORITY
, 0ul, priority
);
1117 if (flags
& SPAPR_XIVE_END_ALWAYS_NOTIFY
) {
1118 end
.w0
|= cpu_to_be32(END_W0_UCOND_NOTIFY
);
1120 end
.w0
&= cpu_to_be32((uint32_t)~END_W0_UCOND_NOTIFY
);
1124 * The generation bit for the END starts at 1 and The END page
1125 * offset counter starts at 0.
1127 end
.w1
= cpu_to_be32(END_W1_GENERATION
) |
1128 xive_set_field32(END_W1_PAGE_OFF
, 0ul, 0ul);
1129 end
.w0
|= cpu_to_be32(END_W0_VALID
);
1132 * TODO: issue syncs required to ensure all in-flight interrupts
1133 * are complete on the old END
1137 if (kvm_irqchip_in_kernel()) {
1138 Error
*local_err
= NULL
;
1140 kvmppc_xive_set_queue_config(xive
, end_blk
, end_idx
, &end
, &local_err
);
1142 error_report_err(local_err
);
1148 memcpy(&xive
->endt
[end_idx
], &end
, sizeof(XiveEND
));
1153 * The H_INT_GET_QUEUE_CONFIG hcall() is used to get a EQ for a given
1154 * target and priority.
1159 * Bits 0-62: Reserved
1160 * Bit 63: Debug: Return debug data
1161 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1162 * "ibm,ppc-interrupt-gserver#s"
1163 * - R6: "priority" is a valid priority not in
1164 * "ibm,plat-res-int-priorities"
1168 * Bits 0-61: Reserved
1169 * Bit 62: The value of Event Queue Generation Number (g) per
1170 * the XIVE spec if "Debug" = 1
1171 * Bit 63: The value of Unconditional Notify (n) per the XIVE spec
1172 * - R5: The logical real address of the start of the EQ
1173 * - R6: The power of 2 EQ size per "ibm,xive-eq-sizes"
1174 * - R7: The value of Event Queue Offset Counter per XIVE spec
1175 * if "Debug" = 1, else 0
1179 #define SPAPR_XIVE_END_DEBUG PPC_BIT(63)
1181 static target_ulong
h_int_get_queue_config(PowerPCCPU
*cpu
,
1182 SpaprMachineState
*spapr
,
1183 target_ulong opcode
,
1186 SpaprXive
*xive
= spapr
->xive
;
1187 target_ulong flags
= args
[0];
1188 target_ulong target
= args
[1];
1189 target_ulong priority
= args
[2];
1194 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1198 if (flags
& ~SPAPR_XIVE_END_DEBUG
) {
1203 * H_STATE should be returned if a H_INT_RESET is in progress.
1204 * This is not needed when running the emulation under QEMU
1207 if (spapr_xive_priority_is_reserved(priority
)) {
1208 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: priority " TARGET_FMT_ld
1209 " is reserved\n", priority
);
1214 * Validate that "target" is part of the list of threads allocated
1215 * to the partition. For that, find the END corresponding to the
1218 if (spapr_xive_target_to_end(target
, priority
, &end_blk
, &end_idx
)) {
1222 assert(end_idx
< xive
->nr_ends
);
1223 end
= &xive
->endt
[end_idx
];
1226 if (xive_end_is_notify(end
)) {
1227 args
[0] |= SPAPR_XIVE_END_ALWAYS_NOTIFY
;
1230 if (xive_end_is_enqueue(end
)) {
1231 args
[1] = xive_end_qaddr(end
);
1232 args
[2] = xive_get_field32(END_W0_QSIZE
, end
->w0
) + 12;
1238 if (kvm_irqchip_in_kernel()) {
1239 Error
*local_err
= NULL
;
1241 kvmppc_xive_get_queue_config(xive
, end_blk
, end_idx
, end
, &local_err
);
1243 error_report_err(local_err
);
1248 /* TODO: do we need any locking on the END ? */
1249 if (flags
& SPAPR_XIVE_END_DEBUG
) {
1250 /* Load the event queue generation number into the return flags */
1251 args
[0] |= (uint64_t)xive_get_field32(END_W1_GENERATION
, end
->w1
) << 62;
1253 /* Load R7 with the event queue offset counter */
1254 args
[3] = xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1263 * The H_INT_SET_OS_REPORTING_LINE hcall() is used to set the
1264 * reporting cache line pair for the calling thread. The reporting
1265 * cache lines will contain the OS interrupt context when the OS
1266 * issues a CI store byte to @TIMA+0xC10 to acknowledge the OS
1267 * interrupt. The reporting cache lines can be reset by inputting -1
1268 * in "reportingLine". Issuing the CI store byte without reporting
1269 * cache lines registered will result in the data not being accessible
1275 * Bits 0-63: Reserved
1276 * - R5: "reportingLine": The logical real address of the reporting cache
1282 static target_ulong
h_int_set_os_reporting_line(PowerPCCPU
*cpu
,
1283 SpaprMachineState
*spapr
,
1284 target_ulong opcode
,
1287 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1292 * H_STATE should be returned if a H_INT_RESET is in progress.
1293 * This is not needed when running the emulation under QEMU
1296 /* TODO: H_INT_SET_OS_REPORTING_LINE */
1301 * The H_INT_GET_OS_REPORTING_LINE hcall() is used to get the logical
1302 * real address of the reporting cache line pair set for the input
1303 * "target". If no reporting cache line pair has been set, -1 is
1309 * Bits 0-63: Reserved
1310 * - R5: "target" is per "ibm,ppc-interrupt-server#s" or
1311 * "ibm,ppc-interrupt-gserver#s"
1312 * - R6: "reportingLine": The logical real address of the reporting
1316 * - R4: The logical real address of the reporting line if set, else -1
1318 static target_ulong
h_int_get_os_reporting_line(PowerPCCPU
*cpu
,
1319 SpaprMachineState
*spapr
,
1320 target_ulong opcode
,
1323 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1328 * H_STATE should be returned if a H_INT_RESET is in progress.
1329 * This is not needed when running the emulation under QEMU
1332 /* TODO: H_INT_GET_OS_REPORTING_LINE */
1337 * The H_INT_ESB hcall() is used to issue a load or store to the ESB
1338 * page for the input "lisn". This hcall is only supported for LISNs
1339 * that have the ESB hcall flag set to 1 when returned from hcall()
1340 * H_INT_GET_SOURCE_INFO.
1345 * Bits 0-62: Reserved
1346 * bit 63: Store: Store=1, store operation, else load operation
1347 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1348 * "ibm,xive-lisn-ranges" properties, or as returned by the
1349 * ibm,query-interrupt-source-number RTAS call, or as
1350 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1351 * - R6: "esbOffset" is the offset into the ESB page for the load or
1353 * - R7: "storeData" is the data to write for a store operation
1356 * - R4: The value of the load if load operation, else -1
1359 #define SPAPR_XIVE_ESB_STORE PPC_BIT(63)
1361 static target_ulong
h_int_esb(PowerPCCPU
*cpu
,
1362 SpaprMachineState
*spapr
,
1363 target_ulong opcode
,
1366 SpaprXive
*xive
= spapr
->xive
;
1368 target_ulong flags
= args
[0];
1369 target_ulong lisn
= args
[1];
1370 target_ulong offset
= args
[2];
1371 target_ulong data
= args
[3];
1373 XiveSource
*xsrc
= &xive
->source
;
1375 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1379 if (flags
& ~SPAPR_XIVE_ESB_STORE
) {
1383 if (lisn
>= xive
->nr_irqs
) {
1384 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1389 eas
= xive
->eat
[lisn
];
1390 if (!xive_eas_is_valid(&eas
)) {
1391 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1396 if (offset
> (1ull << xsrc
->esb_shift
)) {
1400 if (kvm_irqchip_in_kernel()) {
1401 args
[0] = kvmppc_xive_esb_rw(xsrc
, lisn
, offset
, data
,
1402 flags
& SPAPR_XIVE_ESB_STORE
);
1404 mmio_addr
= xive
->vc_base
+ xive_source_esb_mgmt(xsrc
, lisn
) + offset
;
1406 if (dma_memory_rw(&address_space_memory
, mmio_addr
, &data
, 8,
1407 (flags
& SPAPR_XIVE_ESB_STORE
))) {
1408 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to access ESB @0x%"
1409 HWADDR_PRIx
"\n", mmio_addr
);
1412 args
[0] = (flags
& SPAPR_XIVE_ESB_STORE
) ? -1 : data
;
1418 * The H_INT_SYNC hcall() is used to issue hardware syncs that will
1419 * ensure any in flight events for the input lisn are in the event
1425 * Bits 0-63: Reserved
1426 * - R5: "lisn" is per "interrupts", "interrupt-map", or
1427 * "ibm,xive-lisn-ranges" properties, or as returned by the
1428 * ibm,query-interrupt-source-number RTAS call, or as
1429 * returned by the H_ALLOCATE_VAS_WINDOW hcall
1434 static target_ulong
h_int_sync(PowerPCCPU
*cpu
,
1435 SpaprMachineState
*spapr
,
1436 target_ulong opcode
,
1439 SpaprXive
*xive
= spapr
->xive
;
1441 target_ulong flags
= args
[0];
1442 target_ulong lisn
= args
[1];
1444 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1452 if (lisn
>= xive
->nr_irqs
) {
1453 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN " TARGET_FMT_lx
"\n",
1458 eas
= xive
->eat
[lisn
];
1459 if (!xive_eas_is_valid(&eas
)) {
1460 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Invalid LISN " TARGET_FMT_lx
"\n",
1466 * H_STATE should be returned if a H_INT_RESET is in progress.
1467 * This is not needed when running the emulation under QEMU
1471 * This is not real hardware. Nothing to be done unless when
1475 if (kvm_irqchip_in_kernel()) {
1476 Error
*local_err
= NULL
;
1478 kvmppc_xive_sync_source(xive
, lisn
, &local_err
);
1480 error_report_err(local_err
);
1488 * The H_INT_RESET hcall() is used to reset all of the partition's
1489 * interrupt exploitation structures to their initial state. This
1490 * means losing all previously set interrupt state set via
1491 * H_INT_SET_SOURCE_CONFIG and H_INT_SET_QUEUE_CONFIG.
1496 * Bits 0-63: Reserved
1501 static target_ulong
h_int_reset(PowerPCCPU
*cpu
,
1502 SpaprMachineState
*spapr
,
1503 target_ulong opcode
,
1506 SpaprXive
*xive
= spapr
->xive
;
1507 target_ulong flags
= args
[0];
1509 if (!spapr_ovec_test(spapr
->ov5_cas
, OV5_XIVE_EXPLOIT
)) {
1517 device_reset(DEVICE(xive
));
1519 if (kvm_irqchip_in_kernel()) {
1520 Error
*local_err
= NULL
;
1522 kvmppc_xive_reset(xive
, &local_err
);
1524 error_report_err(local_err
);
1531 void spapr_xive_hcall_init(SpaprMachineState
*spapr
)
1533 spapr_register_hypercall(H_INT_GET_SOURCE_INFO
, h_int_get_source_info
);
1534 spapr_register_hypercall(H_INT_SET_SOURCE_CONFIG
, h_int_set_source_config
);
1535 spapr_register_hypercall(H_INT_GET_SOURCE_CONFIG
, h_int_get_source_config
);
1536 spapr_register_hypercall(H_INT_GET_QUEUE_INFO
, h_int_get_queue_info
);
1537 spapr_register_hypercall(H_INT_SET_QUEUE_CONFIG
, h_int_set_queue_config
);
1538 spapr_register_hypercall(H_INT_GET_QUEUE_CONFIG
, h_int_get_queue_config
);
1539 spapr_register_hypercall(H_INT_SET_OS_REPORTING_LINE
,
1540 h_int_set_os_reporting_line
);
1541 spapr_register_hypercall(H_INT_GET_OS_REPORTING_LINE
,
1542 h_int_get_os_reporting_line
);
1543 spapr_register_hypercall(H_INT_ESB
, h_int_esb
);
1544 spapr_register_hypercall(H_INT_SYNC
, h_int_sync
);
1545 spapr_register_hypercall(H_INT_RESET
, h_int_reset
);
1548 void spapr_dt_xive(SpaprMachineState
*spapr
, uint32_t nr_servers
, void *fdt
,
1551 SpaprXive
*xive
= spapr
->xive
;
1553 uint64_t timas
[2 * 2];
1554 /* Interrupt number ranges for the IPIs */
1555 uint32_t lisn_ranges
[] = {
1557 cpu_to_be32(nr_servers
),
1560 * EQ size - the sizes of pages supported by the system 4K, 64K,
1561 * 2M, 16M. We only advertise 64K for the moment.
1563 uint32_t eq_sizes
[] = {
1564 cpu_to_be32(16), /* 64K */
1567 * The following array is in sync with the reserved priorities
1568 * defined by the 'spapr_xive_priority_is_reserved' routine.
1570 uint32_t plat_res_int_priorities
[] = {
1571 cpu_to_be32(7), /* start */
1572 cpu_to_be32(0xf8), /* count */
1575 /* Thread Interrupt Management Area : User (ring 3) and OS (ring 2) */
1576 timas
[0] = cpu_to_be64(xive
->tm_base
+
1577 XIVE_TM_USER_PAGE
* (1ull << TM_SHIFT
));
1578 timas
[1] = cpu_to_be64(1ull << TM_SHIFT
);
1579 timas
[2] = cpu_to_be64(xive
->tm_base
+
1580 XIVE_TM_OS_PAGE
* (1ull << TM_SHIFT
));
1581 timas
[3] = cpu_to_be64(1ull << TM_SHIFT
);
1583 _FDT(node
= fdt_add_subnode(fdt
, 0, xive
->nodename
));
1585 _FDT(fdt_setprop_string(fdt
, node
, "device_type", "power-ivpe"));
1586 _FDT(fdt_setprop(fdt
, node
, "reg", timas
, sizeof(timas
)));
1588 _FDT(fdt_setprop_string(fdt
, node
, "compatible", "ibm,power-ivpe"));
1589 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-eq-sizes", eq_sizes
,
1591 _FDT(fdt_setprop(fdt
, node
, "ibm,xive-lisn-ranges", lisn_ranges
,
1592 sizeof(lisn_ranges
)));
1594 /* For Linux to link the LSIs to the interrupt controller. */
1595 _FDT(fdt_setprop(fdt
, node
, "interrupt-controller", NULL
, 0));
1596 _FDT(fdt_setprop_cell(fdt
, node
, "#interrupt-cells", 2));
1599 _FDT(fdt_setprop_cell(fdt
, node
, "linux,phandle", phandle
));
1600 _FDT(fdt_setprop_cell(fdt
, node
, "phandle", phandle
));
1603 * The "ibm,plat-res-int-priorities" property defines the priority
1604 * ranges reserved by the hypervisor
1606 _FDT(fdt_setprop(fdt
, 0, "ibm,plat-res-int-priorities",
1607 plat_res_int_priorities
, sizeof(plat_res_int_priorities
)));