hw/intc/xics.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "qemu-common.h"
  31 #include "cpu.h"
  32 #include "hw/hw.h"
  33 #include "trace.h"
  34 #include "qemu/timer.h"
  35 #include "hw/ppc/xics.h"
  36 #include "qemu/error-report.h"
  37 #include "qapi/visitor.h"
  38 #include "monitor/monitor.h"
  39 #include "hw/intc/intc.h"
  40
  41 int xics_get_cpu_index_by_dt_id(int cpu_dt_id)
  42 {
  43     PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
  44
  45     if (cpu) {
  46         return cpu->parent_obj.cpu_index;
  47     }
  48
  49     return -1;
  50 }
  51
  52 void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu)
  53 {
  54     CPUState *cs = CPU(cpu);
  55     ICPState *ss = xics_icp_get(xi, cs->cpu_index);
  56
  57     assert(ss);
  58     assert(cs == ss->cs);
  59
  60     ss->output = NULL;
  61     ss->cs = NULL;
  62 }
  63
  64 void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu)
  65 {
  66     CPUState *cs = CPU(cpu);
  67     CPUPPCState *env = &cpu->env;
  68     ICPState *ss = xics_icp_get(xi, cs->cpu_index);
  69     ICPStateClass *icpc;
  70
  71     assert(ss);
  72
  73     ss->cs = cs;
  74
  75     icpc = ICP_GET_CLASS(ss);
  76     if (icpc->cpu_setup) {
  77         icpc->cpu_setup(ss, cpu);
  78     }
  79
  80     switch (PPC_INPUT(env)) {
  81     case PPC_FLAGS_INPUT_POWER7:
  82         ss->output = env->irq_inputs[POWER7_INPUT_INT];
  83         break;
  84
  85     case PPC_FLAGS_INPUT_970:
  86         ss->output = env->irq_inputs[PPC970_INPUT_INT];
  87         break;
  88
  89     default:
  90         error_report("XICS interrupt controller does not support this CPU "
  91                      "bus model");
  92         abort();
  93     }
  94 }
  95
  96 static void icp_pic_print_info(InterruptStatsProvider *obj,
  97                            Monitor *mon)
  98 {
  99     ICPState *icp = ICP(obj);
 100     int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
 101
 102     if (!icp->output) {
 103         return;
 104     }
 105     monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
 106                    cpu_index, icp->xirr, icp->xirr_owner,
 107                    icp->pending_priority, icp->mfrr);
 108 }
 109
 110 static void ics_simple_pic_print_info(InterruptStatsProvider *obj,
 111                                       Monitor *mon)
 112 {
 113     ICSState *ics = ICS_SIMPLE(obj);
 114     uint32_t i;
 115
 116     monitor_printf(mon, "ICS %4x..%4x %p\n",
 117                    ics->offset, ics->offset + ics->nr_irqs - 1, ics);
 118
 119     if (!ics->irqs) {
 120         return;
 121     }
 122
 123     for (i = 0; i < ics->nr_irqs; i++) {
 124         ICSIRQState *irq = ics->irqs + i;
 125
 126         if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
 127             continue;
 128         }
 129         monitor_printf(mon, "  %4x %s %02x %02x\n",
 130                        ics->offset + i,
 131                        (irq->flags & XICS_FLAGS_IRQ_LSI) ?
 132                        "LSI" : "MSI",
 133                        irq->priority, irq->status);
 134     }
 135 }
 136
 137 /*
 138  * ICP: Presentation layer
 139  */
 140
 141 #define XISR_MASK  0x00ffffff
 142 #define CPPR_MASK  0xff000000
 143
 144 #define XISR(ss)   (((ss)->xirr) & XISR_MASK)
 145 #define CPPR(ss)   (((ss)->xirr) >> 24)
 146
 147 static void ics_reject(ICSState *ics, uint32_t nr)
 148 {
 149     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
 150
 151     if (k->reject) {
 152         k->reject(ics, nr);
 153     }
 154 }
 155
 156 void ics_resend(ICSState *ics)
 157 {
 158     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
 159
 160     if (k->resend) {
 161         k->resend(ics);
 162     }
 163 }
 164
 165 static void ics_eoi(ICSState *ics, int nr)
 166 {
 167     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
 168
 169     if (k->eoi) {
 170         k->eoi(ics, nr);
 171     }
 172 }
 173
 174 static void icp_check_ipi(ICPState *ss)
 175 {
 176     if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
 177         return;
 178     }
 179
 180     trace_xics_icp_check_ipi(ss->cs->cpu_index, ss->mfrr);
 181
 182     if (XISR(ss) && ss->xirr_owner) {
 183         ics_reject(ss->xirr_owner, XISR(ss));
 184     }
 185
 186     ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
 187     ss->pending_priority = ss->mfrr;
 188     ss->xirr_owner = NULL;
 189     qemu_irq_raise(ss->output);
 190 }
 191
 192 void icp_resend(ICPState *ss)
 193 {
 194     XICSFabric *xi = ss->xics;
 195     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 196
 197     if (ss->mfrr < CPPR(ss)) {
 198         icp_check_ipi(ss);
 199     }
 200
 201     xic->ics_resend(xi);
 202 }
 203
 204 void icp_set_cppr(ICPState *ss, uint8_t cppr)
 205 {
 206     uint8_t old_cppr;
 207     uint32_t old_xisr;
 208
 209     old_cppr = CPPR(ss);
 210     ss->xirr = (ss->xirr & ~CPPR_MASK) | (cppr << 24);
 211
 212     if (cppr < old_cppr) {
 213         if (XISR(ss) && (cppr <= ss->pending_priority)) {
 214             old_xisr = XISR(ss);
 215             ss->xirr &= ~XISR_MASK; /* Clear XISR */
 216             ss->pending_priority = 0xff;
 217             qemu_irq_lower(ss->output);
 218             if (ss->xirr_owner) {
 219                 ics_reject(ss->xirr_owner, old_xisr);
 220                 ss->xirr_owner = NULL;
 221             }
 222         }
 223     } else {
 224         if (!XISR(ss)) {
 225             icp_resend(ss);
 226         }
 227     }
 228 }
 229
 230 void icp_set_mfrr(ICPState *ss, uint8_t mfrr)
 231 {
 232     ss->mfrr = mfrr;
 233     if (mfrr < CPPR(ss)) {
 234         icp_check_ipi(ss);
 235     }
 236 }
 237
 238 uint32_t icp_accept(ICPState *ss)
 239 {
 240     uint32_t xirr = ss->xirr;
 241
 242     qemu_irq_lower(ss->output);
 243     ss->xirr = ss->pending_priority << 24;
 244     ss->pending_priority = 0xff;
 245     ss->xirr_owner = NULL;
 246
 247     trace_xics_icp_accept(xirr, ss->xirr);
 248
 249     return xirr;
 250 }
 251
 252 uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr)
 253 {
 254     if (mfrr) {
 255         *mfrr = ss->mfrr;
 256     }
 257     return ss->xirr;
 258 }
 259
 260 void icp_eoi(ICPState *ss, uint32_t xirr)
 261 {
 262     XICSFabric *xi = ss->xics;
 263     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 264     ICSState *ics;
 265     uint32_t irq;
 266
 267     /* Send EOI -> ICS */
 268     ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
 269     trace_xics_icp_eoi(ss->cs->cpu_index, xirr, ss->xirr);
 270     irq = xirr & XISR_MASK;
 271
 272     ics = xic->ics_get(xi, irq);
 273     if (ics) {
 274         ics_eoi(ics, irq);
 275     }
 276     if (!XISR(ss)) {
 277         icp_resend(ss);
 278     }
 279 }
 280
 281 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
 282 {
 283     ICPState *ss = xics_icp_get(ics->xics, server);
 284
 285     trace_xics_icp_irq(server, nr, priority);
 286
 287     if ((priority >= CPPR(ss))
 288         || (XISR(ss) && (ss->pending_priority <= priority))) {
 289         ics_reject(ics, nr);
 290     } else {
 291         if (XISR(ss) && ss->xirr_owner) {
 292             ics_reject(ss->xirr_owner, XISR(ss));
 293             ss->xirr_owner = NULL;
 294         }
 295         ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
 296         ss->xirr_owner = ics;
 297         ss->pending_priority = priority;
 298         trace_xics_icp_raise(ss->xirr, ss->pending_priority);
 299         qemu_irq_raise(ss->output);
 300     }
 301 }
 302
 303 static void icp_dispatch_pre_save(void *opaque)
 304 {
 305     ICPState *ss = opaque;
 306     ICPStateClass *info = ICP_GET_CLASS(ss);
 307
 308     if (info->pre_save) {
 309         info->pre_save(ss);
 310     }
 311 }
 312
 313 static int icp_dispatch_post_load(void *opaque, int version_id)
 314 {
 315     ICPState *ss = opaque;
 316     ICPStateClass *info = ICP_GET_CLASS(ss);
 317
 318     if (info->post_load) {
 319         return info->post_load(ss, version_id);
 320     }
 321
 322     return 0;
 323 }
 324
 325 static const VMStateDescription vmstate_icp_server = {
 326     .name = "icp/server",
 327     .version_id = 1,
 328     .minimum_version_id = 1,
 329     .pre_save = icp_dispatch_pre_save,
 330     .post_load = icp_dispatch_post_load,
 331     .fields = (VMStateField[]) {
 332         /* Sanity check */
 333         VMSTATE_UINT32(xirr, ICPState),
 334         VMSTATE_UINT8(pending_priority, ICPState),
 335         VMSTATE_UINT8(mfrr, ICPState),
 336         VMSTATE_END_OF_LIST()
 337     },
 338 };
 339
 340 static void icp_reset(DeviceState *dev)
 341 {
 342     ICPState *icp = ICP(dev);
 343
 344     icp->xirr = 0;
 345     icp->pending_priority = 0xff;
 346     icp->mfrr = 0xff;
 347
 348     /* Make all outputs are deasserted */
 349     qemu_set_irq(icp->output, 0);
 350 }
 351
 352 static void icp_realize(DeviceState *dev, Error **errp)
 353 {
 354     ICPState *icp = ICP(dev);
 355     Object *obj;
 356     Error *err = NULL;
 357
 358     obj = object_property_get_link(OBJECT(dev), "xics", &err);
 359     if (!obj) {
 360         error_setg(errp, "%s: required link 'xics' not found: %s",
 361                    __func__, error_get_pretty(err));
 362         return;
 363     }
 364
 365     icp->xics = XICS_FABRIC(obj);
 366 }
 367
 368
 369 static void icp_class_init(ObjectClass *klass, void *data)
 370 {
 371     DeviceClass *dc = DEVICE_CLASS(klass);
 372     InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass);
 373
 374     dc->reset = icp_reset;
 375     dc->vmsd = &vmstate_icp_server;
 376     dc->realize = icp_realize;
 377     ic->print_info = icp_pic_print_info;
 378 }
 379
 380 static const TypeInfo icp_info = {
 381     .name = TYPE_ICP,
 382     .parent = TYPE_DEVICE,
 383     .instance_size = sizeof(ICPState),
 384     .class_init = icp_class_init,
 385     .class_size = sizeof(ICPStateClass),
 386     .interfaces = (InterfaceInfo[]) {
 387         { TYPE_INTERRUPT_STATS_PROVIDER },
 388         { }
 389     },
 390 };
 391
 392 /*
 393  * ICS: Source layer
 394  */
 395 static void ics_simple_resend_msi(ICSState *ics, int srcno)
 396 {
 397     ICSIRQState *irq = ics->irqs + srcno;
 398
 399     /* FIXME: filter by server#? */
 400     if (irq->status & XICS_STATUS_REJECTED) {
 401         irq->status &= ~XICS_STATUS_REJECTED;
 402         if (irq->priority != 0xff) {
 403             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 404         }
 405     }
 406 }
 407
 408 static void ics_simple_resend_lsi(ICSState *ics, int srcno)
 409 {
 410     ICSIRQState *irq = ics->irqs + srcno;
 411
 412     if ((irq->priority != 0xff)
 413         && (irq->status & XICS_STATUS_ASSERTED)
 414         && !(irq->status & XICS_STATUS_SENT)) {
 415         irq->status |= XICS_STATUS_SENT;
 416         icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 417     }
 418 }
 419
 420 static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val)
 421 {
 422     ICSIRQState *irq = ics->irqs + srcno;
 423
 424     trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset);
 425
 426     if (val) {
 427         if (irq->priority == 0xff) {
 428             irq->status |= XICS_STATUS_MASKED_PENDING;
 429             trace_xics_masked_pending();
 430         } else  {
 431             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 432         }
 433     }
 434 }
 435
 436 static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val)
 437 {
 438     ICSIRQState *irq = ics->irqs + srcno;
 439
 440     trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset);
 441     if (val) {
 442         irq->status |= XICS_STATUS_ASSERTED;
 443     } else {
 444         irq->status &= ~XICS_STATUS_ASSERTED;
 445     }
 446     ics_simple_resend_lsi(ics, srcno);
 447 }
 448
 449 static void ics_simple_set_irq(void *opaque, int srcno, int val)
 450 {
 451     ICSState *ics = (ICSState *)opaque;
 452
 453     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 454         ics_simple_set_irq_lsi(ics, srcno, val);
 455     } else {
 456         ics_simple_set_irq_msi(ics, srcno, val);
 457     }
 458 }
 459
 460 static void ics_simple_write_xive_msi(ICSState *ics, int srcno)
 461 {
 462     ICSIRQState *irq = ics->irqs + srcno;
 463
 464     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
 465         || (irq->priority == 0xff)) {
 466         return;
 467     }
 468
 469     irq->status &= ~XICS_STATUS_MASKED_PENDING;
 470     icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 471 }
 472
 473 static void ics_simple_write_xive_lsi(ICSState *ics, int srcno)
 474 {
 475     ics_simple_resend_lsi(ics, srcno);
 476 }
 477
 478 void ics_simple_write_xive(ICSState *ics, int srcno, int server,
 479                            uint8_t priority, uint8_t saved_priority)
 480 {
 481     ICSIRQState *irq = ics->irqs + srcno;
 482
 483     irq->server = server;
 484     irq->priority = priority;
 485     irq->saved_priority = saved_priority;
 486
 487     trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server,
 488                                      priority);
 489
 490     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 491         ics_simple_write_xive_lsi(ics, srcno);
 492     } else {
 493         ics_simple_write_xive_msi(ics, srcno);
 494     }
 495 }
 496
 497 static void ics_simple_reject(ICSState *ics, uint32_t nr)
 498 {
 499     ICSIRQState *irq = ics->irqs + nr - ics->offset;
 500
 501     trace_xics_ics_simple_reject(nr, nr - ics->offset);
 502     if (irq->flags & XICS_FLAGS_IRQ_MSI) {
 503         irq->status |= XICS_STATUS_REJECTED;
 504     } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
 505         irq->status &= ~XICS_STATUS_SENT;
 506     }
 507 }
 508
 509 static void ics_simple_resend(ICSState *ics)
 510 {
 511     int i;
 512
 513     for (i = 0; i < ics->nr_irqs; i++) {
 514         /* FIXME: filter by server#? */
 515         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
 516             ics_simple_resend_lsi(ics, i);
 517         } else {
 518             ics_simple_resend_msi(ics, i);
 519         }
 520     }
 521 }
 522
 523 static void ics_simple_eoi(ICSState *ics, uint32_t nr)
 524 {
 525     int srcno = nr - ics->offset;
 526     ICSIRQState *irq = ics->irqs + srcno;
 527
 528     trace_xics_ics_simple_eoi(nr);
 529
 530     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 531         irq->status &= ~XICS_STATUS_SENT;
 532     }
 533 }
 534
 535 static void ics_simple_reset(DeviceState *dev)
 536 {
 537     ICSState *ics = ICS_SIMPLE(dev);
 538     int i;
 539     uint8_t flags[ics->nr_irqs];
 540
 541     for (i = 0; i < ics->nr_irqs; i++) {
 542         flags[i] = ics->irqs[i].flags;
 543     }
 544
 545     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
 546
 547     for (i = 0; i < ics->nr_irqs; i++) {
 548         ics->irqs[i].priority = 0xff;
 549         ics->irqs[i].saved_priority = 0xff;
 550         ics->irqs[i].flags = flags[i];
 551     }
 552 }
 553
 554 static int ics_simple_post_load(ICSState *ics, int version_id)
 555 {
 556     XICSFabric *xi = ics->xics;
 557     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 558
 559     xic->icp_resend(xi);
 560     return 0;
 561 }
 562
 563 static void ics_simple_dispatch_pre_save(void *opaque)
 564 {
 565     ICSState *ics = opaque;
 566     ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
 567
 568     if (info->pre_save) {
 569         info->pre_save(ics);
 570     }
 571 }
 572
 573 static int ics_simple_dispatch_post_load(void *opaque, int version_id)
 574 {
 575     ICSState *ics = opaque;
 576     ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
 577
 578     if (info->post_load) {
 579         return info->post_load(ics, version_id);
 580     }
 581
 582     return 0;
 583 }
 584
 585 static const VMStateDescription vmstate_ics_simple_irq = {
 586     .name = "ics/irq",
 587     .version_id = 2,
 588     .minimum_version_id = 1,
 589     .fields = (VMStateField[]) {
 590         VMSTATE_UINT32(server, ICSIRQState),
 591         VMSTATE_UINT8(priority, ICSIRQState),
 592         VMSTATE_UINT8(saved_priority, ICSIRQState),
 593         VMSTATE_UINT8(status, ICSIRQState),
 594         VMSTATE_UINT8(flags, ICSIRQState),
 595         VMSTATE_END_OF_LIST()
 596     },
 597 };
 598
 599 static const VMStateDescription vmstate_ics_simple = {
 600     .name = "ics",
 601     .version_id = 1,
 602     .minimum_version_id = 1,
 603     .pre_save = ics_simple_dispatch_pre_save,
 604     .post_load = ics_simple_dispatch_post_load,
 605     .fields = (VMStateField[]) {
 606         /* Sanity check */
 607         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState),
 608
 609         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
 610                                              vmstate_ics_simple_irq,
 611                                              ICSIRQState),
 612         VMSTATE_END_OF_LIST()
 613     },
 614 };
 615
 616 static void ics_simple_initfn(Object *obj)
 617 {
 618     ICSState *ics = ICS_SIMPLE(obj);
 619
 620     ics->offset = XICS_IRQ_BASE;
 621 }
 622
 623 static void ics_simple_realize(DeviceState *dev, Error **errp)
 624 {
 625     ICSState *ics = ICS_SIMPLE(dev);
 626
 627     if (!ics->nr_irqs) {
 628         error_setg(errp, "Number of interrupts needs to be greater 0");
 629         return;
 630     }
 631     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
 632     ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
 633 }
 634
 635 static Property ics_simple_properties[] = {
 636     DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
 637     DEFINE_PROP_END_OF_LIST(),
 638 };
 639
 640 static void ics_simple_class_init(ObjectClass *klass, void *data)
 641 {
 642     DeviceClass *dc = DEVICE_CLASS(klass);
 643     ICSStateClass *isc = ICS_BASE_CLASS(klass);
 644     InterruptStatsProviderClass *ic = INTERRUPT_STATS_PROVIDER_CLASS(klass);
 645
 646     isc->realize = ics_simple_realize;
 647     dc->props = ics_simple_properties;
 648     dc->vmsd = &vmstate_ics_simple;
 649     dc->reset = ics_simple_reset;
 650     isc->post_load = ics_simple_post_load;
 651     isc->reject = ics_simple_reject;
 652     isc->resend = ics_simple_resend;
 653     isc->eoi = ics_simple_eoi;
 654     ic->print_info = ics_simple_pic_print_info;
 655 }
 656
 657 static const TypeInfo ics_simple_info = {
 658     .name = TYPE_ICS_SIMPLE,
 659     .parent = TYPE_ICS_BASE,
 660     .instance_size = sizeof(ICSState),
 661     .class_init = ics_simple_class_init,
 662     .class_size = sizeof(ICSStateClass),
 663     .instance_init = ics_simple_initfn,
 664     .interfaces = (InterfaceInfo[]) {
 665         { TYPE_INTERRUPT_STATS_PROVIDER },
 666         { }
 667     },
 668 };
 669
 670 static void ics_base_realize(DeviceState *dev, Error **errp)
 671 {
 672     ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
 673     ICSState *ics = ICS_BASE(dev);
 674     Object *obj;
 675     Error *err = NULL;
 676
 677     obj = object_property_get_link(OBJECT(dev), "xics", &err);
 678     if (!obj) {
 679         error_setg(errp, "%s: required link 'xics' not found: %s",
 680                    __func__, error_get_pretty(err));
 681         return;
 682     }
 683     ics->xics = XICS_FABRIC(obj);
 684
 685
 686     if (icsc->realize) {
 687         icsc->realize(dev, errp);
 688     }
 689 }
 690
 691 static void ics_base_class_init(ObjectClass *klass, void *data)
 692 {
 693     DeviceClass *dc = DEVICE_CLASS(klass);
 694
 695     dc->realize = ics_base_realize;
 696 }
 697
 698 static const TypeInfo ics_base_info = {
 699     .name = TYPE_ICS_BASE,
 700     .parent = TYPE_DEVICE,
 701     .abstract = true,
 702     .instance_size = sizeof(ICSState),
 703     .class_init = ics_base_class_init,
 704     .class_size = sizeof(ICSStateClass),
 705 };
 706
 707 static const TypeInfo xics_fabric_info = {
 708     .name = TYPE_XICS_FABRIC,
 709     .parent = TYPE_INTERFACE,
 710     .class_size = sizeof(XICSFabricClass),
 711 };
 712
 713 /*
 714  * Exported functions
 715  */
 716 qemu_irq xics_get_qirq(XICSFabric *xi, int irq)
 717 {
 718     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 719     ICSState *ics = xic->ics_get(xi, irq);
 720
 721     if (ics) {
 722         return ics->qirqs[irq - ics->offset];
 723     }
 724
 725     return NULL;
 726 }
 727
 728 ICPState *xics_icp_get(XICSFabric *xi, int server)
 729 {
 730     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 731
 732     return xic->icp_get(xi, server);
 733 }
 734
 735 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
 736 {
 737     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
 738
 739     ics->irqs[srcno].flags |=
 740         lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
 741 }
 742
 743 static void xics_register_types(void)
 744 {
 745     type_register_static(&ics_simple_info);
 746     type_register_static(&ics_base_info);
 747     type_register_static(&icp_info);
 748     type_register_static(&xics_fabric_info);
 749 }
 750
 751 type_init(xics_register_types)