hw/intc/xics.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "qemu-common.h"
  31 #include "cpu.h"
  32 #include "hw/hw.h"
  33 #include "trace.h"
  34 #include "qemu/timer.h"
  35 #include "hw/ppc/xics.h"
  36 #include "qemu/error-report.h"
  37 #include "qapi/visitor.h"
  38 #include "monitor/monitor.h"
  39 #include "hw/intc/intc.h"
  40
  41 int xics_get_cpu_index_by_dt_id(int cpu_dt_id)
  42 {
  43     PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
  44
  45     if (cpu) {
  46         return cpu->parent_obj.cpu_index;
  47     }
  48
  49     return -1;
  50 }
  51
  52 void xics_cpu_destroy(XICSFabric *xi, PowerPCCPU *cpu)
  53 {
  54     CPUState *cs = CPU(cpu);
  55     ICPState *icp = ICP(cpu->intc);
  56
  57     assert(icp);
  58     assert(cs == icp->cs);
  59
  60     icp->output = NULL;
  61     icp->cs = NULL;
  62 }
  63
  64 void xics_cpu_setup(XICSFabric *xi, PowerPCCPU *cpu, ICPState *icp)
  65 {
  66     CPUState *cs = CPU(cpu);
  67     CPUPPCState *env = &cpu->env;
  68     ICPStateClass *icpc;
  69
  70     assert(icp);
  71
  72     cpu->intc = OBJECT(icp);
  73     icp->cs = cs;
  74
  75     icpc = ICP_GET_CLASS(icp);
  76     if (icpc->cpu_setup) {
  77         icpc->cpu_setup(icp, cpu);
  78     }
  79
  80     switch (PPC_INPUT(env)) {
  81     case PPC_FLAGS_INPUT_POWER7:
  82         icp->output = env->irq_inputs[POWER7_INPUT_INT];
  83         break;
  84
  85     case PPC_FLAGS_INPUT_970:
  86         icp->output = env->irq_inputs[PPC970_INPUT_INT];
  87         break;
  88
  89     default:
  90         error_report("XICS interrupt controller does not support this CPU "
  91                      "bus model");
  92         abort();
  93     }
  94 }
  95
  96 void icp_pic_print_info(ICPState *icp, Monitor *mon)
  97 {
  98     int cpu_index = icp->cs ? icp->cs->cpu_index : -1;
  99
 100     if (!icp->output) {
 101         return;
 102     }
 103     monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
 104                    cpu_index, icp->xirr, icp->xirr_owner,
 105                    icp->pending_priority, icp->mfrr);
 106 }
 107
 108 void ics_pic_print_info(ICSState *ics, Monitor *mon)
 109 {
 110     uint32_t i;
 111
 112     monitor_printf(mon, "ICS %4x..%4x %p\n",
 113                    ics->offset, ics->offset + ics->nr_irqs - 1, ics);
 114
 115     if (!ics->irqs) {
 116         return;
 117     }
 118
 119     for (i = 0; i < ics->nr_irqs; i++) {
 120         ICSIRQState *irq = ics->irqs + i;
 121
 122         if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
 123             continue;
 124         }
 125         monitor_printf(mon, "  %4x %s %02x %02x\n",
 126                        ics->offset + i,
 127                        (irq->flags & XICS_FLAGS_IRQ_LSI) ?
 128                        "LSI" : "MSI",
 129                        irq->priority, irq->status);
 130     }
 131 }
 132
 133 /*
 134  * ICP: Presentation layer
 135  */
 136
 137 #define XISR_MASK  0x00ffffff
 138 #define CPPR_MASK  0xff000000
 139
 140 #define XISR(icp)   (((icp)->xirr) & XISR_MASK)
 141 #define CPPR(icp)   (((icp)->xirr) >> 24)
 142
 143 static void ics_reject(ICSState *ics, uint32_t nr)
 144 {
 145     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
 146
 147     if (k->reject) {
 148         k->reject(ics, nr);
 149     }
 150 }
 151
 152 void ics_resend(ICSState *ics)
 153 {
 154     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
 155
 156     if (k->resend) {
 157         k->resend(ics);
 158     }
 159 }
 160
 161 static void ics_eoi(ICSState *ics, int nr)
 162 {
 163     ICSStateClass *k = ICS_BASE_GET_CLASS(ics);
 164
 165     if (k->eoi) {
 166         k->eoi(ics, nr);
 167     }
 168 }
 169
 170 static void icp_check_ipi(ICPState *icp)
 171 {
 172     if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
 173         return;
 174     }
 175
 176     trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
 177
 178     if (XISR(icp) && icp->xirr_owner) {
 179         ics_reject(icp->xirr_owner, XISR(icp));
 180     }
 181
 182     icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
 183     icp->pending_priority = icp->mfrr;
 184     icp->xirr_owner = NULL;
 185     qemu_irq_raise(icp->output);
 186 }
 187
 188 void icp_resend(ICPState *icp)
 189 {
 190     XICSFabric *xi = icp->xics;
 191     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 192
 193     if (icp->mfrr < CPPR(icp)) {
 194         icp_check_ipi(icp);
 195     }
 196
 197     xic->ics_resend(xi);
 198 }
 199
 200 void icp_set_cppr(ICPState *icp, uint8_t cppr)
 201 {
 202     uint8_t old_cppr;
 203     uint32_t old_xisr;
 204
 205     old_cppr = CPPR(icp);
 206     icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
 207
 208     if (cppr < old_cppr) {
 209         if (XISR(icp) && (cppr <= icp->pending_priority)) {
 210             old_xisr = XISR(icp);
 211             icp->xirr &= ~XISR_MASK; /* Clear XISR */
 212             icp->pending_priority = 0xff;
 213             qemu_irq_lower(icp->output);
 214             if (icp->xirr_owner) {
 215                 ics_reject(icp->xirr_owner, old_xisr);
 216                 icp->xirr_owner = NULL;
 217             }
 218         }
 219     } else {
 220         if (!XISR(icp)) {
 221             icp_resend(icp);
 222         }
 223     }
 224 }
 225
 226 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
 227 {
 228     icp->mfrr = mfrr;
 229     if (mfrr < CPPR(icp)) {
 230         icp_check_ipi(icp);
 231     }
 232 }
 233
 234 uint32_t icp_accept(ICPState *icp)
 235 {
 236     uint32_t xirr = icp->xirr;
 237
 238     qemu_irq_lower(icp->output);
 239     icp->xirr = icp->pending_priority << 24;
 240     icp->pending_priority = 0xff;
 241     icp->xirr_owner = NULL;
 242
 243     trace_xics_icp_accept(xirr, icp->xirr);
 244
 245     return xirr;
 246 }
 247
 248 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
 249 {
 250     if (mfrr) {
 251         *mfrr = icp->mfrr;
 252     }
 253     return icp->xirr;
 254 }
 255
 256 void icp_eoi(ICPState *icp, uint32_t xirr)
 257 {
 258     XICSFabric *xi = icp->xics;
 259     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 260     ICSState *ics;
 261     uint32_t irq;
 262
 263     /* Send EOI -> ICS */
 264     icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
 265     trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
 266     irq = xirr & XISR_MASK;
 267
 268     ics = xic->ics_get(xi, irq);
 269     if (ics) {
 270         ics_eoi(ics, irq);
 271     }
 272     if (!XISR(icp)) {
 273         icp_resend(icp);
 274     }
 275 }
 276
 277 static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
 278 {
 279     ICPState *icp = xics_icp_get(ics->xics, server);
 280
 281     trace_xics_icp_irq(server, nr, priority);
 282
 283     if ((priority >= CPPR(icp))
 284         || (XISR(icp) && (icp->pending_priority <= priority))) {
 285         ics_reject(ics, nr);
 286     } else {
 287         if (XISR(icp) && icp->xirr_owner) {
 288             ics_reject(icp->xirr_owner, XISR(icp));
 289             icp->xirr_owner = NULL;
 290         }
 291         icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
 292         icp->xirr_owner = ics;
 293         icp->pending_priority = priority;
 294         trace_xics_icp_raise(icp->xirr, icp->pending_priority);
 295         qemu_irq_raise(icp->output);
 296     }
 297 }
 298
 299 static void icp_dispatch_pre_save(void *opaque)
 300 {
 301     ICPState *icp = opaque;
 302     ICPStateClass *info = ICP_GET_CLASS(icp);
 303
 304     if (info->pre_save) {
 305         info->pre_save(icp);
 306     }
 307 }
 308
 309 static int icp_dispatch_post_load(void *opaque, int version_id)
 310 {
 311     ICPState *icp = opaque;
 312     ICPStateClass *info = ICP_GET_CLASS(icp);
 313
 314     if (info->post_load) {
 315         return info->post_load(icp, version_id);
 316     }
 317
 318     return 0;
 319 }
 320
 321 static const VMStateDescription vmstate_icp_server = {
 322     .name = "icp/server",
 323     .version_id = 1,
 324     .minimum_version_id = 1,
 325     .pre_save = icp_dispatch_pre_save,
 326     .post_load = icp_dispatch_post_load,
 327     .fields = (VMStateField[]) {
 328         /* Sanity check */
 329         VMSTATE_UINT32(xirr, ICPState),
 330         VMSTATE_UINT8(pending_priority, ICPState),
 331         VMSTATE_UINT8(mfrr, ICPState),
 332         VMSTATE_END_OF_LIST()
 333     },
 334 };
 335
 336 static void icp_reset(void *dev)
 337 {
 338     ICPState *icp = ICP(dev);
 339
 340     icp->xirr = 0;
 341     icp->pending_priority = 0xff;
 342     icp->mfrr = 0xff;
 343
 344     /* Make all outputs are deasserted */
 345     qemu_set_irq(icp->output, 0);
 346 }
 347
 348 static void icp_realize(DeviceState *dev, Error **errp)
 349 {
 350     ICPState *icp = ICP(dev);
 351     Object *obj;
 352     Error *err = NULL;
 353
 354     obj = object_property_get_link(OBJECT(dev), "xics", &err);
 355     if (!obj) {
 356         error_setg(errp, "%s: required link 'xics' not found: %s",
 357                    __func__, error_get_pretty(err));
 358         return;
 359     }
 360
 361     icp->xics = XICS_FABRIC(obj);
 362
 363     qemu_register_reset(icp_reset, dev);
 364 }
 365
 366
 367 static void icp_class_init(ObjectClass *klass, void *data)
 368 {
 369     DeviceClass *dc = DEVICE_CLASS(klass);
 370
 371     dc->vmsd = &vmstate_icp_server;
 372     dc->realize = icp_realize;
 373 }
 374
 375 static const TypeInfo icp_info = {
 376     .name = TYPE_ICP,
 377     .parent = TYPE_DEVICE,
 378     .instance_size = sizeof(ICPState),
 379     .class_init = icp_class_init,
 380     .class_size = sizeof(ICPStateClass),
 381 };
 382
 383 /*
 384  * ICS: Source layer
 385  */
 386 static void ics_simple_resend_msi(ICSState *ics, int srcno)
 387 {
 388     ICSIRQState *irq = ics->irqs + srcno;
 389
 390     /* FIXME: filter by server#? */
 391     if (irq->status & XICS_STATUS_REJECTED) {
 392         irq->status &= ~XICS_STATUS_REJECTED;
 393         if (irq->priority != 0xff) {
 394             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 395         }
 396     }
 397 }
 398
 399 static void ics_simple_resend_lsi(ICSState *ics, int srcno)
 400 {
 401     ICSIRQState *irq = ics->irqs + srcno;
 402
 403     if ((irq->priority != 0xff)
 404         && (irq->status & XICS_STATUS_ASSERTED)
 405         && !(irq->status & XICS_STATUS_SENT)) {
 406         irq->status |= XICS_STATUS_SENT;
 407         icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 408     }
 409 }
 410
 411 static void ics_simple_set_irq_msi(ICSState *ics, int srcno, int val)
 412 {
 413     ICSIRQState *irq = ics->irqs + srcno;
 414
 415     trace_xics_ics_simple_set_irq_msi(srcno, srcno + ics->offset);
 416
 417     if (val) {
 418         if (irq->priority == 0xff) {
 419             irq->status |= XICS_STATUS_MASKED_PENDING;
 420             trace_xics_masked_pending();
 421         } else  {
 422             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 423         }
 424     }
 425 }
 426
 427 static void ics_simple_set_irq_lsi(ICSState *ics, int srcno, int val)
 428 {
 429     ICSIRQState *irq = ics->irqs + srcno;
 430
 431     trace_xics_ics_simple_set_irq_lsi(srcno, srcno + ics->offset);
 432     if (val) {
 433         irq->status |= XICS_STATUS_ASSERTED;
 434     } else {
 435         irq->status &= ~XICS_STATUS_ASSERTED;
 436     }
 437     ics_simple_resend_lsi(ics, srcno);
 438 }
 439
 440 static void ics_simple_set_irq(void *opaque, int srcno, int val)
 441 {
 442     ICSState *ics = (ICSState *)opaque;
 443
 444     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 445         ics_simple_set_irq_lsi(ics, srcno, val);
 446     } else {
 447         ics_simple_set_irq_msi(ics, srcno, val);
 448     }
 449 }
 450
 451 static void ics_simple_write_xive_msi(ICSState *ics, int srcno)
 452 {
 453     ICSIRQState *irq = ics->irqs + srcno;
 454
 455     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
 456         || (irq->priority == 0xff)) {
 457         return;
 458     }
 459
 460     irq->status &= ~XICS_STATUS_MASKED_PENDING;
 461     icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 462 }
 463
 464 static void ics_simple_write_xive_lsi(ICSState *ics, int srcno)
 465 {
 466     ics_simple_resend_lsi(ics, srcno);
 467 }
 468
 469 void ics_simple_write_xive(ICSState *ics, int srcno, int server,
 470                            uint8_t priority, uint8_t saved_priority)
 471 {
 472     ICSIRQState *irq = ics->irqs + srcno;
 473
 474     irq->server = server;
 475     irq->priority = priority;
 476     irq->saved_priority = saved_priority;
 477
 478     trace_xics_ics_simple_write_xive(ics->offset + srcno, srcno, server,
 479                                      priority);
 480
 481     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 482         ics_simple_write_xive_lsi(ics, srcno);
 483     } else {
 484         ics_simple_write_xive_msi(ics, srcno);
 485     }
 486 }
 487
 488 static void ics_simple_reject(ICSState *ics, uint32_t nr)
 489 {
 490     ICSIRQState *irq = ics->irqs + nr - ics->offset;
 491
 492     trace_xics_ics_simple_reject(nr, nr - ics->offset);
 493     if (irq->flags & XICS_FLAGS_IRQ_MSI) {
 494         irq->status |= XICS_STATUS_REJECTED;
 495     } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
 496         irq->status &= ~XICS_STATUS_SENT;
 497     }
 498 }
 499
 500 static void ics_simple_resend(ICSState *ics)
 501 {
 502     int i;
 503
 504     for (i = 0; i < ics->nr_irqs; i++) {
 505         /* FIXME: filter by server#? */
 506         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
 507             ics_simple_resend_lsi(ics, i);
 508         } else {
 509             ics_simple_resend_msi(ics, i);
 510         }
 511     }
 512 }
 513
 514 static void ics_simple_eoi(ICSState *ics, uint32_t nr)
 515 {
 516     int srcno = nr - ics->offset;
 517     ICSIRQState *irq = ics->irqs + srcno;
 518
 519     trace_xics_ics_simple_eoi(nr);
 520
 521     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 522         irq->status &= ~XICS_STATUS_SENT;
 523     }
 524 }
 525
 526 static void ics_simple_reset(void *dev)
 527 {
 528     ICSState *ics = ICS_SIMPLE(dev);
 529     int i;
 530     uint8_t flags[ics->nr_irqs];
 531
 532     for (i = 0; i < ics->nr_irqs; i++) {
 533         flags[i] = ics->irqs[i].flags;
 534     }
 535
 536     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
 537
 538     for (i = 0; i < ics->nr_irqs; i++) {
 539         ics->irqs[i].priority = 0xff;
 540         ics->irqs[i].saved_priority = 0xff;
 541         ics->irqs[i].flags = flags[i];
 542     }
 543 }
 544
 545 static void ics_simple_dispatch_pre_save(void *opaque)
 546 {
 547     ICSState *ics = opaque;
 548     ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
 549
 550     if (info->pre_save) {
 551         info->pre_save(ics);
 552     }
 553 }
 554
 555 static int ics_simple_dispatch_post_load(void *opaque, int version_id)
 556 {
 557     ICSState *ics = opaque;
 558     ICSStateClass *info = ICS_BASE_GET_CLASS(ics);
 559
 560     if (info->post_load) {
 561         return info->post_load(ics, version_id);
 562     }
 563
 564     return 0;
 565 }
 566
 567 static const VMStateDescription vmstate_ics_simple_irq = {
 568     .name = "ics/irq",
 569     .version_id = 2,
 570     .minimum_version_id = 1,
 571     .fields = (VMStateField[]) {
 572         VMSTATE_UINT32(server, ICSIRQState),
 573         VMSTATE_UINT8(priority, ICSIRQState),
 574         VMSTATE_UINT8(saved_priority, ICSIRQState),
 575         VMSTATE_UINT8(status, ICSIRQState),
 576         VMSTATE_UINT8(flags, ICSIRQState),
 577         VMSTATE_END_OF_LIST()
 578     },
 579 };
 580
 581 static const VMStateDescription vmstate_ics_simple = {
 582     .name = "ics",
 583     .version_id = 1,
 584     .minimum_version_id = 1,
 585     .pre_save = ics_simple_dispatch_pre_save,
 586     .post_load = ics_simple_dispatch_post_load,
 587     .fields = (VMStateField[]) {
 588         /* Sanity check */
 589         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState),
 590
 591         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
 592                                              vmstate_ics_simple_irq,
 593                                              ICSIRQState),
 594         VMSTATE_END_OF_LIST()
 595     },
 596 };
 597
 598 static void ics_simple_initfn(Object *obj)
 599 {
 600     ICSState *ics = ICS_SIMPLE(obj);
 601
 602     ics->offset = XICS_IRQ_BASE;
 603 }
 604
 605 static void ics_simple_realize(DeviceState *dev, Error **errp)
 606 {
 607     ICSState *ics = ICS_SIMPLE(dev);
 608
 609     if (!ics->nr_irqs) {
 610         error_setg(errp, "Number of interrupts needs to be greater 0");
 611         return;
 612     }
 613     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
 614     ics->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs);
 615
 616     qemu_register_reset(ics_simple_reset, dev);
 617 }
 618
 619 static Property ics_simple_properties[] = {
 620     DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
 621     DEFINE_PROP_END_OF_LIST(),
 622 };
 623
 624 static void ics_simple_class_init(ObjectClass *klass, void *data)
 625 {
 626     DeviceClass *dc = DEVICE_CLASS(klass);
 627     ICSStateClass *isc = ICS_BASE_CLASS(klass);
 628
 629     isc->realize = ics_simple_realize;
 630     dc->props = ics_simple_properties;
 631     dc->vmsd = &vmstate_ics_simple;
 632     isc->reject = ics_simple_reject;
 633     isc->resend = ics_simple_resend;
 634     isc->eoi = ics_simple_eoi;
 635 }
 636
 637 static const TypeInfo ics_simple_info = {
 638     .name = TYPE_ICS_SIMPLE,
 639     .parent = TYPE_ICS_BASE,
 640     .instance_size = sizeof(ICSState),
 641     .class_init = ics_simple_class_init,
 642     .class_size = sizeof(ICSStateClass),
 643     .instance_init = ics_simple_initfn,
 644 };
 645
 646 static void ics_base_realize(DeviceState *dev, Error **errp)
 647 {
 648     ICSStateClass *icsc = ICS_BASE_GET_CLASS(dev);
 649     ICSState *ics = ICS_BASE(dev);
 650     Object *obj;
 651     Error *err = NULL;
 652
 653     obj = object_property_get_link(OBJECT(dev), "xics", &err);
 654     if (!obj) {
 655         error_setg(errp, "%s: required link 'xics' not found: %s",
 656                    __func__, error_get_pretty(err));
 657         return;
 658     }
 659     ics->xics = XICS_FABRIC(obj);
 660
 661
 662     if (icsc->realize) {
 663         icsc->realize(dev, errp);
 664     }
 665 }
 666
 667 static void ics_base_class_init(ObjectClass *klass, void *data)
 668 {
 669     DeviceClass *dc = DEVICE_CLASS(klass);
 670
 671     dc->realize = ics_base_realize;
 672 }
 673
 674 static const TypeInfo ics_base_info = {
 675     .name = TYPE_ICS_BASE,
 676     .parent = TYPE_DEVICE,
 677     .abstract = true,
 678     .instance_size = sizeof(ICSState),
 679     .class_init = ics_base_class_init,
 680     .class_size = sizeof(ICSStateClass),
 681 };
 682
 683 static const TypeInfo xics_fabric_info = {
 684     .name = TYPE_XICS_FABRIC,
 685     .parent = TYPE_INTERFACE,
 686     .class_size = sizeof(XICSFabricClass),
 687 };
 688
 689 /*
 690  * Exported functions
 691  */
 692 qemu_irq xics_get_qirq(XICSFabric *xi, int irq)
 693 {
 694     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 695     ICSState *ics = xic->ics_get(xi, irq);
 696
 697     if (ics) {
 698         return ics->qirqs[irq - ics->offset];
 699     }
 700
 701     return NULL;
 702 }
 703
 704 ICPState *xics_icp_get(XICSFabric *xi, int server)
 705 {
 706     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 707
 708     return xic->icp_get(xi, server);
 709 }
 710
 711 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
 712 {
 713     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
 714
 715     ics->irqs[srcno].flags |=
 716         lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
 717 }
 718
 719 static void xics_register_types(void)
 720 {
 721     type_register_static(&ics_simple_info);
 722     type_register_static(&ics_base_info);
 723     type_register_static(&icp_info);
 724     type_register_static(&xics_fabric_info);
 725 }
 726
 727 type_init(xics_register_types)