2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
31 #include "qemu/timer.h"
32 #include "hw/ppc/xics.h"
33 #include "hw/qdev-properties.h"
34 #include "qemu/error-report.h"
35 #include "qemu/module.h"
36 #include "qapi/visitor.h"
37 #include "migration/vmstate.h"
38 #include "monitor/monitor.h"
39 #include "hw/intc/intc.h"
41 #include "sysemu/kvm.h"
42 #include "sysemu/reset.h"
44 void icp_pic_print_info(ICPState
*icp
, Monitor
*mon
)
48 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs
49 * are hot plugged or unplugged.
55 cpu_index
= icp
->cs
? icp
->cs
->cpu_index
: -1;
61 if (kvm_irqchip_in_kernel()) {
62 icp_synchronize_state(icp
);
65 monitor_printf(mon
, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
66 cpu_index
, icp
->xirr
, icp
->xirr_owner
,
67 icp
->pending_priority
, icp
->mfrr
);
70 void ics_pic_print_info(ICSState
*ics
, Monitor
*mon
)
74 monitor_printf(mon
, "ICS %4x..%4x %p\n",
75 ics
->offset
, ics
->offset
+ ics
->nr_irqs
- 1, ics
);
81 if (kvm_irqchip_in_kernel()) {
82 ics_synchronize_state(ics
);
85 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
86 ICSIRQState
*irq
= ics
->irqs
+ i
;
88 if (!(irq
->flags
& XICS_FLAGS_IRQ_MASK
)) {
91 monitor_printf(mon
, " %4x %s %02x %02x\n",
93 (irq
->flags
& XICS_FLAGS_IRQ_LSI
) ?
95 irq
->priority
, irq
->status
);
100 * ICP: Presentation layer
103 #define XISR_MASK 0x00ffffff
104 #define CPPR_MASK 0xff000000
106 #define XISR(icp) (((icp)->xirr) & XISR_MASK)
107 #define CPPR(icp) (((icp)->xirr) >> 24)
109 static void ics_reject(ICSState
*ics
, uint32_t nr
);
110 static void ics_eoi(ICSState
*ics
, uint32_t nr
);
112 static void icp_check_ipi(ICPState
*icp
)
114 if (XISR(icp
) && (icp
->pending_priority
<= icp
->mfrr
)) {
118 trace_xics_icp_check_ipi(icp
->cs
->cpu_index
, icp
->mfrr
);
120 if (XISR(icp
) && icp
->xirr_owner
) {
121 ics_reject(icp
->xirr_owner
, XISR(icp
));
124 icp
->xirr
= (icp
->xirr
& ~XISR_MASK
) | XICS_IPI
;
125 icp
->pending_priority
= icp
->mfrr
;
126 icp
->xirr_owner
= NULL
;
127 qemu_irq_raise(icp
->output
);
130 void icp_resend(ICPState
*icp
)
132 XICSFabric
*xi
= icp
->xics
;
133 XICSFabricClass
*xic
= XICS_FABRIC_GET_CLASS(xi
);
135 if (icp
->mfrr
< CPPR(icp
)) {
142 void icp_set_cppr(ICPState
*icp
, uint8_t cppr
)
147 old_cppr
= CPPR(icp
);
148 icp
->xirr
= (icp
->xirr
& ~CPPR_MASK
) | (cppr
<< 24);
150 if (cppr
< old_cppr
) {
151 if (XISR(icp
) && (cppr
<= icp
->pending_priority
)) {
152 old_xisr
= XISR(icp
);
153 icp
->xirr
&= ~XISR_MASK
; /* Clear XISR */
154 icp
->pending_priority
= 0xff;
155 qemu_irq_lower(icp
->output
);
156 if (icp
->xirr_owner
) {
157 ics_reject(icp
->xirr_owner
, old_xisr
);
158 icp
->xirr_owner
= NULL
;
168 void icp_set_mfrr(ICPState
*icp
, uint8_t mfrr
)
171 if (mfrr
< CPPR(icp
)) {
176 uint32_t icp_accept(ICPState
*icp
)
178 uint32_t xirr
= icp
->xirr
;
180 qemu_irq_lower(icp
->output
);
181 icp
->xirr
= icp
->pending_priority
<< 24;
182 icp
->pending_priority
= 0xff;
183 icp
->xirr_owner
= NULL
;
185 trace_xics_icp_accept(xirr
, icp
->xirr
);
190 uint32_t icp_ipoll(ICPState
*icp
, uint32_t *mfrr
)
198 void icp_eoi(ICPState
*icp
, uint32_t xirr
)
200 XICSFabric
*xi
= icp
->xics
;
201 XICSFabricClass
*xic
= XICS_FABRIC_GET_CLASS(xi
);
205 /* Send EOI -> ICS */
206 icp
->xirr
= (icp
->xirr
& ~CPPR_MASK
) | (xirr
& CPPR_MASK
);
207 trace_xics_icp_eoi(icp
->cs
->cpu_index
, xirr
, icp
->xirr
);
208 irq
= xirr
& XISR_MASK
;
210 ics
= xic
->ics_get(xi
, irq
);
219 void icp_irq(ICSState
*ics
, int server
, int nr
, uint8_t priority
)
221 ICPState
*icp
= xics_icp_get(ics
->xics
, server
);
223 trace_xics_icp_irq(server
, nr
, priority
);
225 if ((priority
>= CPPR(icp
))
226 || (XISR(icp
) && (icp
->pending_priority
<= priority
))) {
229 if (XISR(icp
) && icp
->xirr_owner
) {
230 ics_reject(icp
->xirr_owner
, XISR(icp
));
231 icp
->xirr_owner
= NULL
;
233 icp
->xirr
= (icp
->xirr
& ~XISR_MASK
) | (nr
& XISR_MASK
);
234 icp
->xirr_owner
= ics
;
235 icp
->pending_priority
= priority
;
236 trace_xics_icp_raise(icp
->xirr
, icp
->pending_priority
);
237 qemu_irq_raise(icp
->output
);
241 static int icp_pre_save(void *opaque
)
243 ICPState
*icp
= opaque
;
245 if (kvm_irqchip_in_kernel()) {
246 icp_get_kvm_state(icp
);
252 static int icp_post_load(void *opaque
, int version_id
)
254 ICPState
*icp
= opaque
;
256 if (kvm_irqchip_in_kernel()) {
257 Error
*local_err
= NULL
;
260 ret
= icp_set_kvm_state(icp
, &local_err
);
262 error_report_err(local_err
);
270 static const VMStateDescription vmstate_icp_server
= {
271 .name
= "icp/server",
273 .minimum_version_id
= 1,
274 .pre_save
= icp_pre_save
,
275 .post_load
= icp_post_load
,
276 .fields
= (const VMStateField
[]) {
278 VMSTATE_UINT32(xirr
, ICPState
),
279 VMSTATE_UINT8(pending_priority
, ICPState
),
280 VMSTATE_UINT8(mfrr
, ICPState
),
281 VMSTATE_END_OF_LIST()
285 void icp_reset(ICPState
*icp
)
288 icp
->pending_priority
= 0xff;
291 if (kvm_irqchip_in_kernel()) {
292 Error
*local_err
= NULL
;
294 icp_set_kvm_state(icp
, &local_err
);
296 error_report_err(local_err
);
301 static void icp_realize(DeviceState
*dev
, Error
**errp
)
303 ICPState
*icp
= ICP(dev
);
311 cpu
= POWERPC_CPU(icp
->cs
);
313 switch (PPC_INPUT(env
)) {
314 case PPC_FLAGS_INPUT_POWER7
:
315 icp
->output
= qdev_get_gpio_in(DEVICE(cpu
), POWER7_INPUT_INT
);
317 case PPC_FLAGS_INPUT_POWER9
: /* For SPAPR xics emulation */
318 icp
->output
= qdev_get_gpio_in(DEVICE(cpu
), POWER9_INPUT_INT
);
321 case PPC_FLAGS_INPUT_970
:
322 icp
->output
= qdev_get_gpio_in(DEVICE(cpu
), PPC970_INPUT_INT
);
326 error_setg(errp
, "XICS interrupt controller does not support this CPU bus model");
330 /* Connect the presenter to the VCPU (required for CPU hotplug) */
331 if (kvm_irqchip_in_kernel()) {
332 icp_kvm_realize(dev
, &err
);
334 error_propagate(errp
, err
);
339 * The way that pre_2_10_icp is handling is really, really hacky.
340 * We used to have here this call:
342 * vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
345 * pre_2_10_vmstate_register_dummy_icp()
346 * this vmstate_register()
347 * pre_2_10_vmstate_unregister_dummy_icp()
349 * So for a short amount of time we had to vmstate entries with
350 * the same name. This fixes it.
352 vmstate_replace_hack_for_ppc(NULL
, icp
->cs
->cpu_index
,
353 &vmstate_icp_server
, icp
);
356 static void icp_unrealize(DeviceState
*dev
)
358 ICPState
*icp
= ICP(dev
);
360 vmstate_unregister(NULL
, &vmstate_icp_server
, icp
);
363 static Property icp_properties
[] = {
364 DEFINE_PROP_LINK(ICP_PROP_XICS
, ICPState
, xics
, TYPE_XICS_FABRIC
,
366 DEFINE_PROP_LINK(ICP_PROP_CPU
, ICPState
, cs
, TYPE_CPU
, CPUState
*),
367 DEFINE_PROP_END_OF_LIST(),
370 static void icp_class_init(ObjectClass
*klass
, void *data
)
372 DeviceClass
*dc
= DEVICE_CLASS(klass
);
374 dc
->realize
= icp_realize
;
375 dc
->unrealize
= icp_unrealize
;
376 device_class_set_props(dc
, icp_properties
);
378 * Reason: part of XICS interrupt controller, needs to be wired up
381 dc
->user_creatable
= false;
384 static const TypeInfo icp_info
= {
386 .parent
= TYPE_DEVICE
,
387 .instance_size
= sizeof(ICPState
),
388 .class_init
= icp_class_init
,
389 .class_size
= sizeof(ICPStateClass
),
392 Object
*icp_create(Object
*cpu
, const char *type
, XICSFabric
*xi
, Error
**errp
)
396 obj
= object_new(type
);
397 object_property_add_child(cpu
, type
, obj
);
399 object_property_set_link(obj
, ICP_PROP_XICS
, OBJECT(xi
), &error_abort
);
400 object_property_set_link(obj
, ICP_PROP_CPU
, cpu
, &error_abort
);
401 if (!qdev_realize(DEVICE(obj
), NULL
, errp
)) {
402 object_unparent(obj
);
409 void icp_destroy(ICPState
*icp
)
411 Object
*obj
= OBJECT(icp
);
413 object_unparent(obj
);
419 static void ics_resend_msi(ICSState
*ics
, int srcno
)
421 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
423 /* FIXME: filter by server#? */
424 if (irq
->status
& XICS_STATUS_REJECTED
) {
425 irq
->status
&= ~XICS_STATUS_REJECTED
;
426 if (irq
->priority
!= 0xff) {
427 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
432 static void ics_resend_lsi(ICSState
*ics
, int srcno
)
434 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
436 if ((irq
->priority
!= 0xff)
437 && (irq
->status
& XICS_STATUS_ASSERTED
)
438 && !(irq
->status
& XICS_STATUS_SENT
)) {
439 irq
->status
|= XICS_STATUS_SENT
;
440 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
444 static void ics_set_irq_msi(ICSState
*ics
, int srcno
, int val
)
446 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
448 trace_xics_ics_set_irq_msi(srcno
, srcno
+ ics
->offset
);
451 if (irq
->priority
== 0xff) {
452 irq
->status
|= XICS_STATUS_MASKED_PENDING
;
453 trace_xics_masked_pending();
455 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
460 static void ics_set_irq_lsi(ICSState
*ics
, int srcno
, int val
)
462 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
464 trace_xics_ics_set_irq_lsi(srcno
, srcno
+ ics
->offset
);
466 irq
->status
|= XICS_STATUS_ASSERTED
;
468 irq
->status
&= ~XICS_STATUS_ASSERTED
;
470 ics_resend_lsi(ics
, srcno
);
473 void ics_set_irq(void *opaque
, int srcno
, int val
)
475 ICSState
*ics
= (ICSState
*)opaque
;
477 if (kvm_irqchip_in_kernel()) {
478 ics_kvm_set_irq(ics
, srcno
, val
);
482 if (ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_LSI
) {
483 ics_set_irq_lsi(ics
, srcno
, val
);
485 ics_set_irq_msi(ics
, srcno
, val
);
489 static void ics_write_xive_msi(ICSState
*ics
, int srcno
)
491 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
493 if (!(irq
->status
& XICS_STATUS_MASKED_PENDING
)
494 || (irq
->priority
== 0xff)) {
498 irq
->status
&= ~XICS_STATUS_MASKED_PENDING
;
499 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
502 static void ics_write_xive_lsi(ICSState
*ics
, int srcno
)
504 ics_resend_lsi(ics
, srcno
);
507 void ics_write_xive(ICSState
*ics
, int srcno
, int server
,
508 uint8_t priority
, uint8_t saved_priority
)
510 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
512 irq
->server
= server
;
513 irq
->priority
= priority
;
514 irq
->saved_priority
= saved_priority
;
516 trace_xics_ics_write_xive(ics
->offset
+ srcno
, srcno
, server
, priority
);
518 if (ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_LSI
) {
519 ics_write_xive_lsi(ics
, srcno
);
521 ics_write_xive_msi(ics
, srcno
);
525 static void ics_reject(ICSState
*ics
, uint32_t nr
)
527 ICSStateClass
*isc
= ICS_GET_CLASS(ics
);
528 ICSIRQState
*irq
= ics
->irqs
+ nr
- ics
->offset
;
531 isc
->reject(ics
, nr
);
535 trace_xics_ics_reject(nr
, nr
- ics
->offset
);
536 if (irq
->flags
& XICS_FLAGS_IRQ_MSI
) {
537 irq
->status
|= XICS_STATUS_REJECTED
;
538 } else if (irq
->flags
& XICS_FLAGS_IRQ_LSI
) {
539 irq
->status
&= ~XICS_STATUS_SENT
;
543 void ics_resend(ICSState
*ics
)
545 ICSStateClass
*isc
= ICS_GET_CLASS(ics
);
553 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
554 /* FIXME: filter by server#? */
555 if (ics
->irqs
[i
].flags
& XICS_FLAGS_IRQ_LSI
) {
556 ics_resend_lsi(ics
, i
);
558 ics_resend_msi(ics
, i
);
563 static void ics_eoi(ICSState
*ics
, uint32_t nr
)
565 int srcno
= nr
- ics
->offset
;
566 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
568 trace_xics_ics_eoi(nr
);
570 if (ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_LSI
) {
571 irq
->status
&= ~XICS_STATUS_SENT
;
575 static void ics_reset_irq(ICSIRQState
*irq
)
577 irq
->priority
= 0xff;
578 irq
->saved_priority
= 0xff;
581 static void ics_reset_hold(Object
*obj
)
583 ICSState
*ics
= ICS(obj
);
584 g_autofree
uint8_t *flags
= g_malloc(ics
->nr_irqs
);
587 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
588 flags
[i
] = ics
->irqs
[i
].flags
;
591 memset(ics
->irqs
, 0, sizeof(ICSIRQState
) * ics
->nr_irqs
);
593 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
594 ics_reset_irq(ics
->irqs
+ i
);
595 ics
->irqs
[i
].flags
= flags
[i
];
598 if (kvm_irqchip_in_kernel()) {
599 Error
*local_err
= NULL
;
601 ics_set_kvm_state(ics
, &local_err
);
603 error_report_err(local_err
);
608 static void ics_reset_handler(void *dev
)
610 device_cold_reset(dev
);
613 static void ics_realize(DeviceState
*dev
, Error
**errp
)
615 ICSState
*ics
= ICS(dev
);
620 error_setg(errp
, "Number of interrupts needs to be greater 0");
623 ics
->irqs
= g_new0(ICSIRQState
, ics
->nr_irqs
);
625 qemu_register_reset(ics_reset_handler
, ics
);
628 static void ics_instance_init(Object
*obj
)
630 ICSState
*ics
= ICS(obj
);
632 ics
->offset
= XICS_IRQ_BASE
;
635 static int ics_pre_save(void *opaque
)
637 ICSState
*ics
= opaque
;
639 if (kvm_irqchip_in_kernel()) {
640 ics_get_kvm_state(ics
);
646 static int ics_post_load(void *opaque
, int version_id
)
648 ICSState
*ics
= opaque
;
650 if (kvm_irqchip_in_kernel()) {
651 Error
*local_err
= NULL
;
654 ret
= ics_set_kvm_state(ics
, &local_err
);
656 error_report_err(local_err
);
664 static const VMStateDescription vmstate_ics_irq
= {
667 .minimum_version_id
= 1,
668 .fields
= (const VMStateField
[]) {
669 VMSTATE_UINT32(server
, ICSIRQState
),
670 VMSTATE_UINT8(priority
, ICSIRQState
),
671 VMSTATE_UINT8(saved_priority
, ICSIRQState
),
672 VMSTATE_UINT8(status
, ICSIRQState
),
673 VMSTATE_UINT8(flags
, ICSIRQState
),
674 VMSTATE_END_OF_LIST()
678 static const VMStateDescription vmstate_ics
= {
681 .minimum_version_id
= 1,
682 .pre_save
= ics_pre_save
,
683 .post_load
= ics_post_load
,
684 .fields
= (const VMStateField
[]) {
686 VMSTATE_UINT32_EQUAL(nr_irqs
, ICSState
, NULL
),
688 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs
, ICSState
, nr_irqs
,
691 VMSTATE_END_OF_LIST()
695 static Property ics_properties
[] = {
696 DEFINE_PROP_UINT32("nr-irqs", ICSState
, nr_irqs
, 0),
697 DEFINE_PROP_LINK(ICS_PROP_XICS
, ICSState
, xics
, TYPE_XICS_FABRIC
,
699 DEFINE_PROP_END_OF_LIST(),
702 static void ics_class_init(ObjectClass
*klass
, void *data
)
704 DeviceClass
*dc
= DEVICE_CLASS(klass
);
705 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
707 dc
->realize
= ics_realize
;
708 device_class_set_props(dc
, ics_properties
);
709 dc
->vmsd
= &vmstate_ics
;
711 * Reason: part of XICS interrupt controller, needs to be wired up,
712 * e.g. by spapr_irq_init().
714 dc
->user_creatable
= false;
715 rc
->phases
.hold
= ics_reset_hold
;
718 static const TypeInfo ics_info
= {
720 .parent
= TYPE_DEVICE
,
721 .instance_size
= sizeof(ICSState
),
722 .instance_init
= ics_instance_init
,
723 .class_init
= ics_class_init
,
724 .class_size
= sizeof(ICSStateClass
),
727 static const TypeInfo xics_fabric_info
= {
728 .name
= TYPE_XICS_FABRIC
,
729 .parent
= TYPE_INTERFACE
,
730 .class_size
= sizeof(XICSFabricClass
),
736 ICPState
*xics_icp_get(XICSFabric
*xi
, int server
)
738 XICSFabricClass
*xic
= XICS_FABRIC_GET_CLASS(xi
);
740 return xic
->icp_get(xi
, server
);
743 void ics_set_irq_type(ICSState
*ics
, int srcno
, bool lsi
)
745 assert(!(ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_MASK
));
747 ics
->irqs
[srcno
].flags
|=
748 lsi
? XICS_FLAGS_IRQ_LSI
: XICS_FLAGS_IRQ_MSI
;
750 if (kvm_irqchip_in_kernel()) {
751 Error
*local_err
= NULL
;
753 ics_reset_irq(ics
->irqs
+ srcno
);
754 ics_set_kvm_state_one(ics
, srcno
, &local_err
);
756 error_report_err(local_err
);
761 static void xics_register_types(void)
763 type_register_static(&ics_info
);
764 type_register_static(&icp_info
);
765 type_register_static(&xics_fabric_info
);
768 type_init(xics_register_types
)