hw/intc/xics.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "qemu/osdep.h"
  29 #include "qapi/error.h"
  30 #include "cpu.h"
  31 #include "trace.h"
  32 #include "qemu/timer.h"
  33 #include "hw/ppc/xics.h"
  34 #include "hw/qdev-properties.h"
  35 #include "qemu/error-report.h"
  36 #include "qemu/module.h"
  37 #include "qapi/visitor.h"
  38 #include "migration/vmstate.h"
  39 #include "monitor/monitor.h"
  40 #include "hw/intc/intc.h"
  41 #include "hw/irq.h"
  42 #include "sysemu/kvm.h"
  43 #include "sysemu/reset.h"
  44
  45 void icp_pic_print_info(ICPState *icp, Monitor *mon)
  46 {
  47     int cpu_index;
  48
  49     /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs
  50      * are hot plugged or unplugged.
  51      */
  52     if (!icp) {
  53         return;
  54     }
  55
  56     cpu_index = icp->cs ? icp->cs->cpu_index : -1;
  57
  58     if (!icp->output) {
  59         return;
  60     }
  61
  62     if (kvm_irqchip_in_kernel()) {
  63         icp_synchronize_state(icp);
  64     }
  65
  66     monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
  67                    cpu_index, icp->xirr, icp->xirr_owner,
  68                    icp->pending_priority, icp->mfrr);
  69 }
  70
  71 void ics_pic_print_info(ICSState *ics, Monitor *mon)
  72 {
  73     uint32_t i;
  74
  75     monitor_printf(mon, "ICS %4x..%4x %p\n",
  76                    ics->offset, ics->offset + ics->nr_irqs - 1, ics);
  77
  78     if (!ics->irqs) {
  79         return;
  80     }
  81
  82     if (kvm_irqchip_in_kernel()) {
  83         ics_synchronize_state(ics);
  84     }
  85
  86     for (i = 0; i < ics->nr_irqs; i++) {
  87         ICSIRQState *irq = ics->irqs + i;
  88
  89         if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
  90             continue;
  91         }
  92         monitor_printf(mon, "  %4x %s %02x %02x\n",
  93                        ics->offset + i,
  94                        (irq->flags & XICS_FLAGS_IRQ_LSI) ?
  95                        "LSI" : "MSI",
  96                        irq->priority, irq->status);
  97     }
  98 }
  99
 100 /*
 101  * ICP: Presentation layer
 102  */
 103
 104 #define XISR_MASK  0x00ffffff
 105 #define CPPR_MASK  0xff000000
 106
 107 #define XISR(icp)   (((icp)->xirr) & XISR_MASK)
 108 #define CPPR(icp)   (((icp)->xirr) >> 24)
 109
 110 static void ics_reject(ICSState *ics, uint32_t nr);
 111 static void ics_eoi(ICSState *ics, uint32_t nr);
 112
 113 static void icp_check_ipi(ICPState *icp)
 114 {
 115     if (XISR(icp) && (icp->pending_priority <= icp->mfrr)) {
 116         return;
 117     }
 118
 119     trace_xics_icp_check_ipi(icp->cs->cpu_index, icp->mfrr);
 120
 121     if (XISR(icp) && icp->xirr_owner) {
 122         ics_reject(icp->xirr_owner, XISR(icp));
 123     }
 124
 125     icp->xirr = (icp->xirr & ~XISR_MASK) | XICS_IPI;
 126     icp->pending_priority = icp->mfrr;
 127     icp->xirr_owner = NULL;
 128     qemu_irq_raise(icp->output);
 129 }
 130
 131 void icp_resend(ICPState *icp)
 132 {
 133     XICSFabric *xi = icp->xics;
 134     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 135
 136     if (icp->mfrr < CPPR(icp)) {
 137         icp_check_ipi(icp);
 138     }
 139
 140     xic->ics_resend(xi);
 141 }
 142
 143 void icp_set_cppr(ICPState *icp, uint8_t cppr)
 144 {
 145     uint8_t old_cppr;
 146     uint32_t old_xisr;
 147
 148     old_cppr = CPPR(icp);
 149     icp->xirr = (icp->xirr & ~CPPR_MASK) | (cppr << 24);
 150
 151     if (cppr < old_cppr) {
 152         if (XISR(icp) && (cppr <= icp->pending_priority)) {
 153             old_xisr = XISR(icp);
 154             icp->xirr &= ~XISR_MASK; /* Clear XISR */
 155             icp->pending_priority = 0xff;
 156             qemu_irq_lower(icp->output);
 157             if (icp->xirr_owner) {
 158                 ics_reject(icp->xirr_owner, old_xisr);
 159                 icp->xirr_owner = NULL;
 160             }
 161         }
 162     } else {
 163         if (!XISR(icp)) {
 164             icp_resend(icp);
 165         }
 166     }
 167 }
 168
 169 void icp_set_mfrr(ICPState *icp, uint8_t mfrr)
 170 {
 171     icp->mfrr = mfrr;
 172     if (mfrr < CPPR(icp)) {
 173         icp_check_ipi(icp);
 174     }
 175 }
 176
 177 uint32_t icp_accept(ICPState *icp)
 178 {
 179     uint32_t xirr = icp->xirr;
 180
 181     qemu_irq_lower(icp->output);
 182     icp->xirr = icp->pending_priority << 24;
 183     icp->pending_priority = 0xff;
 184     icp->xirr_owner = NULL;
 185
 186     trace_xics_icp_accept(xirr, icp->xirr);
 187
 188     return xirr;
 189 }
 190
 191 uint32_t icp_ipoll(ICPState *icp, uint32_t *mfrr)
 192 {
 193     if (mfrr) {
 194         *mfrr = icp->mfrr;
 195     }
 196     return icp->xirr;
 197 }
 198
 199 void icp_eoi(ICPState *icp, uint32_t xirr)
 200 {
 201     XICSFabric *xi = icp->xics;
 202     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 203     ICSState *ics;
 204     uint32_t irq;
 205
 206     /* Send EOI -> ICS */
 207     icp->xirr = (icp->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
 208     trace_xics_icp_eoi(icp->cs->cpu_index, xirr, icp->xirr);
 209     irq = xirr & XISR_MASK;
 210
 211     ics = xic->ics_get(xi, irq);
 212     if (ics) {
 213         ics_eoi(ics, irq);
 214     }
 215     if (!XISR(icp)) {
 216         icp_resend(icp);
 217     }
 218 }
 219
 220 void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
 221 {
 222     ICPState *icp = xics_icp_get(ics->xics, server);
 223
 224     trace_xics_icp_irq(server, nr, priority);
 225
 226     if ((priority >= CPPR(icp))
 227         || (XISR(icp) && (icp->pending_priority <= priority))) {
 228         ics_reject(ics, nr);
 229     } else {
 230         if (XISR(icp) && icp->xirr_owner) {
 231             ics_reject(icp->xirr_owner, XISR(icp));
 232             icp->xirr_owner = NULL;
 233         }
 234         icp->xirr = (icp->xirr & ~XISR_MASK) | (nr & XISR_MASK);
 235         icp->xirr_owner = ics;
 236         icp->pending_priority = priority;
 237         trace_xics_icp_raise(icp->xirr, icp->pending_priority);
 238         qemu_irq_raise(icp->output);
 239     }
 240 }
 241
 242 static int icp_pre_save(void *opaque)
 243 {
 244     ICPState *icp = opaque;
 245
 246     if (kvm_irqchip_in_kernel()) {
 247         icp_get_kvm_state(icp);
 248     }
 249
 250     return 0;
 251 }
 252
 253 static int icp_post_load(void *opaque, int version_id)
 254 {
 255     ICPState *icp = opaque;
 256
 257     if (kvm_irqchip_in_kernel()) {
 258         Error *local_err = NULL;
 259         int ret;
 260
 261         ret = icp_set_kvm_state(icp, &local_err);
 262         if (ret < 0) {
 263             error_report_err(local_err);
 264             return ret;
 265         }
 266     }
 267
 268     return 0;
 269 }
 270
 271 static const VMStateDescription vmstate_icp_server = {
 272     .name = "icp/server",
 273     .version_id = 1,
 274     .minimum_version_id = 1,
 275     .pre_save = icp_pre_save,
 276     .post_load = icp_post_load,
 277     .fields = (VMStateField[]) {
 278         /* Sanity check */
 279         VMSTATE_UINT32(xirr, ICPState),
 280         VMSTATE_UINT8(pending_priority, ICPState),
 281         VMSTATE_UINT8(mfrr, ICPState),
 282         VMSTATE_END_OF_LIST()
 283     },
 284 };
 285
 286 void icp_reset(ICPState *icp)
 287 {
 288     icp->xirr = 0;
 289     icp->pending_priority = 0xff;
 290     icp->mfrr = 0xff;
 291
 292     if (kvm_irqchip_in_kernel()) {
 293         Error *local_err = NULL;
 294
 295         icp_set_kvm_state(icp, &local_err);
 296         if (local_err) {
 297             error_report_err(local_err);
 298         }
 299     }
 300 }
 301
 302 static void icp_realize(DeviceState *dev, Error **errp)
 303 {
 304     ICPState *icp = ICP(dev);
 305     CPUPPCState *env;
 306     Error *err = NULL;
 307
 308     assert(icp->xics);
 309     assert(icp->cs);
 310
 311     env = &POWERPC_CPU(icp->cs)->env;
 312     switch (PPC_INPUT(env)) {
 313     case PPC_FLAGS_INPUT_POWER7:
 314         icp->output = env->irq_inputs[POWER7_INPUT_INT];
 315         break;
 316     case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */
 317         icp->output = env->irq_inputs[POWER9_INPUT_INT];
 318         break;
 319
 320     case PPC_FLAGS_INPUT_970:
 321         icp->output = env->irq_inputs[PPC970_INPUT_INT];
 322         break;
 323
 324     default:
 325         error_setg(errp, "XICS interrupt controller does not support this CPU bus model");
 326         return;
 327     }
 328
 329     /* Connect the presenter to the VCPU (required for CPU hotplug) */
 330     if (kvm_irqchip_in_kernel()) {
 331         icp_kvm_realize(dev, &err);
 332         if (err) {
 333             error_propagate(errp, err);
 334             return;
 335         }
 336     }
 337
 338     vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp);
 339 }
 340
 341 static void icp_unrealize(DeviceState *dev)
 342 {
 343     ICPState *icp = ICP(dev);
 344
 345     vmstate_unregister(NULL, &vmstate_icp_server, icp);
 346 }
 347
 348 static Property icp_properties[] = {
 349     DEFINE_PROP_LINK(ICP_PROP_XICS, ICPState, xics, TYPE_XICS_FABRIC,
 350                      XICSFabric *),
 351     DEFINE_PROP_LINK(ICP_PROP_CPU, ICPState, cs, TYPE_CPU, CPUState *),
 352     DEFINE_PROP_END_OF_LIST(),
 353 };
 354
 355 static void icp_class_init(ObjectClass *klass, void *data)
 356 {
 357     DeviceClass *dc = DEVICE_CLASS(klass);
 358
 359     dc->realize = icp_realize;
 360     dc->unrealize = icp_unrealize;
 361     device_class_set_props(dc, icp_properties);
 362     /*
 363      * Reason: part of XICS interrupt controller, needs to be wired up
 364      * by icp_create().
 365      */
 366     dc->user_creatable = false;
 367 }
 368
 369 static const TypeInfo icp_info = {
 370     .name = TYPE_ICP,
 371     .parent = TYPE_DEVICE,
 372     .instance_size = sizeof(ICPState),
 373     .class_init = icp_class_init,
 374     .class_size = sizeof(ICPStateClass),
 375 };
 376
 377 Object *icp_create(Object *cpu, const char *type, XICSFabric *xi, Error **errp)
 378 {
 379     Error *local_err = NULL;
 380     Object *obj;
 381
 382     obj = object_new(type);
 383     object_property_add_child(cpu, type, obj);
 384     object_unref(obj);
 385     object_property_set_link(obj, OBJECT(xi), ICP_PROP_XICS, &error_abort);
 386     object_property_set_link(obj, cpu, ICP_PROP_CPU, &error_abort);
 387     object_property_set_bool(obj, true, "realized", &local_err);
 388     if (local_err) {
 389         object_unparent(obj);
 390         error_propagate(errp, local_err);
 391         obj = NULL;
 392     }
 393
 394     return obj;
 395 }
 396
 397 void icp_destroy(ICPState *icp)
 398 {
 399     Object *obj = OBJECT(icp);
 400
 401     object_unparent(obj);
 402 }
 403
 404 /*
 405  * ICS: Source layer
 406  */
 407 static void ics_resend_msi(ICSState *ics, int srcno)
 408 {
 409     ICSIRQState *irq = ics->irqs + srcno;
 410
 411     /* FIXME: filter by server#? */
 412     if (irq->status & XICS_STATUS_REJECTED) {
 413         irq->status &= ~XICS_STATUS_REJECTED;
 414         if (irq->priority != 0xff) {
 415             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 416         }
 417     }
 418 }
 419
 420 static void ics_resend_lsi(ICSState *ics, int srcno)
 421 {
 422     ICSIRQState *irq = ics->irqs + srcno;
 423
 424     if ((irq->priority != 0xff)
 425         && (irq->status & XICS_STATUS_ASSERTED)
 426         && !(irq->status & XICS_STATUS_SENT)) {
 427         irq->status |= XICS_STATUS_SENT;
 428         icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 429     }
 430 }
 431
 432 static void ics_set_irq_msi(ICSState *ics, int srcno, int val)
 433 {
 434     ICSIRQState *irq = ics->irqs + srcno;
 435
 436     trace_xics_ics_set_irq_msi(srcno, srcno + ics->offset);
 437
 438     if (val) {
 439         if (irq->priority == 0xff) {
 440             irq->status |= XICS_STATUS_MASKED_PENDING;
 441             trace_xics_masked_pending();
 442         } else  {
 443             icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 444         }
 445     }
 446 }
 447
 448 static void ics_set_irq_lsi(ICSState *ics, int srcno, int val)
 449 {
 450     ICSIRQState *irq = ics->irqs + srcno;
 451
 452     trace_xics_ics_set_irq_lsi(srcno, srcno + ics->offset);
 453     if (val) {
 454         irq->status |= XICS_STATUS_ASSERTED;
 455     } else {
 456         irq->status &= ~XICS_STATUS_ASSERTED;
 457     }
 458     ics_resend_lsi(ics, srcno);
 459 }
 460
 461 void ics_set_irq(void *opaque, int srcno, int val)
 462 {
 463     ICSState *ics = (ICSState *)opaque;
 464
 465     if (kvm_irqchip_in_kernel()) {
 466         ics_kvm_set_irq(ics, srcno, val);
 467         return;
 468     }
 469
 470     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 471         ics_set_irq_lsi(ics, srcno, val);
 472     } else {
 473         ics_set_irq_msi(ics, srcno, val);
 474     }
 475 }
 476
 477 static void ics_write_xive_msi(ICSState *ics, int srcno)
 478 {
 479     ICSIRQState *irq = ics->irqs + srcno;
 480
 481     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
 482         || (irq->priority == 0xff)) {
 483         return;
 484     }
 485
 486     irq->status &= ~XICS_STATUS_MASKED_PENDING;
 487     icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
 488 }
 489
 490 static void ics_write_xive_lsi(ICSState *ics, int srcno)
 491 {
 492     ics_resend_lsi(ics, srcno);
 493 }
 494
 495 void ics_write_xive(ICSState *ics, int srcno, int server,
 496                     uint8_t priority, uint8_t saved_priority)
 497 {
 498     ICSIRQState *irq = ics->irqs + srcno;
 499
 500     irq->server = server;
 501     irq->priority = priority;
 502     irq->saved_priority = saved_priority;
 503
 504     trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority);
 505
 506     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 507         ics_write_xive_lsi(ics, srcno);
 508     } else {
 509         ics_write_xive_msi(ics, srcno);
 510     }
 511 }
 512
 513 static void ics_reject(ICSState *ics, uint32_t nr)
 514 {
 515     ICSStateClass *isc = ICS_GET_CLASS(ics);
 516     ICSIRQState *irq = ics->irqs + nr - ics->offset;
 517
 518     if (isc->reject) {
 519         isc->reject(ics, nr);
 520         return;
 521     }
 522
 523     trace_xics_ics_reject(nr, nr - ics->offset);
 524     if (irq->flags & XICS_FLAGS_IRQ_MSI) {
 525         irq->status |= XICS_STATUS_REJECTED;
 526     } else if (irq->flags & XICS_FLAGS_IRQ_LSI) {
 527         irq->status &= ~XICS_STATUS_SENT;
 528     }
 529 }
 530
 531 void ics_resend(ICSState *ics)
 532 {
 533     ICSStateClass *isc = ICS_GET_CLASS(ics);
 534     int i;
 535
 536     if (isc->resend) {
 537         isc->resend(ics);
 538         return;
 539     }
 540
 541     for (i = 0; i < ics->nr_irqs; i++) {
 542         /* FIXME: filter by server#? */
 543         if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
 544             ics_resend_lsi(ics, i);
 545         } else {
 546             ics_resend_msi(ics, i);
 547         }
 548     }
 549 }
 550
 551 static void ics_eoi(ICSState *ics, uint32_t nr)
 552 {
 553     int srcno = nr - ics->offset;
 554     ICSIRQState *irq = ics->irqs + srcno;
 555
 556     trace_xics_ics_eoi(nr);
 557
 558     if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
 559         irq->status &= ~XICS_STATUS_SENT;
 560     }
 561 }
 562
 563 static void ics_reset_irq(ICSIRQState *irq)
 564 {
 565     irq->priority = 0xff;
 566     irq->saved_priority = 0xff;
 567 }
 568
 569 static void ics_reset(DeviceState *dev)
 570 {
 571     ICSState *ics = ICS(dev);
 572     int i;
 573     uint8_t flags[ics->nr_irqs];
 574
 575     for (i = 0; i < ics->nr_irqs; i++) {
 576         flags[i] = ics->irqs[i].flags;
 577     }
 578
 579     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
 580
 581     for (i = 0; i < ics->nr_irqs; i++) {
 582         ics_reset_irq(ics->irqs + i);
 583         ics->irqs[i].flags = flags[i];
 584     }
 585
 586     if (kvm_irqchip_in_kernel()) {
 587         Error *local_err = NULL;
 588
 589         ics_set_kvm_state(ICS(dev), &local_err);
 590         if (local_err) {
 591             error_report_err(local_err);
 592         }
 593     }
 594 }
 595
 596 static void ics_reset_handler(void *dev)
 597 {
 598     ics_reset(dev);
 599 }
 600
 601 static void ics_realize(DeviceState *dev, Error **errp)
 602 {
 603     ICSState *ics = ICS(dev);
 604
 605     assert(ics->xics);
 606
 607     if (!ics->nr_irqs) {
 608         error_setg(errp, "Number of interrupts needs to be greater 0");
 609         return;
 610     }
 611     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
 612
 613     qemu_register_reset(ics_reset_handler, ics);
 614 }
 615
 616 static void ics_instance_init(Object *obj)
 617 {
 618     ICSState *ics = ICS(obj);
 619
 620     ics->offset = XICS_IRQ_BASE;
 621 }
 622
 623 static int ics_pre_save(void *opaque)
 624 {
 625     ICSState *ics = opaque;
 626
 627     if (kvm_irqchip_in_kernel()) {
 628         ics_get_kvm_state(ics);
 629     }
 630
 631     return 0;
 632 }
 633
 634 static int ics_post_load(void *opaque, int version_id)
 635 {
 636     ICSState *ics = opaque;
 637
 638     if (kvm_irqchip_in_kernel()) {
 639         Error *local_err = NULL;
 640         int ret;
 641
 642         ret = ics_set_kvm_state(ics, &local_err);
 643         if (ret < 0) {
 644             error_report_err(local_err);
 645             return ret;
 646         }
 647     }
 648
 649     return 0;
 650 }
 651
 652 static const VMStateDescription vmstate_ics_irq = {
 653     .name = "ics/irq",
 654     .version_id = 2,
 655     .minimum_version_id = 1,
 656     .fields = (VMStateField[]) {
 657         VMSTATE_UINT32(server, ICSIRQState),
 658         VMSTATE_UINT8(priority, ICSIRQState),
 659         VMSTATE_UINT8(saved_priority, ICSIRQState),
 660         VMSTATE_UINT8(status, ICSIRQState),
 661         VMSTATE_UINT8(flags, ICSIRQState),
 662         VMSTATE_END_OF_LIST()
 663     },
 664 };
 665
 666 static const VMStateDescription vmstate_ics = {
 667     .name = "ics",
 668     .version_id = 1,
 669     .minimum_version_id = 1,
 670     .pre_save = ics_pre_save,
 671     .post_load = ics_post_load,
 672     .fields = (VMStateField[]) {
 673         /* Sanity check */
 674         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState, NULL),
 675
 676         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
 677                                              vmstate_ics_irq,
 678                                              ICSIRQState),
 679         VMSTATE_END_OF_LIST()
 680     },
 681 };
 682
 683 static Property ics_properties[] = {
 684     DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0),
 685     DEFINE_PROP_LINK(ICS_PROP_XICS, ICSState, xics, TYPE_XICS_FABRIC,
 686                      XICSFabric *),
 687     DEFINE_PROP_END_OF_LIST(),
 688 };
 689
 690 static void ics_class_init(ObjectClass *klass, void *data)
 691 {
 692     DeviceClass *dc = DEVICE_CLASS(klass);
 693
 694     dc->realize = ics_realize;
 695     device_class_set_props(dc, ics_properties);
 696     dc->reset = ics_reset;
 697     dc->vmsd = &vmstate_ics;
 698     /*
 699      * Reason: part of XICS interrupt controller, needs to be wired up,
 700      * e.g. by spapr_irq_init().
 701      */
 702     dc->user_creatable = false;
 703 }
 704
 705 static const TypeInfo ics_info = {
 706     .name = TYPE_ICS,
 707     .parent = TYPE_DEVICE,
 708     .instance_size = sizeof(ICSState),
 709     .instance_init = ics_instance_init,
 710     .class_init = ics_class_init,
 711     .class_size = sizeof(ICSStateClass),
 712 };
 713
 714 static const TypeInfo xics_fabric_info = {
 715     .name = TYPE_XICS_FABRIC,
 716     .parent = TYPE_INTERFACE,
 717     .class_size = sizeof(XICSFabricClass),
 718 };
 719
 720 /*
 721  * Exported functions
 722  */
 723 ICPState *xics_icp_get(XICSFabric *xi, int server)
 724 {
 725     XICSFabricClass *xic = XICS_FABRIC_GET_CLASS(xi);
 726
 727     return xic->icp_get(xi, server);
 728 }
 729
 730 void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
 731 {
 732     assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
 733
 734     ics->irqs[srcno].flags |=
 735         lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
 736
 737     if (kvm_irqchip_in_kernel()) {
 738         Error *local_err = NULL;
 739
 740         ics_reset_irq(ics->irqs + srcno);
 741         ics_set_kvm_state_one(ics, srcno, &local_err);
 742         if (local_err) {
 743             error_report_err(local_err);
 744         }
 745     }
 746 }
 747
 748 static void xics_register_types(void)
 749 {
 750     type_register_static(&ics_info);
 751     type_register_static(&icp_info);
 752     type_register_static(&xics_fabric_info);
 753 }
 754
 755 type_init(xics_register_types)