2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "qemu-common.h"
34 #include "qemu/timer.h"
35 #include "hw/ppc/xics.h"
36 #include "qemu/error-report.h"
37 #include "qapi/visitor.h"
38 #include "monitor/monitor.h"
39 #include "hw/intc/intc.h"
41 void icp_pic_print_info(ICPState
*icp
, Monitor
*mon
)
43 ICPStateClass
*icpc
= ICP_GET_CLASS(icp
);
44 int cpu_index
= icp
->cs
? icp
->cs
->cpu_index
: -1;
50 if (icpc
->synchronize_state
) {
51 icpc
->synchronize_state(icp
);
54 monitor_printf(mon
, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
55 cpu_index
, icp
->xirr
, icp
->xirr_owner
,
56 icp
->pending_priority
, icp
->mfrr
);
59 void ics_pic_print_info(ICSState
*ics
, Monitor
*mon
)
61 ICSStateClass
*icsc
= ICS_BASE_GET_CLASS(ics
);
64 monitor_printf(mon
, "ICS %4x..%4x %p\n",
65 ics
->offset
, ics
->offset
+ ics
->nr_irqs
- 1, ics
);
71 if (icsc
->synchronize_state
) {
72 icsc
->synchronize_state(ics
);
75 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
76 ICSIRQState
*irq
= ics
->irqs
+ i
;
78 if (!(irq
->flags
& XICS_FLAGS_IRQ_MASK
)) {
81 monitor_printf(mon
, " %4x %s %02x %02x\n",
83 (irq
->flags
& XICS_FLAGS_IRQ_LSI
) ?
85 irq
->priority
, irq
->status
);
90 * ICP: Presentation layer
93 #define XISR_MASK 0x00ffffff
94 #define CPPR_MASK 0xff000000
96 #define XISR(icp) (((icp)->xirr) & XISR_MASK)
97 #define CPPR(icp) (((icp)->xirr) >> 24)
99 static void ics_reject(ICSState
*ics
, uint32_t nr
)
101 ICSStateClass
*k
= ICS_BASE_GET_CLASS(ics
);
108 void ics_resend(ICSState
*ics
)
110 ICSStateClass
*k
= ICS_BASE_GET_CLASS(ics
);
117 static void ics_eoi(ICSState
*ics
, int nr
)
119 ICSStateClass
*k
= ICS_BASE_GET_CLASS(ics
);
126 static void icp_check_ipi(ICPState
*icp
)
128 if (XISR(icp
) && (icp
->pending_priority
<= icp
->mfrr
)) {
132 trace_xics_icp_check_ipi(icp
->cs
->cpu_index
, icp
->mfrr
);
134 if (XISR(icp
) && icp
->xirr_owner
) {
135 ics_reject(icp
->xirr_owner
, XISR(icp
));
138 icp
->xirr
= (icp
->xirr
& ~XISR_MASK
) | XICS_IPI
;
139 icp
->pending_priority
= icp
->mfrr
;
140 icp
->xirr_owner
= NULL
;
141 qemu_irq_raise(icp
->output
);
144 void icp_resend(ICPState
*icp
)
146 XICSFabric
*xi
= icp
->xics
;
147 XICSFabricClass
*xic
= XICS_FABRIC_GET_CLASS(xi
);
149 if (icp
->mfrr
< CPPR(icp
)) {
156 void icp_set_cppr(ICPState
*icp
, uint8_t cppr
)
161 old_cppr
= CPPR(icp
);
162 icp
->xirr
= (icp
->xirr
& ~CPPR_MASK
) | (cppr
<< 24);
164 if (cppr
< old_cppr
) {
165 if (XISR(icp
) && (cppr
<= icp
->pending_priority
)) {
166 old_xisr
= XISR(icp
);
167 icp
->xirr
&= ~XISR_MASK
; /* Clear XISR */
168 icp
->pending_priority
= 0xff;
169 qemu_irq_lower(icp
->output
);
170 if (icp
->xirr_owner
) {
171 ics_reject(icp
->xirr_owner
, old_xisr
);
172 icp
->xirr_owner
= NULL
;
182 void icp_set_mfrr(ICPState
*icp
, uint8_t mfrr
)
185 if (mfrr
< CPPR(icp
)) {
190 uint32_t icp_accept(ICPState
*icp
)
192 uint32_t xirr
= icp
->xirr
;
194 qemu_irq_lower(icp
->output
);
195 icp
->xirr
= icp
->pending_priority
<< 24;
196 icp
->pending_priority
= 0xff;
197 icp
->xirr_owner
= NULL
;
199 trace_xics_icp_accept(xirr
, icp
->xirr
);
204 uint32_t icp_ipoll(ICPState
*icp
, uint32_t *mfrr
)
212 void icp_eoi(ICPState
*icp
, uint32_t xirr
)
214 XICSFabric
*xi
= icp
->xics
;
215 XICSFabricClass
*xic
= XICS_FABRIC_GET_CLASS(xi
);
219 /* Send EOI -> ICS */
220 icp
->xirr
= (icp
->xirr
& ~CPPR_MASK
) | (xirr
& CPPR_MASK
);
221 trace_xics_icp_eoi(icp
->cs
->cpu_index
, xirr
, icp
->xirr
);
222 irq
= xirr
& XISR_MASK
;
224 ics
= xic
->ics_get(xi
, irq
);
233 static void icp_irq(ICSState
*ics
, int server
, int nr
, uint8_t priority
)
235 ICPState
*icp
= xics_icp_get(ics
->xics
, server
);
237 trace_xics_icp_irq(server
, nr
, priority
);
239 if ((priority
>= CPPR(icp
))
240 || (XISR(icp
) && (icp
->pending_priority
<= priority
))) {
243 if (XISR(icp
) && icp
->xirr_owner
) {
244 ics_reject(icp
->xirr_owner
, XISR(icp
));
245 icp
->xirr_owner
= NULL
;
247 icp
->xirr
= (icp
->xirr
& ~XISR_MASK
) | (nr
& XISR_MASK
);
248 icp
->xirr_owner
= ics
;
249 icp
->pending_priority
= priority
;
250 trace_xics_icp_raise(icp
->xirr
, icp
->pending_priority
);
251 qemu_irq_raise(icp
->output
);
255 static int icp_dispatch_pre_save(void *opaque
)
257 ICPState
*icp
= opaque
;
258 ICPStateClass
*info
= ICP_GET_CLASS(icp
);
260 if (info
->pre_save
) {
267 static int icp_dispatch_post_load(void *opaque
, int version_id
)
269 ICPState
*icp
= opaque
;
270 ICPStateClass
*info
= ICP_GET_CLASS(icp
);
272 if (info
->post_load
) {
273 return info
->post_load(icp
, version_id
);
279 static const VMStateDescription vmstate_icp_server
= {
280 .name
= "icp/server",
282 .minimum_version_id
= 1,
283 .pre_save
= icp_dispatch_pre_save
,
284 .post_load
= icp_dispatch_post_load
,
285 .fields
= (VMStateField
[]) {
287 VMSTATE_UINT32(xirr
, ICPState
),
288 VMSTATE_UINT8(pending_priority
, ICPState
),
289 VMSTATE_UINT8(mfrr
, ICPState
),
290 VMSTATE_END_OF_LIST()
294 static void icp_reset(void *dev
)
296 ICPState
*icp
= ICP(dev
);
299 icp
->pending_priority
= 0xff;
302 /* Make all outputs are deasserted */
303 qemu_set_irq(icp
->output
, 0);
306 static void icp_realize(DeviceState
*dev
, Error
**errp
)
308 ICPState
*icp
= ICP(dev
);
314 obj
= object_property_get_link(OBJECT(dev
), ICP_PROP_XICS
, &err
);
316 error_propagate(errp
, err
);
317 error_prepend(errp
, "required link '" ICP_PROP_XICS
"' not found: ");
321 icp
->xics
= XICS_FABRIC(obj
);
323 obj
= object_property_get_link(OBJECT(dev
), ICP_PROP_CPU
, &err
);
325 error_propagate(errp
, err
);
326 error_prepend(errp
, "required link '" ICP_PROP_CPU
"' not found: ");
330 cpu
= POWERPC_CPU(obj
);
334 switch (PPC_INPUT(env
)) {
335 case PPC_FLAGS_INPUT_POWER7
:
336 icp
->output
= env
->irq_inputs
[POWER7_INPUT_INT
];
339 case PPC_FLAGS_INPUT_970
:
340 icp
->output
= env
->irq_inputs
[PPC970_INPUT_INT
];
344 error_setg(errp
, "XICS interrupt controller does not support this CPU bus model");
348 qemu_register_reset(icp_reset
, dev
);
349 vmstate_register(NULL
, icp
->cs
->cpu_index
, &vmstate_icp_server
, icp
);
352 static void icp_unrealize(DeviceState
*dev
, Error
**errp
)
354 ICPState
*icp
= ICP(dev
);
356 vmstate_unregister(NULL
, &vmstate_icp_server
, icp
);
357 qemu_unregister_reset(icp_reset
, dev
);
360 static void icp_class_init(ObjectClass
*klass
, void *data
)
362 DeviceClass
*dc
= DEVICE_CLASS(klass
);
364 dc
->realize
= icp_realize
;
365 dc
->unrealize
= icp_unrealize
;
368 static const TypeInfo icp_info
= {
370 .parent
= TYPE_DEVICE
,
371 .instance_size
= sizeof(ICPState
),
372 .class_init
= icp_class_init
,
373 .class_size
= sizeof(ICPStateClass
),
376 Object
*icp_create(Object
*cpu
, const char *type
, XICSFabric
*xi
, Error
**errp
)
378 Error
*local_err
= NULL
;
381 obj
= object_new(type
);
382 object_property_add_child(cpu
, type
, obj
, &error_abort
);
384 object_property_add_const_link(obj
, ICP_PROP_XICS
, OBJECT(xi
),
386 object_property_add_const_link(obj
, ICP_PROP_CPU
, cpu
, &error_abort
);
387 object_property_set_bool(obj
, true, "realized", &local_err
);
389 object_unparent(obj
);
390 error_propagate(errp
, local_err
);
400 static void ics_simple_resend_msi(ICSState
*ics
, int srcno
)
402 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
404 /* FIXME: filter by server#? */
405 if (irq
->status
& XICS_STATUS_REJECTED
) {
406 irq
->status
&= ~XICS_STATUS_REJECTED
;
407 if (irq
->priority
!= 0xff) {
408 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
413 static void ics_simple_resend_lsi(ICSState
*ics
, int srcno
)
415 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
417 if ((irq
->priority
!= 0xff)
418 && (irq
->status
& XICS_STATUS_ASSERTED
)
419 && !(irq
->status
& XICS_STATUS_SENT
)) {
420 irq
->status
|= XICS_STATUS_SENT
;
421 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
425 static void ics_simple_set_irq_msi(ICSState
*ics
, int srcno
, int val
)
427 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
429 trace_xics_ics_simple_set_irq_msi(srcno
, srcno
+ ics
->offset
);
432 if (irq
->priority
== 0xff) {
433 irq
->status
|= XICS_STATUS_MASKED_PENDING
;
434 trace_xics_masked_pending();
436 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
441 static void ics_simple_set_irq_lsi(ICSState
*ics
, int srcno
, int val
)
443 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
445 trace_xics_ics_simple_set_irq_lsi(srcno
, srcno
+ ics
->offset
);
447 irq
->status
|= XICS_STATUS_ASSERTED
;
449 irq
->status
&= ~XICS_STATUS_ASSERTED
;
451 ics_simple_resend_lsi(ics
, srcno
);
454 static void ics_simple_set_irq(void *opaque
, int srcno
, int val
)
456 ICSState
*ics
= (ICSState
*)opaque
;
458 if (ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_LSI
) {
459 ics_simple_set_irq_lsi(ics
, srcno
, val
);
461 ics_simple_set_irq_msi(ics
, srcno
, val
);
465 static void ics_simple_write_xive_msi(ICSState
*ics
, int srcno
)
467 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
469 if (!(irq
->status
& XICS_STATUS_MASKED_PENDING
)
470 || (irq
->priority
== 0xff)) {
474 irq
->status
&= ~XICS_STATUS_MASKED_PENDING
;
475 icp_irq(ics
, irq
->server
, srcno
+ ics
->offset
, irq
->priority
);
478 static void ics_simple_write_xive_lsi(ICSState
*ics
, int srcno
)
480 ics_simple_resend_lsi(ics
, srcno
);
483 void ics_simple_write_xive(ICSState
*ics
, int srcno
, int server
,
484 uint8_t priority
, uint8_t saved_priority
)
486 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
488 irq
->server
= server
;
489 irq
->priority
= priority
;
490 irq
->saved_priority
= saved_priority
;
492 trace_xics_ics_simple_write_xive(ics
->offset
+ srcno
, srcno
, server
,
495 if (ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_LSI
) {
496 ics_simple_write_xive_lsi(ics
, srcno
);
498 ics_simple_write_xive_msi(ics
, srcno
);
502 static void ics_simple_reject(ICSState
*ics
, uint32_t nr
)
504 ICSIRQState
*irq
= ics
->irqs
+ nr
- ics
->offset
;
506 trace_xics_ics_simple_reject(nr
, nr
- ics
->offset
);
507 if (irq
->flags
& XICS_FLAGS_IRQ_MSI
) {
508 irq
->status
|= XICS_STATUS_REJECTED
;
509 } else if (irq
->flags
& XICS_FLAGS_IRQ_LSI
) {
510 irq
->status
&= ~XICS_STATUS_SENT
;
514 static void ics_simple_resend(ICSState
*ics
)
518 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
519 /* FIXME: filter by server#? */
520 if (ics
->irqs
[i
].flags
& XICS_FLAGS_IRQ_LSI
) {
521 ics_simple_resend_lsi(ics
, i
);
523 ics_simple_resend_msi(ics
, i
);
528 static void ics_simple_eoi(ICSState
*ics
, uint32_t nr
)
530 int srcno
= nr
- ics
->offset
;
531 ICSIRQState
*irq
= ics
->irqs
+ srcno
;
533 trace_xics_ics_simple_eoi(nr
);
535 if (ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_LSI
) {
536 irq
->status
&= ~XICS_STATUS_SENT
;
540 static void ics_simple_reset(DeviceState
*dev
)
542 ICSStateClass
*icsc
= ICS_BASE_GET_CLASS(dev
);
544 icsc
->parent_reset(dev
);
547 static void ics_simple_reset_handler(void *dev
)
549 ics_simple_reset(dev
);
552 static int ics_simple_dispatch_pre_save(void *opaque
)
554 ICSState
*ics
= opaque
;
555 ICSStateClass
*info
= ICS_BASE_GET_CLASS(ics
);
557 if (info
->pre_save
) {
564 static int ics_simple_dispatch_post_load(void *opaque
, int version_id
)
566 ICSState
*ics
= opaque
;
567 ICSStateClass
*info
= ICS_BASE_GET_CLASS(ics
);
569 if (info
->post_load
) {
570 return info
->post_load(ics
, version_id
);
576 static const VMStateDescription vmstate_ics_simple_irq
= {
579 .minimum_version_id
= 1,
580 .fields
= (VMStateField
[]) {
581 VMSTATE_UINT32(server
, ICSIRQState
),
582 VMSTATE_UINT8(priority
, ICSIRQState
),
583 VMSTATE_UINT8(saved_priority
, ICSIRQState
),
584 VMSTATE_UINT8(status
, ICSIRQState
),
585 VMSTATE_UINT8(flags
, ICSIRQState
),
586 VMSTATE_END_OF_LIST()
590 static const VMStateDescription vmstate_ics_simple
= {
593 .minimum_version_id
= 1,
594 .pre_save
= ics_simple_dispatch_pre_save
,
595 .post_load
= ics_simple_dispatch_post_load
,
596 .fields
= (VMStateField
[]) {
598 VMSTATE_UINT32_EQUAL(nr_irqs
, ICSState
, NULL
),
600 VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs
, ICSState
, nr_irqs
,
601 vmstate_ics_simple_irq
,
603 VMSTATE_END_OF_LIST()
607 static void ics_simple_realize(DeviceState
*dev
, Error
**errp
)
609 ICSState
*ics
= ICS_SIMPLE(dev
);
610 ICSStateClass
*icsc
= ICS_BASE_GET_CLASS(ics
);
611 Error
*local_err
= NULL
;
613 icsc
->parent_realize(dev
, &local_err
);
615 error_propagate(errp
, local_err
);
619 ics
->qirqs
= qemu_allocate_irqs(ics_simple_set_irq
, ics
, ics
->nr_irqs
);
621 qemu_register_reset(ics_simple_reset_handler
, ics
);
624 static void ics_simple_class_init(ObjectClass
*klass
, void *data
)
626 DeviceClass
*dc
= DEVICE_CLASS(klass
);
627 ICSStateClass
*isc
= ICS_BASE_CLASS(klass
);
629 device_class_set_parent_realize(dc
, ics_simple_realize
,
630 &isc
->parent_realize
);
631 device_class_set_parent_reset(dc
, ics_simple_reset
,
634 dc
->vmsd
= &vmstate_ics_simple
;
635 isc
->reject
= ics_simple_reject
;
636 isc
->resend
= ics_simple_resend
;
637 isc
->eoi
= ics_simple_eoi
;
640 static const TypeInfo ics_simple_info
= {
641 .name
= TYPE_ICS_SIMPLE
,
642 .parent
= TYPE_ICS_BASE
,
643 .instance_size
= sizeof(ICSState
),
644 .class_init
= ics_simple_class_init
,
645 .class_size
= sizeof(ICSStateClass
),
648 static void ics_base_reset(DeviceState
*dev
)
650 ICSState
*ics
= ICS_BASE(dev
);
652 uint8_t flags
[ics
->nr_irqs
];
654 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
655 flags
[i
] = ics
->irqs
[i
].flags
;
658 memset(ics
->irqs
, 0, sizeof(ICSIRQState
) * ics
->nr_irqs
);
660 for (i
= 0; i
< ics
->nr_irqs
; i
++) {
661 ics
->irqs
[i
].priority
= 0xff;
662 ics
->irqs
[i
].saved_priority
= 0xff;
663 ics
->irqs
[i
].flags
= flags
[i
];
667 static void ics_base_realize(DeviceState
*dev
, Error
**errp
)
669 ICSState
*ics
= ICS_BASE(dev
);
673 obj
= object_property_get_link(OBJECT(dev
), ICS_PROP_XICS
, &err
);
675 error_propagate(errp
, err
);
676 error_prepend(errp
, "required link '" ICS_PROP_XICS
"' not found: ");
679 ics
->xics
= XICS_FABRIC(obj
);
682 error_setg(errp
, "Number of interrupts needs to be greater 0");
685 ics
->irqs
= g_malloc0(ics
->nr_irqs
* sizeof(ICSIRQState
));
688 static void ics_base_instance_init(Object
*obj
)
690 ICSState
*ics
= ICS_BASE(obj
);
692 ics
->offset
= XICS_IRQ_BASE
;
695 static Property ics_base_properties
[] = {
696 DEFINE_PROP_UINT32("nr-irqs", ICSState
, nr_irqs
, 0),
697 DEFINE_PROP_END_OF_LIST(),
700 static void ics_base_class_init(ObjectClass
*klass
, void *data
)
702 DeviceClass
*dc
= DEVICE_CLASS(klass
);
704 dc
->realize
= ics_base_realize
;
705 dc
->props
= ics_base_properties
;
706 dc
->reset
= ics_base_reset
;
709 static const TypeInfo ics_base_info
= {
710 .name
= TYPE_ICS_BASE
,
711 .parent
= TYPE_DEVICE
,
713 .instance_size
= sizeof(ICSState
),
714 .instance_init
= ics_base_instance_init
,
715 .class_init
= ics_base_class_init
,
716 .class_size
= sizeof(ICSStateClass
),
719 static const TypeInfo xics_fabric_info
= {
720 .name
= TYPE_XICS_FABRIC
,
721 .parent
= TYPE_INTERFACE
,
722 .class_size
= sizeof(XICSFabricClass
),
728 ICPState
*xics_icp_get(XICSFabric
*xi
, int server
)
730 XICSFabricClass
*xic
= XICS_FABRIC_GET_CLASS(xi
);
732 return xic
->icp_get(xi
, server
);
735 void ics_set_irq_type(ICSState
*ics
, int srcno
, bool lsi
)
737 assert(!(ics
->irqs
[srcno
].flags
& XICS_FLAGS_IRQ_MASK
));
739 ics
->irqs
[srcno
].flags
|=
740 lsi
? XICS_FLAGS_IRQ_LSI
: XICS_FLAGS_IRQ_MSI
;
743 static void xics_register_types(void)
745 type_register_static(&ics_simple_info
);
746 type_register_static(&ics_base_info
);
747 type_register_static(&icp_info
);
748 type_register_static(&xics_fabric_info
);
751 type_init(xics_register_types
)