2 * QEMU PowerPC XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "sysemu/dma.h"
17 #include "hw/qdev-properties.h"
18 #include "monitor/monitor.h"
19 #include "hw/ppc/xive.h"
20 #include "hw/ppc/xive_regs.h"
23 * XIVE Thread Interrupt Management context
27 * Convert a priority number to an Interrupt Pending Buffer (IPB)
28 * register, which indicates a pending interrupt at the priority
29 * corresponding to the bit number
31 static uint8_t priority_to_ipb(uint8_t priority
)
33 return priority
> XIVE_PRIORITY_MAX
?
34 0 : 1 << (XIVE_PRIORITY_MAX
- priority
);
38 * Convert an Interrupt Pending Buffer (IPB) register to a Pending
39 * Interrupt Priority Register (PIPR), which contains the priority of
40 * the most favored pending notification.
42 static uint8_t ipb_to_pipr(uint8_t ibp
)
44 return ibp
? clz32((uint32_t)ibp
<< 24) : 0xff;
47 static void ipb_update(uint8_t *regs
, uint8_t priority
)
49 regs
[TM_IPB
] |= priority_to_ipb(priority
);
50 regs
[TM_PIPR
] = ipb_to_pipr(regs
[TM_IPB
]);
53 static uint8_t exception_mask(uint8_t ring
)
61 g_assert_not_reached();
65 static uint64_t xive_tctx_accept(XiveTCTX
*tctx
, uint8_t ring
)
67 uint8_t *regs
= &tctx
->regs
[ring
];
68 uint8_t nsr
= regs
[TM_NSR
];
69 uint8_t mask
= exception_mask(ring
);
71 qemu_irq_lower(tctx
->output
);
73 if (regs
[TM_NSR
] & mask
) {
74 uint8_t cppr
= regs
[TM_PIPR
];
78 /* Reset the pending buffer bit */
79 regs
[TM_IPB
] &= ~priority_to_ipb(cppr
);
80 regs
[TM_PIPR
] = ipb_to_pipr(regs
[TM_IPB
]);
82 /* Drop Exception bit */
83 regs
[TM_NSR
] &= ~mask
;
86 return (nsr
<< 8) | regs
[TM_CPPR
];
89 static void xive_tctx_notify(XiveTCTX
*tctx
, uint8_t ring
)
91 uint8_t *regs
= &tctx
->regs
[ring
];
93 if (regs
[TM_PIPR
] < regs
[TM_CPPR
]) {
96 regs
[TM_NSR
] |= TM_QW1_NSR_EO
;
99 regs
[TM_NSR
] |= (TM_QW3_NSR_HE_PHYS
<< 6);
102 g_assert_not_reached();
104 qemu_irq_raise(tctx
->output
);
108 static void xive_tctx_set_cppr(XiveTCTX
*tctx
, uint8_t ring
, uint8_t cppr
)
110 if (cppr
> XIVE_PRIORITY_MAX
) {
114 tctx
->regs
[ring
+ TM_CPPR
] = cppr
;
116 /* CPPR has changed, check if we need to raise a pending exception */
117 xive_tctx_notify(tctx
, ring
);
121 * XIVE Thread Interrupt Management Area (TIMA)
124 static void xive_tm_set_hv_cppr(XiveTCTX
*tctx
, hwaddr offset
,
125 uint64_t value
, unsigned size
)
127 xive_tctx_set_cppr(tctx
, TM_QW3_HV_PHYS
, value
& 0xff);
130 static uint64_t xive_tm_ack_hv_reg(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
132 return xive_tctx_accept(tctx
, TM_QW3_HV_PHYS
);
135 static uint64_t xive_tm_pull_pool_ctx(XiveTCTX
*tctx
, hwaddr offset
,
140 ret
= tctx
->regs
[TM_QW2_HV_POOL
+ TM_WORD2
] & TM_QW2W2_POOL_CAM
;
141 tctx
->regs
[TM_QW2_HV_POOL
+ TM_WORD2
] &= ~TM_QW2W2_POOL_CAM
;
145 static void xive_tm_vt_push(XiveTCTX
*tctx
, hwaddr offset
,
146 uint64_t value
, unsigned size
)
148 tctx
->regs
[TM_QW3_HV_PHYS
+ TM_WORD2
] = value
& 0xff;
151 static uint64_t xive_tm_vt_poll(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
153 return tctx
->regs
[TM_QW3_HV_PHYS
+ TM_WORD2
] & 0xff;
157 * Define an access map for each page of the TIMA that we will use in
158 * the memory region ops to filter values when doing loads and stores
159 * of raw registers values
161 * Registers accessibility bits :
169 static const uint8_t xive_tm_hw_view
[] = {
170 /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
171 /* QW-1 OS */ 3, 3, 3, 3, 3, 3, 0, 3, 3, 3, 3, 3, 0, 0, 0, 0,
172 /* QW-2 POOL */ 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
173 /* QW-3 PHYS */ 3, 3, 3, 3, 0, 3, 0, 3, 3, 0, 0, 3, 3, 3, 3, 0,
176 static const uint8_t xive_tm_hv_view
[] = {
177 /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
178 /* QW-1 OS */ 3, 3, 3, 3, 3, 3, 0, 3, 3, 3, 3, 3, 0, 0, 0, 0,
179 /* QW-2 POOL */ 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0,
180 /* QW-3 PHYS */ 3, 3, 3, 3, 0, 3, 0, 3, 3, 0, 0, 3, 0, 0, 0, 0,
183 static const uint8_t xive_tm_os_view
[] = {
184 /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
185 /* QW-1 OS */ 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0,
186 /* QW-2 POOL */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
187 /* QW-3 PHYS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
190 static const uint8_t xive_tm_user_view
[] = {
191 /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
192 /* QW-1 OS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
193 /* QW-2 POOL */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
194 /* QW-3 PHYS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
198 * Overall TIMA access map for the thread interrupt management context
201 static const uint8_t *xive_tm_views
[] = {
202 [XIVE_TM_HW_PAGE
] = xive_tm_hw_view
,
203 [XIVE_TM_HV_PAGE
] = xive_tm_hv_view
,
204 [XIVE_TM_OS_PAGE
] = xive_tm_os_view
,
205 [XIVE_TM_USER_PAGE
] = xive_tm_user_view
,
209 * Computes a register access mask for a given offset in the TIMA
211 static uint64_t xive_tm_mask(hwaddr offset
, unsigned size
, bool write
)
213 uint8_t page_offset
= (offset
>> TM_SHIFT
) & 0x3;
214 uint8_t reg_offset
= offset
& 0x3F;
215 uint8_t reg_mask
= write
? 0x1 : 0x2;
219 for (i
= 0; i
< size
; i
++) {
220 if (xive_tm_views
[page_offset
][reg_offset
+ i
] & reg_mask
) {
221 mask
|= (uint64_t) 0xff << (8 * (size
- i
- 1));
228 static void xive_tm_raw_write(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
231 uint8_t ring_offset
= offset
& 0x30;
232 uint8_t reg_offset
= offset
& 0x3F;
233 uint64_t mask
= xive_tm_mask(offset
, size
, true);
237 * Only 4 or 8 bytes stores are allowed and the User ring is
240 if (size
< 4 || !mask
|| ring_offset
== TM_QW0_USER
) {
241 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid write access at TIMA @%"
242 HWADDR_PRIx
"\n", offset
);
247 * Use the register offset for the raw values and filter out
250 for (i
= 0; i
< size
; i
++) {
251 uint8_t byte_mask
= (mask
>> (8 * (size
- i
- 1)));
253 tctx
->regs
[reg_offset
+ i
] = (value
>> (8 * (size
- i
- 1))) &
259 static uint64_t xive_tm_raw_read(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
261 uint8_t ring_offset
= offset
& 0x30;
262 uint8_t reg_offset
= offset
& 0x3F;
263 uint64_t mask
= xive_tm_mask(offset
, size
, false);
268 * Only 4 or 8 bytes loads are allowed and the User ring is
271 if (size
< 4 || !mask
|| ring_offset
== TM_QW0_USER
) {
272 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid read access at TIMA @%"
273 HWADDR_PRIx
"\n", offset
);
277 /* Use the register offset for the raw values */
279 for (i
= 0; i
< size
; i
++) {
280 ret
|= (uint64_t) tctx
->regs
[reg_offset
+ i
] << (8 * (size
- i
- 1));
283 /* filter out reserved values */
288 * The TM context is mapped twice within each page. Stores and loads
289 * to the first mapping below 2K write and read the specified values
290 * without modification. The second mapping above 2K performs specific
291 * state changes (side effects) in addition to setting/returning the
292 * interrupt management area context of the processor thread.
294 static uint64_t xive_tm_ack_os_reg(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
296 return xive_tctx_accept(tctx
, TM_QW1_OS
);
299 static void xive_tm_set_os_cppr(XiveTCTX
*tctx
, hwaddr offset
,
300 uint64_t value
, unsigned size
)
302 xive_tctx_set_cppr(tctx
, TM_QW1_OS
, value
& 0xff);
306 * Adjust the IPB to allow a CPU to process event queues of other
307 * priorities during one physical interrupt cycle.
309 static void xive_tm_set_os_pending(XiveTCTX
*tctx
, hwaddr offset
,
310 uint64_t value
, unsigned size
)
312 ipb_update(&tctx
->regs
[TM_QW1_OS
], value
& 0xff);
313 xive_tctx_notify(tctx
, TM_QW1_OS
);
317 * Define a mapping of "special" operations depending on the TIMA page
318 * offset and the size of the operation.
320 typedef struct XiveTmOp
{
324 void (*write_handler
)(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
326 uint64_t (*read_handler
)(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
);
329 static const XiveTmOp xive_tm_operations
[] = {
331 * MMIOs below 2K : raw values and special operations without side
334 { XIVE_TM_OS_PAGE
, TM_QW1_OS
+ TM_CPPR
, 1, xive_tm_set_os_cppr
, NULL
},
335 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_CPPR
, 1, xive_tm_set_hv_cppr
, NULL
},
336 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_WORD2
, 1, xive_tm_vt_push
, NULL
},
337 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_WORD2
, 1, NULL
, xive_tm_vt_poll
},
339 /* MMIOs above 2K : special operations with side effects */
340 { XIVE_TM_OS_PAGE
, TM_SPC_ACK_OS_REG
, 2, NULL
, xive_tm_ack_os_reg
},
341 { XIVE_TM_OS_PAGE
, TM_SPC_SET_OS_PENDING
, 1, xive_tm_set_os_pending
, NULL
},
342 { XIVE_TM_HV_PAGE
, TM_SPC_ACK_HV_REG
, 2, NULL
, xive_tm_ack_hv_reg
},
343 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_POOL_CTX
, 4, NULL
, xive_tm_pull_pool_ctx
},
344 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_POOL_CTX
, 8, NULL
, xive_tm_pull_pool_ctx
},
347 static const XiveTmOp
*xive_tm_find_op(hwaddr offset
, unsigned size
, bool write
)
349 uint8_t page_offset
= (offset
>> TM_SHIFT
) & 0x3;
350 uint32_t op_offset
= offset
& 0xFFF;
353 for (i
= 0; i
< ARRAY_SIZE(xive_tm_operations
); i
++) {
354 const XiveTmOp
*xto
= &xive_tm_operations
[i
];
356 /* Accesses done from a more privileged TIMA page is allowed */
357 if (xto
->page_offset
>= page_offset
&&
358 xto
->op_offset
== op_offset
&&
360 ((write
&& xto
->write_handler
) || (!write
&& xto
->read_handler
))) {
370 void xive_tctx_tm_write(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
376 * TODO: check V bit in Q[0-3]W2
380 * First, check for special operations in the 2K region
382 if (offset
& 0x800) {
383 xto
= xive_tm_find_op(offset
, size
, true);
385 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid write access at TIMA"
386 "@%"HWADDR_PRIx
"\n", offset
);
388 xto
->write_handler(tctx
, offset
, value
, size
);
394 * Then, for special operations in the region below 2K.
396 xto
= xive_tm_find_op(offset
, size
, true);
398 xto
->write_handler(tctx
, offset
, value
, size
);
403 * Finish with raw access to the register values
405 xive_tm_raw_write(tctx
, offset
, value
, size
);
408 uint64_t xive_tctx_tm_read(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
413 * TODO: check V bit in Q[0-3]W2
417 * First, check for special operations in the 2K region
419 if (offset
& 0x800) {
420 xto
= xive_tm_find_op(offset
, size
, false);
422 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid read access to TIMA"
423 "@%"HWADDR_PRIx
"\n", offset
);
426 return xto
->read_handler(tctx
, offset
, size
);
430 * Then, for special operations in the region below 2K.
432 xto
= xive_tm_find_op(offset
, size
, false);
434 return xto
->read_handler(tctx
, offset
, size
);
438 * Finish with raw access to the register values
440 return xive_tm_raw_read(tctx
, offset
, size
);
443 static void xive_tm_write(void *opaque
, hwaddr offset
,
444 uint64_t value
, unsigned size
)
446 XiveTCTX
*tctx
= xive_router_get_tctx(XIVE_ROUTER(opaque
), current_cpu
);
448 xive_tctx_tm_write(tctx
, offset
, value
, size
);
451 static uint64_t xive_tm_read(void *opaque
, hwaddr offset
, unsigned size
)
453 XiveTCTX
*tctx
= xive_router_get_tctx(XIVE_ROUTER(opaque
), current_cpu
);
455 return xive_tctx_tm_read(tctx
, offset
, size
);
458 const MemoryRegionOps xive_tm_ops
= {
459 .read
= xive_tm_read
,
460 .write
= xive_tm_write
,
461 .endianness
= DEVICE_BIG_ENDIAN
,
463 .min_access_size
= 1,
464 .max_access_size
= 8,
467 .min_access_size
= 1,
468 .max_access_size
= 8,
472 static inline uint32_t xive_tctx_word2(uint8_t *ring
)
474 return *((uint32_t *) &ring
[TM_WORD2
]);
477 static char *xive_tctx_ring_print(uint8_t *ring
)
479 uint32_t w2
= xive_tctx_word2(ring
);
481 return g_strdup_printf("%02x %02x %02x %02x %02x "
482 "%02x %02x %02x %08x",
483 ring
[TM_NSR
], ring
[TM_CPPR
], ring
[TM_IPB
], ring
[TM_LSMFB
],
484 ring
[TM_ACK_CNT
], ring
[TM_INC
], ring
[TM_AGE
], ring
[TM_PIPR
],
488 static const char * const xive_tctx_ring_names
[] = {
489 "USER", "OS", "POOL", "PHYS",
492 void xive_tctx_pic_print_info(XiveTCTX
*tctx
, Monitor
*mon
)
494 int cpu_index
= tctx
->cs
? tctx
->cs
->cpu_index
: -1;
497 if (kvm_irqchip_in_kernel()) {
498 Error
*local_err
= NULL
;
500 kvmppc_xive_cpu_synchronize_state(tctx
, &local_err
);
502 error_report_err(local_err
);
507 monitor_printf(mon
, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR"
510 for (i
= 0; i
< XIVE_TM_RING_COUNT
; i
++) {
511 char *s
= xive_tctx_ring_print(&tctx
->regs
[i
* XIVE_TM_RING_SIZE
]);
512 monitor_printf(mon
, "CPU[%04x]: %4s %s\n", cpu_index
,
513 xive_tctx_ring_names
[i
], s
);
518 static void xive_tctx_reset(void *dev
)
520 XiveTCTX
*tctx
= XIVE_TCTX(dev
);
522 memset(tctx
->regs
, 0, sizeof(tctx
->regs
));
524 /* Set some defaults */
525 tctx
->regs
[TM_QW1_OS
+ TM_LSMFB
] = 0xFF;
526 tctx
->regs
[TM_QW1_OS
+ TM_ACK_CNT
] = 0xFF;
527 tctx
->regs
[TM_QW1_OS
+ TM_AGE
] = 0xFF;
530 * Initialize PIPR to 0xFF to avoid phantom interrupts when the
533 tctx
->regs
[TM_QW1_OS
+ TM_PIPR
] =
534 ipb_to_pipr(tctx
->regs
[TM_QW1_OS
+ TM_IPB
]);
535 tctx
->regs
[TM_QW3_HV_PHYS
+ TM_PIPR
] =
536 ipb_to_pipr(tctx
->regs
[TM_QW3_HV_PHYS
+ TM_IPB
]);
539 static void xive_tctx_realize(DeviceState
*dev
, Error
**errp
)
541 XiveTCTX
*tctx
= XIVE_TCTX(dev
);
545 Error
*local_err
= NULL
;
547 obj
= object_property_get_link(OBJECT(dev
), "cpu", &local_err
);
549 error_propagate(errp
, local_err
);
550 error_prepend(errp
, "required link 'cpu' not found: ");
554 cpu
= POWERPC_CPU(obj
);
558 switch (PPC_INPUT(env
)) {
559 case PPC_FLAGS_INPUT_POWER9
:
560 tctx
->output
= env
->irq_inputs
[POWER9_INPUT_INT
];
564 error_setg(errp
, "XIVE interrupt controller does not support "
565 "this CPU bus model");
569 /* Connect the presenter to the VCPU (required for CPU hotplug) */
570 if (kvm_irqchip_in_kernel()) {
571 kvmppc_xive_cpu_connect(tctx
, &local_err
);
573 error_propagate(errp
, local_err
);
578 qemu_register_reset(xive_tctx_reset
, dev
);
581 static void xive_tctx_unrealize(DeviceState
*dev
, Error
**errp
)
583 qemu_unregister_reset(xive_tctx_reset
, dev
);
586 static int vmstate_xive_tctx_pre_save(void *opaque
)
588 Error
*local_err
= NULL
;
590 if (kvm_irqchip_in_kernel()) {
591 kvmppc_xive_cpu_get_state(XIVE_TCTX(opaque
), &local_err
);
593 error_report_err(local_err
);
601 static const VMStateDescription vmstate_xive_tctx
= {
602 .name
= TYPE_XIVE_TCTX
,
604 .minimum_version_id
= 1,
605 .pre_save
= vmstate_xive_tctx_pre_save
,
606 .post_load
= NULL
, /* handled by the sPAPRxive model */
607 .fields
= (VMStateField
[]) {
608 VMSTATE_BUFFER(regs
, XiveTCTX
),
609 VMSTATE_END_OF_LIST()
613 static void xive_tctx_class_init(ObjectClass
*klass
, void *data
)
615 DeviceClass
*dc
= DEVICE_CLASS(klass
);
617 dc
->desc
= "XIVE Interrupt Thread Context";
618 dc
->realize
= xive_tctx_realize
;
619 dc
->unrealize
= xive_tctx_unrealize
;
620 dc
->vmsd
= &vmstate_xive_tctx
;
623 static const TypeInfo xive_tctx_info
= {
624 .name
= TYPE_XIVE_TCTX
,
625 .parent
= TYPE_DEVICE
,
626 .instance_size
= sizeof(XiveTCTX
),
627 .class_init
= xive_tctx_class_init
,
630 Object
*xive_tctx_create(Object
*cpu
, XiveRouter
*xrtr
, Error
**errp
)
632 Error
*local_err
= NULL
;
635 obj
= object_new(TYPE_XIVE_TCTX
);
636 object_property_add_child(cpu
, TYPE_XIVE_TCTX
, obj
, &error_abort
);
638 object_property_add_const_link(obj
, "cpu", cpu
, &error_abort
);
639 object_property_set_bool(obj
, true, "realized", &local_err
);
647 object_unparent(obj
);
648 error_propagate(errp
, local_err
);
656 static uint8_t xive_esb_set(uint8_t *pq
, uint8_t value
)
658 uint8_t old_pq
= *pq
& 0x3;
666 static bool xive_esb_trigger(uint8_t *pq
)
668 uint8_t old_pq
= *pq
& 0x3;
672 xive_esb_set(pq
, XIVE_ESB_PENDING
);
674 case XIVE_ESB_PENDING
:
675 case XIVE_ESB_QUEUED
:
676 xive_esb_set(pq
, XIVE_ESB_QUEUED
);
679 xive_esb_set(pq
, XIVE_ESB_OFF
);
682 g_assert_not_reached();
686 static bool xive_esb_eoi(uint8_t *pq
)
688 uint8_t old_pq
= *pq
& 0x3;
692 case XIVE_ESB_PENDING
:
693 xive_esb_set(pq
, XIVE_ESB_RESET
);
695 case XIVE_ESB_QUEUED
:
696 xive_esb_set(pq
, XIVE_ESB_PENDING
);
699 xive_esb_set(pq
, XIVE_ESB_OFF
);
702 g_assert_not_reached();
707 * XIVE Interrupt Source (or IVSE)
710 uint8_t xive_source_esb_get(XiveSource
*xsrc
, uint32_t srcno
)
712 assert(srcno
< xsrc
->nr_irqs
);
714 return xsrc
->status
[srcno
] & 0x3;
717 uint8_t xive_source_esb_set(XiveSource
*xsrc
, uint32_t srcno
, uint8_t pq
)
719 assert(srcno
< xsrc
->nr_irqs
);
721 return xive_esb_set(&xsrc
->status
[srcno
], pq
);
725 * Returns whether the event notification should be forwarded.
727 static bool xive_source_lsi_trigger(XiveSource
*xsrc
, uint32_t srcno
)
729 uint8_t old_pq
= xive_source_esb_get(xsrc
, srcno
);
731 xsrc
->status
[srcno
] |= XIVE_STATUS_ASSERTED
;
735 xive_source_esb_set(xsrc
, srcno
, XIVE_ESB_PENDING
);
743 * Returns whether the event notification should be forwarded.
745 static bool xive_source_esb_trigger(XiveSource
*xsrc
, uint32_t srcno
)
749 assert(srcno
< xsrc
->nr_irqs
);
751 ret
= xive_esb_trigger(&xsrc
->status
[srcno
]);
753 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
754 xive_source_esb_get(xsrc
, srcno
) == XIVE_ESB_QUEUED
) {
755 qemu_log_mask(LOG_GUEST_ERROR
,
756 "XIVE: queued an event on LSI IRQ %d\n", srcno
);
763 * Returns whether the event notification should be forwarded.
765 static bool xive_source_esb_eoi(XiveSource
*xsrc
, uint32_t srcno
)
769 assert(srcno
< xsrc
->nr_irqs
);
771 ret
= xive_esb_eoi(&xsrc
->status
[srcno
]);
774 * LSI sources do not set the Q bit but they can still be
775 * asserted, in which case we should forward a new event
778 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
779 xsrc
->status
[srcno
] & XIVE_STATUS_ASSERTED
) {
780 ret
= xive_source_lsi_trigger(xsrc
, srcno
);
787 * Forward the source event notification to the Router
789 static void xive_source_notify(XiveSource
*xsrc
, int srcno
)
791 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_GET_CLASS(xsrc
->xive
);
794 xnc
->notify(xsrc
->xive
, srcno
);
799 * In a two pages ESB MMIO setting, even page is the trigger page, odd
800 * page is for management
802 static inline bool addr_is_even(hwaddr addr
, uint32_t shift
)
804 return !((addr
>> shift
) & 1);
807 static inline bool xive_source_is_trigger_page(XiveSource
*xsrc
, hwaddr addr
)
809 return xive_source_esb_has_2page(xsrc
) &&
810 addr_is_even(addr
, xsrc
->esb_shift
- 1);
815 * Trigger page Management/EOI page
817 * ESB MMIO setting 2 pages 1 or 2 pages
819 * 0x000 .. 0x3FF -1 EOI and return 0|1
820 * 0x400 .. 0x7FF -1 EOI and return 0|1
821 * 0x800 .. 0xBFF -1 return PQ
822 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00
823 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01
824 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10
825 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11
827 static uint64_t xive_source_esb_read(void *opaque
, hwaddr addr
, unsigned size
)
829 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
830 uint32_t offset
= addr
& 0xFFF;
831 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
834 /* In a two pages ESB MMIO setting, trigger page should not be read */
835 if (xive_source_is_trigger_page(xsrc
, addr
)) {
836 qemu_log_mask(LOG_GUEST_ERROR
,
837 "XIVE: invalid load on IRQ %d trigger page at "
838 "0x%"HWADDR_PRIx
"\n", srcno
, addr
);
843 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
844 ret
= xive_source_esb_eoi(xsrc
, srcno
);
846 /* Forward the source event notification for routing */
848 xive_source_notify(xsrc
, srcno
);
852 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
853 ret
= xive_source_esb_get(xsrc
, srcno
);
856 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
857 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
858 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
859 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
860 ret
= xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
863 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB load addr %x\n",
872 * Trigger page Management/EOI page
874 * ESB MMIO setting 2 pages 1 or 2 pages
876 * 0x000 .. 0x3FF Trigger Trigger
877 * 0x400 .. 0x7FF Trigger EOI
878 * 0x800 .. 0xBFF Trigger undefined
879 * 0xC00 .. 0xCFF Trigger PQ=00
880 * 0xD00 .. 0xDFF Trigger PQ=01
881 * 0xE00 .. 0xDFF Trigger PQ=10
882 * 0xF00 .. 0xDFF Trigger PQ=11
884 static void xive_source_esb_write(void *opaque
, hwaddr addr
,
885 uint64_t value
, unsigned size
)
887 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
888 uint32_t offset
= addr
& 0xFFF;
889 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
892 /* In a two pages ESB MMIO setting, trigger page only triggers */
893 if (xive_source_is_trigger_page(xsrc
, addr
)) {
894 notify
= xive_source_esb_trigger(xsrc
, srcno
);
900 notify
= xive_source_esb_trigger(xsrc
, srcno
);
903 case XIVE_ESB_STORE_EOI
... XIVE_ESB_STORE_EOI
+ 0x3FF:
904 if (!(xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
)) {
905 qemu_log_mask(LOG_GUEST_ERROR
,
906 "XIVE: invalid Store EOI for IRQ %d\n", srcno
);
910 notify
= xive_source_esb_eoi(xsrc
, srcno
);
913 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
914 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
915 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
916 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
917 xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
921 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr %x\n",
927 /* Forward the source event notification for routing */
929 xive_source_notify(xsrc
, srcno
);
933 static const MemoryRegionOps xive_source_esb_ops
= {
934 .read
= xive_source_esb_read
,
935 .write
= xive_source_esb_write
,
936 .endianness
= DEVICE_BIG_ENDIAN
,
938 .min_access_size
= 8,
939 .max_access_size
= 8,
942 .min_access_size
= 8,
943 .max_access_size
= 8,
947 void xive_source_set_irq(void *opaque
, int srcno
, int val
)
949 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
952 if (xive_source_irq_is_lsi(xsrc
, srcno
)) {
954 notify
= xive_source_lsi_trigger(xsrc
, srcno
);
956 xsrc
->status
[srcno
] &= ~XIVE_STATUS_ASSERTED
;
960 notify
= xive_source_esb_trigger(xsrc
, srcno
);
964 /* Forward the source event notification for routing */
966 xive_source_notify(xsrc
, srcno
);
970 void xive_source_pic_print_info(XiveSource
*xsrc
, uint32_t offset
, Monitor
*mon
)
974 for (i
= 0; i
< xsrc
->nr_irqs
; i
++) {
975 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
977 if (pq
== XIVE_ESB_OFF
) {
981 monitor_printf(mon
, " %08x %s %c%c%c\n", i
+ offset
,
982 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
983 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
984 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
985 xsrc
->status
[i
] & XIVE_STATUS_ASSERTED
? 'A' : ' ');
989 static void xive_source_reset(void *dev
)
991 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
993 /* Do not clear the LSI bitmap */
995 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */
996 memset(xsrc
->status
, XIVE_ESB_OFF
, xsrc
->nr_irqs
);
999 static void xive_source_realize(DeviceState
*dev
, Error
**errp
)
1001 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
1003 Error
*local_err
= NULL
;
1005 obj
= object_property_get_link(OBJECT(dev
), "xive", &local_err
);
1007 error_propagate(errp
, local_err
);
1008 error_prepend(errp
, "required link 'xive' not found: ");
1012 xsrc
->xive
= XIVE_NOTIFIER(obj
);
1014 if (!xsrc
->nr_irqs
) {
1015 error_setg(errp
, "Number of interrupt needs to be greater than 0");
1019 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
1020 xsrc
->esb_shift
!= XIVE_ESB_4K_2PAGE
&&
1021 xsrc
->esb_shift
!= XIVE_ESB_64K
&&
1022 xsrc
->esb_shift
!= XIVE_ESB_64K_2PAGE
) {
1023 error_setg(errp
, "Invalid ESB shift setting");
1027 xsrc
->status
= g_malloc0(xsrc
->nr_irqs
);
1028 xsrc
->lsi_map
= bitmap_new(xsrc
->nr_irqs
);
1030 if (!kvm_irqchip_in_kernel()) {
1031 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
1032 &xive_source_esb_ops
, xsrc
, "xive.esb",
1033 (1ull << xsrc
->esb_shift
) * xsrc
->nr_irqs
);
1036 qemu_register_reset(xive_source_reset
, dev
);
1039 static const VMStateDescription vmstate_xive_source
= {
1040 .name
= TYPE_XIVE_SOURCE
,
1042 .minimum_version_id
= 1,
1043 .fields
= (VMStateField
[]) {
1044 VMSTATE_UINT32_EQUAL(nr_irqs
, XiveSource
, NULL
),
1045 VMSTATE_VBUFFER_UINT32(status
, XiveSource
, 1, NULL
, nr_irqs
),
1046 VMSTATE_END_OF_LIST()
1051 * The default XIVE interrupt source setting for the ESB MMIOs is two
1052 * 64k pages without Store EOI, to be in sync with KVM.
1054 static Property xive_source_properties
[] = {
1055 DEFINE_PROP_UINT64("flags", XiveSource
, esb_flags
, 0),
1056 DEFINE_PROP_UINT32("nr-irqs", XiveSource
, nr_irqs
, 0),
1057 DEFINE_PROP_UINT32("shift", XiveSource
, esb_shift
, XIVE_ESB_64K_2PAGE
),
1058 DEFINE_PROP_END_OF_LIST(),
1061 static void xive_source_class_init(ObjectClass
*klass
, void *data
)
1063 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1065 dc
->desc
= "XIVE Interrupt Source";
1066 dc
->props
= xive_source_properties
;
1067 dc
->realize
= xive_source_realize
;
1068 dc
->vmsd
= &vmstate_xive_source
;
1071 static const TypeInfo xive_source_info
= {
1072 .name
= TYPE_XIVE_SOURCE
,
1073 .parent
= TYPE_DEVICE
,
1074 .instance_size
= sizeof(XiveSource
),
1075 .class_init
= xive_source_class_init
,
1082 void xive_end_queue_pic_print_info(XiveEND
*end
, uint32_t width
, Monitor
*mon
)
1084 uint64_t qaddr_base
= xive_end_qaddr(end
);
1085 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1086 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1087 uint32_t qentries
= 1 << (qsize
+ 10);
1091 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
1093 monitor_printf(mon
, " [ ");
1094 qindex
= (qindex
- (width
- 1)) & (qentries
- 1);
1095 for (i
= 0; i
< width
; i
++) {
1096 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
1097 uint32_t qdata
= -1;
1099 if (dma_memory_read(&address_space_memory
, qaddr
, &qdata
,
1101 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to read EQ @0x%"
1102 HWADDR_PRIx
"\n", qaddr
);
1105 monitor_printf(mon
, "%s%08x ", i
== width
- 1 ? "^" : "",
1106 be32_to_cpu(qdata
));
1107 qindex
= (qindex
+ 1) & (qentries
- 1);
1111 void xive_end_pic_print_info(XiveEND
*end
, uint32_t end_idx
, Monitor
*mon
)
1113 uint64_t qaddr_base
= xive_end_qaddr(end
);
1114 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1115 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
1116 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1117 uint32_t qentries
= 1 << (qsize
+ 10);
1119 uint32_t nvt
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
1120 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
1122 if (!xive_end_is_valid(end
)) {
1126 monitor_printf(mon
, " %08x %c%c%c%c%c prio:%d nvt:%04x eq:@%08"PRIx64
1127 "% 6d/%5d ^%d", end_idx
,
1128 xive_end_is_valid(end
) ? 'v' : '-',
1129 xive_end_is_enqueue(end
) ? 'q' : '-',
1130 xive_end_is_notify(end
) ? 'n' : '-',
1131 xive_end_is_backlog(end
) ? 'b' : '-',
1132 xive_end_is_escalate(end
) ? 'e' : '-',
1133 priority
, nvt
, qaddr_base
, qindex
, qentries
, qgen
);
1135 xive_end_queue_pic_print_info(end
, 6, mon
);
1136 monitor_printf(mon
, "]\n");
1139 static void xive_end_enqueue(XiveEND
*end
, uint32_t data
)
1141 uint64_t qaddr_base
= xive_end_qaddr(end
);
1142 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1143 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1144 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
1146 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
1147 uint32_t qdata
= cpu_to_be32((qgen
<< 31) | (data
& 0x7fffffff));
1148 uint32_t qentries
= 1 << (qsize
+ 10);
1150 if (dma_memory_write(&address_space_memory
, qaddr
, &qdata
, sizeof(qdata
))) {
1151 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to write END data @0x%"
1152 HWADDR_PRIx
"\n", qaddr
);
1156 qindex
= (qindex
+ 1) & (qentries
- 1);
1159 end
->w1
= xive_set_field32(END_W1_GENERATION
, end
->w1
, qgen
);
1161 end
->w1
= xive_set_field32(END_W1_PAGE_OFF
, end
->w1
, qindex
);
1165 * XIVE Router (aka. Virtualization Controller or IVRE)
1168 int xive_router_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
1171 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1173 return xrc
->get_eas(xrtr
, eas_blk
, eas_idx
, eas
);
1176 int xive_router_get_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
1179 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1181 return xrc
->get_end(xrtr
, end_blk
, end_idx
, end
);
1184 int xive_router_write_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
1185 XiveEND
*end
, uint8_t word_number
)
1187 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1189 return xrc
->write_end(xrtr
, end_blk
, end_idx
, end
, word_number
);
1192 int xive_router_get_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
1195 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1197 return xrc
->get_nvt(xrtr
, nvt_blk
, nvt_idx
, nvt
);
1200 int xive_router_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
1201 XiveNVT
*nvt
, uint8_t word_number
)
1203 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1205 return xrc
->write_nvt(xrtr
, nvt_blk
, nvt_idx
, nvt
, word_number
);
1208 XiveTCTX
*xive_router_get_tctx(XiveRouter
*xrtr
, CPUState
*cs
)
1210 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1212 return xrc
->get_tctx(xrtr
, cs
);
1216 * By default on P9, the HW CAM line (23bits) is hardwired to :
1218 * 0x000||0b1||4Bit chip number||7Bit Thread number.
1220 * When the block grouping is enabled, the CAM line is changed to :
1222 * 4Bit chip number||0x001||7Bit Thread number.
1224 static uint32_t hw_cam_line(uint8_t chip_id
, uint8_t tid
)
1226 return 1 << 11 | (chip_id
& 0xf) << 7 | (tid
& 0x7f);
1229 static bool xive_presenter_tctx_match_hw(XiveTCTX
*tctx
,
1230 uint8_t nvt_blk
, uint32_t nvt_idx
)
1232 CPUPPCState
*env
= &POWERPC_CPU(tctx
->cs
)->env
;
1233 uint32_t pir
= env
->spr_cb
[SPR_PIR
].default_value
;
1235 return hw_cam_line((pir
>> 8) & 0xf, pir
& 0x7f) ==
1236 hw_cam_line(nvt_blk
, nvt_idx
);
1240 * The thread context register words are in big-endian format.
1242 static int xive_presenter_tctx_match(XiveTCTX
*tctx
, uint8_t format
,
1243 uint8_t nvt_blk
, uint32_t nvt_idx
,
1244 bool cam_ignore
, uint32_t logic_serv
)
1246 uint32_t cam
= xive_nvt_cam_line(nvt_blk
, nvt_idx
);
1247 uint32_t qw3w2
= xive_tctx_word2(&tctx
->regs
[TM_QW3_HV_PHYS
]);
1248 uint32_t qw2w2
= xive_tctx_word2(&tctx
->regs
[TM_QW2_HV_POOL
]);
1249 uint32_t qw1w2
= xive_tctx_word2(&tctx
->regs
[TM_QW1_OS
]);
1250 uint32_t qw0w2
= xive_tctx_word2(&tctx
->regs
[TM_QW0_USER
]);
1253 * TODO (PowerNV): ignore mode. The low order bits of the NVT
1254 * identifier are ignored in the "CAM" match.
1258 if (cam_ignore
== true) {
1260 * F=0 & i=1: Logical server notification (bits ignored at
1261 * the end of the NVT identifier)
1263 qemu_log_mask(LOG_UNIMP
, "XIVE: no support for LS NVT %x/%x\n",
1268 /* F=0 & i=0: Specific NVT notification */
1271 if ((be32_to_cpu(qw3w2
) & TM_QW3W2_VT
) &&
1272 xive_presenter_tctx_match_hw(tctx
, nvt_blk
, nvt_idx
)) {
1273 return TM_QW3_HV_PHYS
;
1277 if ((be32_to_cpu(qw2w2
) & TM_QW2W2_VP
) &&
1278 cam
== xive_get_field32(TM_QW2W2_POOL_CAM
, qw2w2
)) {
1279 return TM_QW2_HV_POOL
;
1283 if ((be32_to_cpu(qw1w2
) & TM_QW1W2_VO
) &&
1284 cam
== xive_get_field32(TM_QW1W2_OS_CAM
, qw1w2
)) {
1288 /* F=1 : User level Event-Based Branch (EBB) notification */
1291 if ((be32_to_cpu(qw1w2
) & TM_QW1W2_VO
) &&
1292 (cam
== xive_get_field32(TM_QW1W2_OS_CAM
, qw1w2
)) &&
1293 (be32_to_cpu(qw0w2
) & TM_QW0W2_VU
) &&
1294 (logic_serv
== xive_get_field32(TM_QW0W2_LOGIC_SERV
, qw0w2
))) {
1301 typedef struct XiveTCTXMatch
{
1306 static bool xive_presenter_match(XiveRouter
*xrtr
, uint8_t format
,
1307 uint8_t nvt_blk
, uint32_t nvt_idx
,
1308 bool cam_ignore
, uint8_t priority
,
1309 uint32_t logic_serv
, XiveTCTXMatch
*match
)
1314 * TODO (PowerNV): handle chip_id overwrite of block field for
1315 * hardwired CAM compares
1319 XiveTCTX
*tctx
= xive_router_get_tctx(xrtr
, cs
);
1323 * HW checks that the CPU is enabled in the Physical Thread
1324 * Enable Register (PTER).
1328 * Check the thread context CAM lines and record matches. We
1329 * will handle CPU exception delivery later
1331 ring
= xive_presenter_tctx_match(tctx
, format
, nvt_blk
, nvt_idx
,
1332 cam_ignore
, logic_serv
);
1334 * Save the context and follow on to catch duplicates, that we
1335 * don't support yet.
1339 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: already found a thread "
1340 "context NVT %x/%x\n", nvt_blk
, nvt_idx
);
1350 qemu_log_mask(LOG_UNIMP
, "XIVE: NVT %x/%x is not dispatched\n",
1359 * This is our simple Xive Presenter Engine model. It is merged in the
1360 * Router as it does not require an extra object.
1362 * It receives notification requests sent by the IVRE to find one
1363 * matching NVT (or more) dispatched on the processor threads. In case
1364 * of a single NVT notification, the process is abreviated and the
1365 * thread is signaled if a match is found. In case of a logical server
1366 * notification (bits ignored at the end of the NVT identifier), the
1367 * IVPE and IVRE select a winning thread using different filters. This
1368 * involves 2 or 3 exchanges on the PowerBus that the model does not
1371 * The parameters represent what is sent on the PowerBus
1373 static void xive_presenter_notify(XiveRouter
*xrtr
, uint8_t format
,
1374 uint8_t nvt_blk
, uint32_t nvt_idx
,
1375 bool cam_ignore
, uint8_t priority
,
1376 uint32_t logic_serv
)
1379 XiveTCTXMatch match
= { .tctx
= NULL
, .ring
= 0 };
1382 /* NVT cache lookup */
1383 if (xive_router_get_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
)) {
1384 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: no NVT %x/%x\n",
1389 if (!xive_nvt_is_valid(&nvt
)) {
1390 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVT %x/%x is invalid\n",
1395 found
= xive_presenter_match(xrtr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
1396 priority
, logic_serv
, &match
);
1398 ipb_update(&match
.tctx
->regs
[match
.ring
], priority
);
1399 xive_tctx_notify(match
.tctx
, match
.ring
);
1403 /* Record the IPB in the associated NVT structure */
1404 ipb_update((uint8_t *) &nvt
.w4
, priority
);
1405 xive_router_write_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
, 4);
1408 * If no matching NVT is dispatched on a HW thread :
1409 * - update the NVT structure if backlog is activated
1410 * - escalate (ESe PQ bits and EAS in w4-5) if escalation is
1416 * An END trigger can come from an event trigger (IPI or HW) or from
1417 * another chip. We don't model the PowerBus but the END trigger
1418 * message has the same parameters than in the function below.
1420 static void xive_router_end_notify(XiveRouter
*xrtr
, uint8_t end_blk
,
1421 uint32_t end_idx
, uint32_t end_data
)
1427 /* END cache lookup */
1428 if (xive_router_get_end(xrtr
, end_blk
, end_idx
, &end
)) {
1429 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
1434 if (!xive_end_is_valid(&end
)) {
1435 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
1440 if (xive_end_is_enqueue(&end
)) {
1441 xive_end_enqueue(&end
, end_data
);
1442 /* Enqueuing event data modifies the EQ toggle and index */
1443 xive_router_write_end(xrtr
, end_blk
, end_idx
, &end
, 1);
1447 * The W7 format depends on the F bit in W6. It defines the type
1448 * of the notification :
1450 * F=0 : single or multiple NVT notification
1451 * F=1 : User level Event-Based Branch (EBB) notification, no
1454 format
= xive_get_field32(END_W6_FORMAT_BIT
, end
.w6
);
1455 priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
.w7
);
1457 /* The END is masked */
1458 if (format
== 0 && priority
== 0xff) {
1463 * Check the END ESn (Event State Buffer for notification) for
1464 * even futher coalescing in the Router
1466 if (!xive_end_is_notify(&end
)) {
1467 uint8_t pq
= xive_get_field32(END_W1_ESn
, end
.w1
);
1468 bool notify
= xive_esb_trigger(&pq
);
1470 if (pq
!= xive_get_field32(END_W1_ESn
, end
.w1
)) {
1471 end
.w1
= xive_set_field32(END_W1_ESn
, end
.w1
, pq
);
1472 xive_router_write_end(xrtr
, end_blk
, end_idx
, &end
, 1);
1475 /* ESn[Q]=1 : end of notification */
1482 * Follows IVPE notification
1484 xive_presenter_notify(xrtr
, format
,
1485 xive_get_field32(END_W6_NVT_BLOCK
, end
.w6
),
1486 xive_get_field32(END_W6_NVT_INDEX
, end
.w6
),
1487 xive_get_field32(END_W7_F0_IGNORE
, end
.w7
),
1489 xive_get_field32(END_W7_F1_LOG_SERVER_ID
, end
.w7
));
1491 /* TODO: Auto EOI. */
1494 void xive_router_notify(XiveNotifier
*xn
, uint32_t lisn
)
1496 XiveRouter
*xrtr
= XIVE_ROUTER(xn
);
1497 uint8_t eas_blk
= XIVE_SRCNO_BLOCK(lisn
);
1498 uint32_t eas_idx
= XIVE_SRCNO_INDEX(lisn
);
1501 /* EAS cache lookup */
1502 if (xive_router_get_eas(xrtr
, eas_blk
, eas_idx
, &eas
)) {
1503 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN %x\n", lisn
);
1508 * The IVRE checks the State Bit Cache at this point. We skip the
1509 * SBC lookup because the state bits of the sources are modeled
1510 * internally in QEMU.
1513 if (!xive_eas_is_valid(&eas
)) {
1514 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid LISN %x\n", lisn
);
1518 if (xive_eas_is_masked(&eas
)) {
1519 /* Notification completed */
1524 * The event trigger becomes an END trigger
1526 xive_router_end_notify(xrtr
,
1527 xive_get_field64(EAS_END_BLOCK
, eas
.w
),
1528 xive_get_field64(EAS_END_INDEX
, eas
.w
),
1529 xive_get_field64(EAS_END_DATA
, eas
.w
));
1532 static void xive_router_class_init(ObjectClass
*klass
, void *data
)
1534 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1535 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_CLASS(klass
);
1537 dc
->desc
= "XIVE Router Engine";
1538 xnc
->notify
= xive_router_notify
;
1541 static const TypeInfo xive_router_info
= {
1542 .name
= TYPE_XIVE_ROUTER
,
1543 .parent
= TYPE_SYS_BUS_DEVICE
,
1545 .class_size
= sizeof(XiveRouterClass
),
1546 .class_init
= xive_router_class_init
,
1547 .interfaces
= (InterfaceInfo
[]) {
1548 { TYPE_XIVE_NOTIFIER
},
1553 void xive_eas_pic_print_info(XiveEAS
*eas
, uint32_t lisn
, Monitor
*mon
)
1555 if (!xive_eas_is_valid(eas
)) {
1559 monitor_printf(mon
, " %08x %s end:%02x/%04x data:%08x\n",
1560 lisn
, xive_eas_is_masked(eas
) ? "M" : " ",
1561 (uint8_t) xive_get_field64(EAS_END_BLOCK
, eas
->w
),
1562 (uint32_t) xive_get_field64(EAS_END_INDEX
, eas
->w
),
1563 (uint32_t) xive_get_field64(EAS_END_DATA
, eas
->w
));
1567 * END ESB MMIO loads
1569 static uint64_t xive_end_source_read(void *opaque
, hwaddr addr
, unsigned size
)
1571 XiveENDSource
*xsrc
= XIVE_END_SOURCE(opaque
);
1572 uint32_t offset
= addr
& 0xFFF;
1576 uint32_t end_esmask
;
1580 end_blk
= xsrc
->block_id
;
1581 end_idx
= addr
>> (xsrc
->esb_shift
+ 1);
1583 if (xive_router_get_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
)) {
1584 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
1589 if (!xive_end_is_valid(&end
)) {
1590 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
1595 end_esmask
= addr_is_even(addr
, xsrc
->esb_shift
) ? END_W1_ESn
: END_W1_ESe
;
1596 pq
= xive_get_field32(end_esmask
, end
.w1
);
1599 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
1600 ret
= xive_esb_eoi(&pq
);
1602 /* Forward the source event notification for routing ?? */
1605 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
1609 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
1610 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
1611 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
1612 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
1613 ret
= xive_esb_set(&pq
, (offset
>> 8) & 0x3);
1616 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid END ESB load addr %d\n",
1621 if (pq
!= xive_get_field32(end_esmask
, end
.w1
)) {
1622 end
.w1
= xive_set_field32(end_esmask
, end
.w1
, pq
);
1623 xive_router_write_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
, 1);
1630 * END ESB MMIO stores are invalid
1632 static void xive_end_source_write(void *opaque
, hwaddr addr
,
1633 uint64_t value
, unsigned size
)
1635 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr 0x%"
1636 HWADDR_PRIx
"\n", addr
);
1639 static const MemoryRegionOps xive_end_source_ops
= {
1640 .read
= xive_end_source_read
,
1641 .write
= xive_end_source_write
,
1642 .endianness
= DEVICE_BIG_ENDIAN
,
1644 .min_access_size
= 8,
1645 .max_access_size
= 8,
1648 .min_access_size
= 8,
1649 .max_access_size
= 8,
1653 static void xive_end_source_realize(DeviceState
*dev
, Error
**errp
)
1655 XiveENDSource
*xsrc
= XIVE_END_SOURCE(dev
);
1657 Error
*local_err
= NULL
;
1659 obj
= object_property_get_link(OBJECT(dev
), "xive", &local_err
);
1661 error_propagate(errp
, local_err
);
1662 error_prepend(errp
, "required link 'xive' not found: ");
1666 xsrc
->xrtr
= XIVE_ROUTER(obj
);
1668 if (!xsrc
->nr_ends
) {
1669 error_setg(errp
, "Number of interrupt needs to be greater than 0");
1673 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
1674 xsrc
->esb_shift
!= XIVE_ESB_64K
) {
1675 error_setg(errp
, "Invalid ESB shift setting");
1680 * Each END is assigned an even/odd pair of MMIO pages, the even page
1681 * manages the ESn field while the odd page manages the ESe field.
1683 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
1684 &xive_end_source_ops
, xsrc
, "xive.end",
1685 (1ull << (xsrc
->esb_shift
+ 1)) * xsrc
->nr_ends
);
1688 static Property xive_end_source_properties
[] = {
1689 DEFINE_PROP_UINT8("block-id", XiveENDSource
, block_id
, 0),
1690 DEFINE_PROP_UINT32("nr-ends", XiveENDSource
, nr_ends
, 0),
1691 DEFINE_PROP_UINT32("shift", XiveENDSource
, esb_shift
, XIVE_ESB_64K
),
1692 DEFINE_PROP_END_OF_LIST(),
1695 static void xive_end_source_class_init(ObjectClass
*klass
, void *data
)
1697 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1699 dc
->desc
= "XIVE END Source";
1700 dc
->props
= xive_end_source_properties
;
1701 dc
->realize
= xive_end_source_realize
;
1704 static const TypeInfo xive_end_source_info
= {
1705 .name
= TYPE_XIVE_END_SOURCE
,
1706 .parent
= TYPE_DEVICE
,
1707 .instance_size
= sizeof(XiveENDSource
),
1708 .class_init
= xive_end_source_class_init
,
1714 static const TypeInfo xive_notifier_info
= {
1715 .name
= TYPE_XIVE_NOTIFIER
,
1716 .parent
= TYPE_INTERFACE
,
1717 .class_size
= sizeof(XiveNotifierClass
),
1720 static void xive_register_types(void)
1722 type_register_static(&xive_source_info
);
1723 type_register_static(&xive_notifier_info
);
1724 type_register_static(&xive_router_info
);
1725 type_register_static(&xive_end_source_info
);
1726 type_register_static(&xive_tctx_info
);
1729 type_init(xive_register_types
)