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1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Gerd Hoffmann <kraxel@redhat.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "hw.h"
21 #include "pci.h"
22 #include "msi.h"
23 #include "qemu-timer.h"
24 #include "audiodev.h"
25 #include "intel-hda.h"
26 #include "intel-hda-defs.h"
27 #include "dma.h"
28
29 /* --------------------------------------------------------------------- */
30 /* hda bus */
31
32 static struct BusInfo hda_codec_bus_info = {
33 .name = "HDA",
34 .size = sizeof(HDACodecBus),
35 .props = (Property[]) {
36 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
37 DEFINE_PROP_END_OF_LIST()
38 }
39 };
40
41 void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus,
42 hda_codec_response_func response,
43 hda_codec_xfer_func xfer)
44 {
45 qbus_create_inplace(&bus->qbus, &hda_codec_bus_info, dev, NULL);
46 bus->response = response;
47 bus->xfer = xfer;
48 }
49
50 static int hda_codec_dev_init(DeviceState *qdev)
51 {
52 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus);
53 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
54 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
55
56 if (dev->cad == -1) {
57 dev->cad = bus->next_cad;
58 }
59 if (dev->cad >= 15) {
60 return -1;
61 }
62 bus->next_cad = dev->cad + 1;
63 return cdc->init(dev);
64 }
65
66 static int hda_codec_dev_exit(DeviceState *qdev)
67 {
68 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
69 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
70
71 if (cdc->exit) {
72 cdc->exit(dev);
73 }
74 return 0;
75 }
76
77 HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
78 {
79 DeviceState *qdev;
80 HDACodecDevice *cdev;
81
82 QTAILQ_FOREACH(qdev, &bus->qbus.children, sibling) {
83 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
84 if (cdev->cad == cad) {
85 return cdev;
86 }
87 }
88 return NULL;
89 }
90
91 void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
92 {
93 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
94 bus->response(dev, solicited, response);
95 }
96
97 bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
98 uint8_t *buf, uint32_t len)
99 {
100 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
101 return bus->xfer(dev, stnr, output, buf, len);
102 }
103
104 /* --------------------------------------------------------------------- */
105 /* intel hda emulation */
106
107 typedef struct IntelHDAStream IntelHDAStream;
108 typedef struct IntelHDAState IntelHDAState;
109 typedef struct IntelHDAReg IntelHDAReg;
110
111 typedef struct bpl {
112 uint64_t addr;
113 uint32_t len;
114 uint32_t flags;
115 } bpl;
116
117 struct IntelHDAStream {
118 /* registers */
119 uint32_t ctl;
120 uint32_t lpib;
121 uint32_t cbl;
122 uint32_t lvi;
123 uint32_t fmt;
124 uint32_t bdlp_lbase;
125 uint32_t bdlp_ubase;
126
127 /* state */
128 bpl *bpl;
129 uint32_t bentries;
130 uint32_t bsize, be, bp;
131 };
132
133 struct IntelHDAState {
134 PCIDevice pci;
135 const char *name;
136 HDACodecBus codecs;
137
138 /* registers */
139 uint32_t g_ctl;
140 uint32_t wake_en;
141 uint32_t state_sts;
142 uint32_t int_ctl;
143 uint32_t int_sts;
144 uint32_t wall_clk;
145
146 uint32_t corb_lbase;
147 uint32_t corb_ubase;
148 uint32_t corb_rp;
149 uint32_t corb_wp;
150 uint32_t corb_ctl;
151 uint32_t corb_sts;
152 uint32_t corb_size;
153
154 uint32_t rirb_lbase;
155 uint32_t rirb_ubase;
156 uint32_t rirb_wp;
157 uint32_t rirb_cnt;
158 uint32_t rirb_ctl;
159 uint32_t rirb_sts;
160 uint32_t rirb_size;
161
162 uint32_t dp_lbase;
163 uint32_t dp_ubase;
164
165 uint32_t icw;
166 uint32_t irr;
167 uint32_t ics;
168
169 /* streams */
170 IntelHDAStream st[8];
171
172 /* state */
173 MemoryRegion mmio;
174 uint32_t rirb_count;
175 int64_t wall_base_ns;
176
177 /* debug logging */
178 const IntelHDAReg *last_reg;
179 uint32_t last_val;
180 uint32_t last_write;
181 uint32_t last_sec;
182 uint32_t repeat_count;
183
184 /* properties */
185 uint32_t debug;
186 uint32_t msi;
187 };
188
189 struct IntelHDAReg {
190 const char *name; /* register name */
191 uint32_t size; /* size in bytes */
192 uint32_t reset; /* reset value */
193 uint32_t wmask; /* write mask */
194 uint32_t wclear; /* write 1 to clear bits */
195 uint32_t offset; /* location in IntelHDAState */
196 uint32_t shift; /* byte access entries for dwords */
197 uint32_t stream;
198 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
199 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
200 };
201
202 static void intel_hda_reset(DeviceState *dev);
203
204 /* --------------------------------------------------------------------- */
205
206 static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
207 {
208 target_phys_addr_t addr;
209
210 #if TARGET_PHYS_ADDR_BITS == 32
211 addr = lbase;
212 #else
213 addr = ubase;
214 addr <<= 32;
215 addr |= lbase;
216 #endif
217 return addr;
218 }
219
220 static void intel_hda_update_int_sts(IntelHDAState *d)
221 {
222 uint32_t sts = 0;
223 uint32_t i;
224
225 /* update controller status */
226 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
227 sts |= (1 << 30);
228 }
229 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
230 sts |= (1 << 30);
231 }
232 if (d->state_sts & d->wake_en) {
233 sts |= (1 << 30);
234 }
235
236 /* update stream status */
237 for (i = 0; i < 8; i++) {
238 /* buffer completion interrupt */
239 if (d->st[i].ctl & (1 << 26)) {
240 sts |= (1 << i);
241 }
242 }
243
244 /* update global status */
245 if (sts & d->int_ctl) {
246 sts |= (1 << 31);
247 }
248
249 d->int_sts = sts;
250 }
251
252 static void intel_hda_update_irq(IntelHDAState *d)
253 {
254 int msi = d->msi && msi_enabled(&d->pci);
255 int level;
256
257 intel_hda_update_int_sts(d);
258 if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) {
259 level = 1;
260 } else {
261 level = 0;
262 }
263 dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__,
264 level, msi ? "msi" : "intx");
265 if (msi) {
266 if (level) {
267 msi_notify(&d->pci, 0);
268 }
269 } else {
270 qemu_set_irq(d->pci.irq[0], level);
271 }
272 }
273
274 static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
275 {
276 uint32_t cad, nid, data;
277 HDACodecDevice *codec;
278 HDACodecDeviceClass *cdc;
279
280 cad = (verb >> 28) & 0x0f;
281 if (verb & (1 << 27)) {
282 /* indirect node addressing, not specified in HDA 1.0 */
283 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__);
284 return -1;
285 }
286 nid = (verb >> 20) & 0x7f;
287 data = verb & 0xfffff;
288
289 codec = hda_codec_find(&d->codecs, cad);
290 if (codec == NULL) {
291 dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
292 return -1;
293 }
294 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
295 cdc->command(codec, nid, data);
296 return 0;
297 }
298
299 static void intel_hda_corb_run(IntelHDAState *d)
300 {
301 target_phys_addr_t addr;
302 uint32_t rp, verb;
303
304 if (d->ics & ICH6_IRS_BUSY) {
305 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw);
306 intel_hda_send_command(d, d->icw);
307 return;
308 }
309
310 for (;;) {
311 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
312 dprint(d, 2, "%s: !run\n", __FUNCTION__);
313 return;
314 }
315 if ((d->corb_rp & 0xff) == d->corb_wp) {
316 dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__);
317 return;
318 }
319 if (d->rirb_count == d->rirb_cnt) {
320 dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__);
321 return;
322 }
323
324 rp = (d->corb_rp + 1) & 0xff;
325 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
326 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
327 d->corb_rp = rp;
328
329 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb);
330 intel_hda_send_command(d, verb);
331 }
332 }
333
334 static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
335 {
336 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
337 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
338 target_phys_addr_t addr;
339 uint32_t wp, ex;
340
341 if (d->ics & ICH6_IRS_BUSY) {
342 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
343 __FUNCTION__, response, dev->cad);
344 d->irr = response;
345 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
346 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
347 return;
348 }
349
350 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
351 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__);
352 return;
353 }
354
355 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
356 wp = (d->rirb_wp + 1) & 0xff;
357 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
358 stl_le_pci_dma(&d->pci, addr + 8*wp, response);
359 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex);
360 d->rirb_wp = wp;
361
362 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
363 __FUNCTION__, wp, response, ex);
364
365 d->rirb_count++;
366 if (d->rirb_count == d->rirb_cnt) {
367 dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count);
368 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
369 d->rirb_sts |= ICH6_RBSTS_IRQ;
370 intel_hda_update_irq(d);
371 }
372 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
373 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__,
374 d->rirb_count, d->rirb_cnt);
375 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
376 d->rirb_sts |= ICH6_RBSTS_IRQ;
377 intel_hda_update_irq(d);
378 }
379 }
380 }
381
382 static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
383 uint8_t *buf, uint32_t len)
384 {
385 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
386 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
387 target_phys_addr_t addr;
388 uint32_t s, copy, left;
389 IntelHDAStream *st;
390 bool irq = false;
391
392 st = output ? d->st + 4 : d->st;
393 for (s = 0; s < 4; s++) {
394 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
395 st = st + s;
396 break;
397 }
398 }
399 if (s == 4) {
400 return false;
401 }
402 if (st->bpl == NULL) {
403 return false;
404 }
405 if (st->ctl & (1 << 26)) {
406 /*
407 * Wait with the next DMA xfer until the guest
408 * has acked the buffer completion interrupt
409 */
410 return false;
411 }
412
413 left = len;
414 while (left > 0) {
415 copy = left;
416 if (copy > st->bsize - st->lpib)
417 copy = st->bsize - st->lpib;
418 if (copy > st->bpl[st->be].len - st->bp)
419 copy = st->bpl[st->be].len - st->bp;
420
421 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
422 st->be, st->bp, st->bpl[st->be].len, copy);
423
424 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output);
425 st->lpib += copy;
426 st->bp += copy;
427 buf += copy;
428 left -= copy;
429
430 if (st->bpl[st->be].len == st->bp) {
431 /* bpl entry filled */
432 if (st->bpl[st->be].flags & 0x01) {
433 irq = true;
434 }
435 st->bp = 0;
436 st->be++;
437 if (st->be == st->bentries) {
438 /* bpl wrap around */
439 st->be = 0;
440 st->lpib = 0;
441 }
442 }
443 }
444 if (d->dp_lbase & 0x01) {
445 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
446 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
447 }
448 dprint(d, 3, "dma: --\n");
449
450 if (irq) {
451 st->ctl |= (1 << 26); /* buffer completion interrupt */
452 intel_hda_update_irq(d);
453 }
454 return true;
455 }
456
457 static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
458 {
459 target_phys_addr_t addr;
460 uint8_t buf[16];
461 uint32_t i;
462
463 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
464 st->bentries = st->lvi +1;
465 g_free(st->bpl);
466 st->bpl = g_malloc(sizeof(bpl) * st->bentries);
467 for (i = 0; i < st->bentries; i++, addr += 16) {
468 pci_dma_read(&d->pci, addr, buf, 16);
469 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
470 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
471 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
472 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
473 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
474 }
475
476 st->bsize = st->cbl;
477 st->lpib = 0;
478 st->be = 0;
479 st->bp = 0;
480 }
481
482 static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
483 {
484 DeviceState *qdev;
485 HDACodecDevice *cdev;
486
487 QTAILQ_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
488 HDACodecDeviceClass *cdc;
489
490 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
491 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
492 if (cdc->stream) {
493 cdc->stream(cdev, stream, running, output);
494 }
495 }
496 }
497
498 /* --------------------------------------------------------------------- */
499
500 static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
501 {
502 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
503 intel_hda_reset(&d->pci.qdev);
504 }
505 }
506
507 static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
508 {
509 intel_hda_update_irq(d);
510 }
511
512 static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
513 {
514 intel_hda_update_irq(d);
515 }
516
517 static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
518 {
519 intel_hda_update_irq(d);
520 }
521
522 static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
523 {
524 int64_t ns;
525
526 ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns;
527 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
528 }
529
530 static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
531 {
532 intel_hda_corb_run(d);
533 }
534
535 static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
536 {
537 intel_hda_corb_run(d);
538 }
539
540 static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
541 {
542 if (d->rirb_wp & ICH6_RIRBWP_RST) {
543 d->rirb_wp = 0;
544 }
545 }
546
547 static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
548 {
549 intel_hda_update_irq(d);
550
551 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
552 /* cleared ICH6_RBSTS_IRQ */
553 d->rirb_count = 0;
554 intel_hda_corb_run(d);
555 }
556 }
557
558 static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
559 {
560 if (d->ics & ICH6_IRS_BUSY) {
561 intel_hda_corb_run(d);
562 }
563 }
564
565 static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
566 {
567 bool output = reg->stream >= 4;
568 IntelHDAStream *st = d->st + reg->stream;
569
570 if (st->ctl & 0x01) {
571 /* reset */
572 dprint(d, 1, "st #%d: reset\n", reg->stream);
573 st->ctl = 0;
574 }
575 if ((st->ctl & 0x02) != (old & 0x02)) {
576 uint32_t stnr = (st->ctl >> 20) & 0x0f;
577 /* run bit flipped */
578 if (st->ctl & 0x02) {
579 /* start */
580 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
581 reg->stream, stnr, st->cbl);
582 intel_hda_parse_bdl(d, st);
583 intel_hda_notify_codecs(d, stnr, true, output);
584 } else {
585 /* stop */
586 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
587 intel_hda_notify_codecs(d, stnr, false, output);
588 }
589 }
590 intel_hda_update_irq(d);
591 }
592
593 /* --------------------------------------------------------------------- */
594
595 #define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
596
597 static const struct IntelHDAReg regtab[] = {
598 /* global */
599 [ ICH6_REG_GCAP ] = {
600 .name = "GCAP",
601 .size = 2,
602 .reset = 0x4401,
603 },
604 [ ICH6_REG_VMIN ] = {
605 .name = "VMIN",
606 .size = 1,
607 },
608 [ ICH6_REG_VMAJ ] = {
609 .name = "VMAJ",
610 .size = 1,
611 .reset = 1,
612 },
613 [ ICH6_REG_OUTPAY ] = {
614 .name = "OUTPAY",
615 .size = 2,
616 .reset = 0x3c,
617 },
618 [ ICH6_REG_INPAY ] = {
619 .name = "INPAY",
620 .size = 2,
621 .reset = 0x1d,
622 },
623 [ ICH6_REG_GCTL ] = {
624 .name = "GCTL",
625 .size = 4,
626 .wmask = 0x0103,
627 .offset = offsetof(IntelHDAState, g_ctl),
628 .whandler = intel_hda_set_g_ctl,
629 },
630 [ ICH6_REG_WAKEEN ] = {
631 .name = "WAKEEN",
632 .size = 2,
633 .wmask = 0x7fff,
634 .offset = offsetof(IntelHDAState, wake_en),
635 .whandler = intel_hda_set_wake_en,
636 },
637 [ ICH6_REG_STATESTS ] = {
638 .name = "STATESTS",
639 .size = 2,
640 .wmask = 0x7fff,
641 .wclear = 0x7fff,
642 .offset = offsetof(IntelHDAState, state_sts),
643 .whandler = intel_hda_set_state_sts,
644 },
645
646 /* interrupts */
647 [ ICH6_REG_INTCTL ] = {
648 .name = "INTCTL",
649 .size = 4,
650 .wmask = 0xc00000ff,
651 .offset = offsetof(IntelHDAState, int_ctl),
652 .whandler = intel_hda_set_int_ctl,
653 },
654 [ ICH6_REG_INTSTS ] = {
655 .name = "INTSTS",
656 .size = 4,
657 .wmask = 0xc00000ff,
658 .wclear = 0xc00000ff,
659 .offset = offsetof(IntelHDAState, int_sts),
660 },
661
662 /* misc */
663 [ ICH6_REG_WALLCLK ] = {
664 .name = "WALLCLK",
665 .size = 4,
666 .offset = offsetof(IntelHDAState, wall_clk),
667 .rhandler = intel_hda_get_wall_clk,
668 },
669 [ ICH6_REG_WALLCLK + 0x2000 ] = {
670 .name = "WALLCLK(alias)",
671 .size = 4,
672 .offset = offsetof(IntelHDAState, wall_clk),
673 .rhandler = intel_hda_get_wall_clk,
674 },
675
676 /* dma engine */
677 [ ICH6_REG_CORBLBASE ] = {
678 .name = "CORBLBASE",
679 .size = 4,
680 .wmask = 0xffffff80,
681 .offset = offsetof(IntelHDAState, corb_lbase),
682 },
683 [ ICH6_REG_CORBUBASE ] = {
684 .name = "CORBUBASE",
685 .size = 4,
686 .wmask = 0xffffffff,
687 .offset = offsetof(IntelHDAState, corb_ubase),
688 },
689 [ ICH6_REG_CORBWP ] = {
690 .name = "CORBWP",
691 .size = 2,
692 .wmask = 0xff,
693 .offset = offsetof(IntelHDAState, corb_wp),
694 .whandler = intel_hda_set_corb_wp,
695 },
696 [ ICH6_REG_CORBRP ] = {
697 .name = "CORBRP",
698 .size = 2,
699 .wmask = 0x80ff,
700 .offset = offsetof(IntelHDAState, corb_rp),
701 },
702 [ ICH6_REG_CORBCTL ] = {
703 .name = "CORBCTL",
704 .size = 1,
705 .wmask = 0x03,
706 .offset = offsetof(IntelHDAState, corb_ctl),
707 .whandler = intel_hda_set_corb_ctl,
708 },
709 [ ICH6_REG_CORBSTS ] = {
710 .name = "CORBSTS",
711 .size = 1,
712 .wmask = 0x01,
713 .wclear = 0x01,
714 .offset = offsetof(IntelHDAState, corb_sts),
715 },
716 [ ICH6_REG_CORBSIZE ] = {
717 .name = "CORBSIZE",
718 .size = 1,
719 .reset = 0x42,
720 .offset = offsetof(IntelHDAState, corb_size),
721 },
722 [ ICH6_REG_RIRBLBASE ] = {
723 .name = "RIRBLBASE",
724 .size = 4,
725 .wmask = 0xffffff80,
726 .offset = offsetof(IntelHDAState, rirb_lbase),
727 },
728 [ ICH6_REG_RIRBUBASE ] = {
729 .name = "RIRBUBASE",
730 .size = 4,
731 .wmask = 0xffffffff,
732 .offset = offsetof(IntelHDAState, rirb_ubase),
733 },
734 [ ICH6_REG_RIRBWP ] = {
735 .name = "RIRBWP",
736 .size = 2,
737 .wmask = 0x8000,
738 .offset = offsetof(IntelHDAState, rirb_wp),
739 .whandler = intel_hda_set_rirb_wp,
740 },
741 [ ICH6_REG_RINTCNT ] = {
742 .name = "RINTCNT",
743 .size = 2,
744 .wmask = 0xff,
745 .offset = offsetof(IntelHDAState, rirb_cnt),
746 },
747 [ ICH6_REG_RIRBCTL ] = {
748 .name = "RIRBCTL",
749 .size = 1,
750 .wmask = 0x07,
751 .offset = offsetof(IntelHDAState, rirb_ctl),
752 },
753 [ ICH6_REG_RIRBSTS ] = {
754 .name = "RIRBSTS",
755 .size = 1,
756 .wmask = 0x05,
757 .wclear = 0x05,
758 .offset = offsetof(IntelHDAState, rirb_sts),
759 .whandler = intel_hda_set_rirb_sts,
760 },
761 [ ICH6_REG_RIRBSIZE ] = {
762 .name = "RIRBSIZE",
763 .size = 1,
764 .reset = 0x42,
765 .offset = offsetof(IntelHDAState, rirb_size),
766 },
767
768 [ ICH6_REG_DPLBASE ] = {
769 .name = "DPLBASE",
770 .size = 4,
771 .wmask = 0xffffff81,
772 .offset = offsetof(IntelHDAState, dp_lbase),
773 },
774 [ ICH6_REG_DPUBASE ] = {
775 .name = "DPUBASE",
776 .size = 4,
777 .wmask = 0xffffffff,
778 .offset = offsetof(IntelHDAState, dp_ubase),
779 },
780
781 [ ICH6_REG_IC ] = {
782 .name = "ICW",
783 .size = 4,
784 .wmask = 0xffffffff,
785 .offset = offsetof(IntelHDAState, icw),
786 },
787 [ ICH6_REG_IR ] = {
788 .name = "IRR",
789 .size = 4,
790 .offset = offsetof(IntelHDAState, irr),
791 },
792 [ ICH6_REG_IRS ] = {
793 .name = "ICS",
794 .size = 2,
795 .wmask = 0x0003,
796 .wclear = 0x0002,
797 .offset = offsetof(IntelHDAState, ics),
798 .whandler = intel_hda_set_ics,
799 },
800
801 #define HDA_STREAM(_t, _i) \
802 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
803 .stream = _i, \
804 .name = _t stringify(_i) " CTL", \
805 .size = 4, \
806 .wmask = 0x1cff001f, \
807 .offset = offsetof(IntelHDAState, st[_i].ctl), \
808 .whandler = intel_hda_set_st_ctl, \
809 }, \
810 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
811 .stream = _i, \
812 .name = _t stringify(_i) " CTL(stnr)", \
813 .size = 1, \
814 .shift = 16, \
815 .wmask = 0x00ff0000, \
816 .offset = offsetof(IntelHDAState, st[_i].ctl), \
817 .whandler = intel_hda_set_st_ctl, \
818 }, \
819 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
820 .stream = _i, \
821 .name = _t stringify(_i) " CTL(sts)", \
822 .size = 1, \
823 .shift = 24, \
824 .wmask = 0x1c000000, \
825 .wclear = 0x1c000000, \
826 .offset = offsetof(IntelHDAState, st[_i].ctl), \
827 .whandler = intel_hda_set_st_ctl, \
828 }, \
829 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
830 .stream = _i, \
831 .name = _t stringify(_i) " LPIB", \
832 .size = 4, \
833 .offset = offsetof(IntelHDAState, st[_i].lpib), \
834 }, \
835 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
836 .stream = _i, \
837 .name = _t stringify(_i) " LPIB(alias)", \
838 .size = 4, \
839 .offset = offsetof(IntelHDAState, st[_i].lpib), \
840 }, \
841 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
842 .stream = _i, \
843 .name = _t stringify(_i) " CBL", \
844 .size = 4, \
845 .wmask = 0xffffffff, \
846 .offset = offsetof(IntelHDAState, st[_i].cbl), \
847 }, \
848 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
849 .stream = _i, \
850 .name = _t stringify(_i) " LVI", \
851 .size = 2, \
852 .wmask = 0x00ff, \
853 .offset = offsetof(IntelHDAState, st[_i].lvi), \
854 }, \
855 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
856 .stream = _i, \
857 .name = _t stringify(_i) " FIFOS", \
858 .size = 2, \
859 .reset = HDA_BUFFER_SIZE, \
860 }, \
861 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
862 .stream = _i, \
863 .name = _t stringify(_i) " FMT", \
864 .size = 2, \
865 .wmask = 0x7f7f, \
866 .offset = offsetof(IntelHDAState, st[_i].fmt), \
867 }, \
868 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
869 .stream = _i, \
870 .name = _t stringify(_i) " BDLPL", \
871 .size = 4, \
872 .wmask = 0xffffff80, \
873 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
874 }, \
875 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
876 .stream = _i, \
877 .name = _t stringify(_i) " BDLPU", \
878 .size = 4, \
879 .wmask = 0xffffffff, \
880 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
881 }, \
882
883 HDA_STREAM("IN", 0)
884 HDA_STREAM("IN", 1)
885 HDA_STREAM("IN", 2)
886 HDA_STREAM("IN", 3)
887
888 HDA_STREAM("OUT", 4)
889 HDA_STREAM("OUT", 5)
890 HDA_STREAM("OUT", 6)
891 HDA_STREAM("OUT", 7)
892
893 };
894
895 static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr)
896 {
897 const IntelHDAReg *reg;
898
899 if (addr >= sizeof(regtab)/sizeof(regtab[0])) {
900 goto noreg;
901 }
902 reg = regtab+addr;
903 if (reg->name == NULL) {
904 goto noreg;
905 }
906 return reg;
907
908 noreg:
909 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
910 return NULL;
911 }
912
913 static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
914 {
915 uint8_t *addr = (void*)d;
916
917 addr += reg->offset;
918 return (uint32_t*)addr;
919 }
920
921 static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
922 uint32_t wmask)
923 {
924 uint32_t *addr;
925 uint32_t old;
926
927 if (!reg) {
928 return;
929 }
930
931 if (d->debug) {
932 time_t now = time(NULL);
933 if (d->last_write && d->last_reg == reg && d->last_val == val) {
934 d->repeat_count++;
935 if (d->last_sec != now) {
936 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
937 d->last_sec = now;
938 d->repeat_count = 0;
939 }
940 } else {
941 if (d->repeat_count) {
942 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
943 }
944 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
945 d->last_write = 1;
946 d->last_reg = reg;
947 d->last_val = val;
948 d->last_sec = now;
949 d->repeat_count = 0;
950 }
951 }
952 assert(reg->offset != 0);
953
954 addr = intel_hda_reg_addr(d, reg);
955 old = *addr;
956
957 if (reg->shift) {
958 val <<= reg->shift;
959 wmask <<= reg->shift;
960 }
961 wmask &= reg->wmask;
962 *addr &= ~wmask;
963 *addr |= wmask & val;
964 *addr &= ~(val & reg->wclear);
965
966 if (reg->whandler) {
967 reg->whandler(d, reg, old);
968 }
969 }
970
971 static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
972 uint32_t rmask)
973 {
974 uint32_t *addr, ret;
975
976 if (!reg) {
977 return 0;
978 }
979
980 if (reg->rhandler) {
981 reg->rhandler(d, reg);
982 }
983
984 if (reg->offset == 0) {
985 /* constant read-only register */
986 ret = reg->reset;
987 } else {
988 addr = intel_hda_reg_addr(d, reg);
989 ret = *addr;
990 if (reg->shift) {
991 ret >>= reg->shift;
992 }
993 ret &= rmask;
994 }
995 if (d->debug) {
996 time_t now = time(NULL);
997 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
998 d->repeat_count++;
999 if (d->last_sec != now) {
1000 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1001 d->last_sec = now;
1002 d->repeat_count = 0;
1003 }
1004 } else {
1005 if (d->repeat_count) {
1006 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1007 }
1008 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1009 d->last_write = 0;
1010 d->last_reg = reg;
1011 d->last_val = ret;
1012 d->last_sec = now;
1013 d->repeat_count = 0;
1014 }
1015 }
1016 return ret;
1017 }
1018
1019 static void intel_hda_regs_reset(IntelHDAState *d)
1020 {
1021 uint32_t *addr;
1022 int i;
1023
1024 for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) {
1025 if (regtab[i].name == NULL) {
1026 continue;
1027 }
1028 if (regtab[i].offset == 0) {
1029 continue;
1030 }
1031 addr = intel_hda_reg_addr(d, regtab + i);
1032 *addr = regtab[i].reset;
1033 }
1034 }
1035
1036 /* --------------------------------------------------------------------- */
1037
1038 static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1039 {
1040 IntelHDAState *d = opaque;
1041 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1042
1043 intel_hda_reg_write(d, reg, val, 0xff);
1044 }
1045
1046 static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1047 {
1048 IntelHDAState *d = opaque;
1049 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1050
1051 intel_hda_reg_write(d, reg, val, 0xffff);
1052 }
1053
1054 static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1055 {
1056 IntelHDAState *d = opaque;
1057 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1058
1059 intel_hda_reg_write(d, reg, val, 0xffffffff);
1060 }
1061
1062 static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr)
1063 {
1064 IntelHDAState *d = opaque;
1065 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1066
1067 return intel_hda_reg_read(d, reg, 0xff);
1068 }
1069
1070 static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr)
1071 {
1072 IntelHDAState *d = opaque;
1073 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1074
1075 return intel_hda_reg_read(d, reg, 0xffff);
1076 }
1077
1078 static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr)
1079 {
1080 IntelHDAState *d = opaque;
1081 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1082
1083 return intel_hda_reg_read(d, reg, 0xffffffff);
1084 }
1085
1086 static const MemoryRegionOps intel_hda_mmio_ops = {
1087 .old_mmio = {
1088 .read = {
1089 intel_hda_mmio_readb,
1090 intel_hda_mmio_readw,
1091 intel_hda_mmio_readl,
1092 },
1093 .write = {
1094 intel_hda_mmio_writeb,
1095 intel_hda_mmio_writew,
1096 intel_hda_mmio_writel,
1097 },
1098 },
1099 .endianness = DEVICE_NATIVE_ENDIAN,
1100 };
1101
1102 /* --------------------------------------------------------------------- */
1103
1104 static void intel_hda_reset(DeviceState *dev)
1105 {
1106 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev);
1107 DeviceState *qdev;
1108 HDACodecDevice *cdev;
1109
1110 intel_hda_regs_reset(d);
1111 d->wall_base_ns = qemu_get_clock_ns(vm_clock);
1112
1113 /* reset codecs */
1114 QTAILQ_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
1115 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
1116 device_reset(DEVICE(cdev));
1117 d->state_sts |= (1 << cdev->cad);
1118 }
1119 intel_hda_update_irq(d);
1120 }
1121
1122 static int intel_hda_init(PCIDevice *pci)
1123 {
1124 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1125 uint8_t *conf = d->pci.config;
1126
1127 d->name = object_get_typename(OBJECT(d));
1128
1129 pci_config_set_interrupt_pin(conf, 1);
1130
1131 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1132 conf[0x40] = 0x01;
1133
1134 memory_region_init_io(&d->mmio, &intel_hda_mmio_ops, d,
1135 "intel-hda", 0x4000);
1136 pci_register_bar(&d->pci, 0, 0, &d->mmio);
1137 if (d->msi) {
1138 msi_init(&d->pci, 0x50, 1, true, false);
1139 }
1140
1141 hda_codec_bus_init(&d->pci.qdev, &d->codecs,
1142 intel_hda_response, intel_hda_xfer);
1143
1144 return 0;
1145 }
1146
1147 static int intel_hda_exit(PCIDevice *pci)
1148 {
1149 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1150
1151 msi_uninit(&d->pci);
1152 memory_region_destroy(&d->mmio);
1153 return 0;
1154 }
1155
1156 static void intel_hda_write_config(PCIDevice *pci, uint32_t addr,
1157 uint32_t val, int len)
1158 {
1159 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1160
1161 pci_default_write_config(pci, addr, val, len);
1162 if (d->msi) {
1163 msi_write_config(pci, addr, val, len);
1164 }
1165 }
1166
1167 static int intel_hda_post_load(void *opaque, int version)
1168 {
1169 IntelHDAState* d = opaque;
1170 int i;
1171
1172 dprint(d, 1, "%s\n", __FUNCTION__);
1173 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1174 if (d->st[i].ctl & 0x02) {
1175 intel_hda_parse_bdl(d, &d->st[i]);
1176 }
1177 }
1178 intel_hda_update_irq(d);
1179 return 0;
1180 }
1181
1182 static const VMStateDescription vmstate_intel_hda_stream = {
1183 .name = "intel-hda-stream",
1184 .version_id = 1,
1185 .fields = (VMStateField []) {
1186 VMSTATE_UINT32(ctl, IntelHDAStream),
1187 VMSTATE_UINT32(lpib, IntelHDAStream),
1188 VMSTATE_UINT32(cbl, IntelHDAStream),
1189 VMSTATE_UINT32(lvi, IntelHDAStream),
1190 VMSTATE_UINT32(fmt, IntelHDAStream),
1191 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1192 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1193 VMSTATE_END_OF_LIST()
1194 }
1195 };
1196
1197 static const VMStateDescription vmstate_intel_hda = {
1198 .name = "intel-hda",
1199 .version_id = 1,
1200 .post_load = intel_hda_post_load,
1201 .fields = (VMStateField []) {
1202 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1203
1204 /* registers */
1205 VMSTATE_UINT32(g_ctl, IntelHDAState),
1206 VMSTATE_UINT32(wake_en, IntelHDAState),
1207 VMSTATE_UINT32(state_sts, IntelHDAState),
1208 VMSTATE_UINT32(int_ctl, IntelHDAState),
1209 VMSTATE_UINT32(int_sts, IntelHDAState),
1210 VMSTATE_UINT32(wall_clk, IntelHDAState),
1211 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1212 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1213 VMSTATE_UINT32(corb_rp, IntelHDAState),
1214 VMSTATE_UINT32(corb_wp, IntelHDAState),
1215 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1216 VMSTATE_UINT32(corb_sts, IntelHDAState),
1217 VMSTATE_UINT32(corb_size, IntelHDAState),
1218 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1219 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1220 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1221 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1222 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1223 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1224 VMSTATE_UINT32(rirb_size, IntelHDAState),
1225 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1226 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1227 VMSTATE_UINT32(icw, IntelHDAState),
1228 VMSTATE_UINT32(irr, IntelHDAState),
1229 VMSTATE_UINT32(ics, IntelHDAState),
1230 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1231 vmstate_intel_hda_stream,
1232 IntelHDAStream),
1233
1234 /* additional state info */
1235 VMSTATE_UINT32(rirb_count, IntelHDAState),
1236 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1237
1238 VMSTATE_END_OF_LIST()
1239 }
1240 };
1241
1242 static Property intel_hda_properties[] = {
1243 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1244 DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1),
1245 DEFINE_PROP_END_OF_LIST(),
1246 };
1247
1248 static void intel_hda_class_init(ObjectClass *klass, void *data)
1249 {
1250 DeviceClass *dc = DEVICE_CLASS(klass);
1251 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1252
1253 k->init = intel_hda_init;
1254 k->exit = intel_hda_exit;
1255 k->config_write = intel_hda_write_config;
1256 k->vendor_id = PCI_VENDOR_ID_INTEL;
1257 k->device_id = 0x2668;
1258 k->revision = 1;
1259 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
1260 dc->desc = "Intel HD Audio Controller";
1261 dc->reset = intel_hda_reset;
1262 dc->vmsd = &vmstate_intel_hda;
1263 dc->props = intel_hda_properties;
1264 }
1265
1266 static TypeInfo intel_hda_info = {
1267 .name = "intel-hda",
1268 .parent = TYPE_PCI_DEVICE,
1269 .instance_size = sizeof(IntelHDAState),
1270 .class_init = intel_hda_class_init,
1271 };
1272
1273 static void hda_codec_device_class_init(ObjectClass *klass, void *data)
1274 {
1275 DeviceClass *k = DEVICE_CLASS(klass);
1276 k->init = hda_codec_dev_init;
1277 k->exit = hda_codec_dev_exit;
1278 k->bus_info = &hda_codec_bus_info;
1279 }
1280
1281 static TypeInfo hda_codec_device_type_info = {
1282 .name = TYPE_HDA_CODEC_DEVICE,
1283 .parent = TYPE_DEVICE,
1284 .instance_size = sizeof(HDACodecDevice),
1285 .abstract = true,
1286 .class_size = sizeof(HDACodecDeviceClass),
1287 .class_init = hda_codec_device_class_init,
1288 };
1289
1290 static void intel_hda_register_types(void)
1291 {
1292 type_register_static(&intel_hda_info);
1293 type_register_static(&hda_codec_device_type_info);
1294 }
1295
1296 type_init(intel_hda_register_types)
1297
1298 /*
1299 * create intel hda controller with codec attached to it,
1300 * so '-soundhw hda' works.
1301 */
1302 int intel_hda_and_codec_init(PCIBus *bus)
1303 {
1304 PCIDevice *controller;
1305 BusState *hdabus;
1306 DeviceState *codec;
1307
1308 controller = pci_create_simple(bus, -1, "intel-hda");
1309 hdabus = QLIST_FIRST(&controller->qdev.child_bus);
1310 codec = qdev_create(hdabus, "hda-duplex");
1311 qdev_init_nofail(codec);
1312 return 0;
1313 }
1314
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