hw/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "hw.h"
  24 #include "pc.h"
  25 #include "apic.h"
  26 #include "ioapic.h"
  27 #include "qemu-timer.h"
  28 #include "host-utils.h"
  29 #include "sysbus.h"
  30
  31 //#define DEBUG_IOAPIC
  32
  33 #ifdef DEBUG_IOAPIC
  34 #define DPRINTF(fmt, ...)                                       \
  35     do { printf("ioapic: " fmt , ## __VA_ARGS__); } while (0)
  36 #else
  37 #define DPRINTF(fmt, ...)
  38 #endif
  39
  40 #define MAX_IOAPICS                     1
  41
  42 #define IOAPIC_LVT_MASKED               (1 << 16)
  43 #define IOAPIC_LVT_REMOTE_IRR           (1 << 14)
  44
  45 #define IOAPIC_TRIGGER_EDGE             0
  46 #define IOAPIC_TRIGGER_LEVEL            1
  47
  48 /*io{apic,sapic} delivery mode*/
  49 #define IOAPIC_DM_FIXED                 0x0
  50 #define IOAPIC_DM_LOWEST_PRIORITY       0x1
  51 #define IOAPIC_DM_PMI                   0x2
  52 #define IOAPIC_DM_NMI                   0x4
  53 #define IOAPIC_DM_INIT                  0x5
  54 #define IOAPIC_DM_SIPI                  0x5
  55 #define IOAPIC_DM_EXTINT                0x7
  56
  57 typedef struct IOAPICState IOAPICState;
  58
  59 struct IOAPICState {
  60     SysBusDevice busdev;
  61     uint8_t id;
  62     uint8_t ioregsel;
  63
  64     uint32_t irr;
  65     uint64_t ioredtbl[IOAPIC_NUM_PINS];
  66 };
  67
  68 static IOAPICState *ioapics[MAX_IOAPICS];
  69
  70 static void ioapic_service(IOAPICState *s)
  71 {
  72     uint8_t i;
  73     uint8_t trig_mode;
  74     uint8_t vector;
  75     uint8_t delivery_mode;
  76     uint32_t mask;
  77     uint64_t entry;
  78     uint8_t dest;
  79     uint8_t dest_mode;
  80     uint8_t polarity;
  81
  82     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  83         mask = 1 << i;
  84         if (s->irr & mask) {
  85             entry = s->ioredtbl[i];
  86             if (!(entry & IOAPIC_LVT_MASKED)) {
  87                 trig_mode = ((entry >> 15) & 1);
  88                 dest = entry >> 56;
  89                 dest_mode = (entry >> 11) & 1;
  90                 delivery_mode = (entry >> 8) & 7;
  91                 polarity = (entry >> 13) & 1;
  92                 if (trig_mode == IOAPIC_TRIGGER_EDGE) {
  93                     s->irr &= ~mask;
  94                 } else {
  95                     s->ioredtbl[i] |= IOAPIC_LVT_REMOTE_IRR;
  96                 }
  97                 if (delivery_mode == IOAPIC_DM_EXTINT)
  98                     vector = pic_read_irq(isa_pic);
  99                 else
 100                     vector = entry & 0xff;
 101
 102                 apic_deliver_irq(dest, dest_mode, delivery_mode,
 103                                  vector, polarity, trig_mode);
 104             }
 105         }
 106     }
 107 }
 108
 109 static void ioapic_set_irq(void *opaque, int vector, int level)
 110 {
 111     IOAPICState *s = opaque;
 112
 113     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
 114      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
 115      * the cleanest way of doing it but it should work. */
 116
 117     DPRINTF("%s: %s vec %x\n", __func__, level? "raise" : "lower", vector);
 118     if (vector == 0)
 119         vector = 2;
 120
 121     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 122         uint32_t mask = 1 << vector;
 123         uint64_t entry = s->ioredtbl[vector];
 124
 125         if ((entry >> 15) & 1) {
 126             /* level triggered */
 127             if (level) {
 128                 s->irr |= mask;
 129                 ioapic_service(s);
 130             } else {
 131                 s->irr &= ~mask;
 132             }
 133         } else {
 134             /* edge triggered */
 135             if (level) {
 136                 s->irr |= mask;
 137                 ioapic_service(s);
 138             }
 139         }
 140     }
 141 }
 142
 143 void ioapic_eoi_broadcast(int vector)
 144 {
 145     IOAPICState *s;
 146     uint64_t entry;
 147     int i, n;
 148
 149     for (i = 0; i < MAX_IOAPICS; i++) {
 150         s = ioapics[i];
 151         if (!s) {
 152             continue;
 153         }
 154         for (n = 0; n < IOAPIC_NUM_PINS; n++) {
 155             entry = s->ioredtbl[n];
 156             if ((entry & IOAPIC_LVT_REMOTE_IRR) && (entry & 0xff) == vector) {
 157                 s->ioredtbl[n] = entry & ~IOAPIC_LVT_REMOTE_IRR;
 158                 if (!(entry & IOAPIC_LVT_MASKED) && (s->irr & (1 << n))) {
 159                     ioapic_service(s);
 160                 }
 161             }
 162         }
 163     }
 164 }
 165
 166 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
 167 {
 168     IOAPICState *s = opaque;
 169     int index;
 170     uint32_t val = 0;
 171
 172     addr &= 0xff;
 173     if (addr == 0x00) {
 174         val = s->ioregsel;
 175     } else if (addr == 0x10) {
 176         switch (s->ioregsel) {
 177             case 0x00:
 178                 val = s->id << 24;
 179                 break;
 180             case 0x01:
 181                 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
 182                 break;
 183             case 0x02:
 184                 val = 0;
 185                 break;
 186             default:
 187                 index = (s->ioregsel - 0x10) >> 1;
 188                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
 189                     if (s->ioregsel & 1)
 190                         val = s->ioredtbl[index] >> 32;
 191                     else
 192                         val = s->ioredtbl[index] & 0xffffffff;
 193                 }
 194         }
 195         DPRINTF("read: %08x = %08x\n", s->ioregsel, val);
 196     }
 197     return val;
 198 }
 199
 200 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 201 {
 202     IOAPICState *s = opaque;
 203     int index;
 204
 205     addr &= 0xff;
 206     if (addr == 0x00)  {
 207         s->ioregsel = val;
 208         return;
 209     } else if (addr == 0x10) {
 210         DPRINTF("write: %08x = %08x\n", s->ioregsel, val);
 211         switch (s->ioregsel) {
 212             case 0x00:
 213                 s->id = (val >> 24) & 0xff;
 214                 return;
 215             case 0x01:
 216             case 0x02:
 217                 return;
 218             default:
 219                 index = (s->ioregsel - 0x10) >> 1;
 220                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
 221                     if (s->ioregsel & 1) {
 222                         s->ioredtbl[index] &= 0xffffffff;
 223                         s->ioredtbl[index] |= (uint64_t)val << 32;
 224                     } else {
 225                         s->ioredtbl[index] &= ~0xffffffffULL;
 226                         s->ioredtbl[index] |= val;
 227                     }
 228                     ioapic_service(s);
 229                 }
 230         }
 231     }
 232 }
 233
 234 static const VMStateDescription vmstate_ioapic = {
 235     .name = "ioapic",
 236     .version_id = 1,
 237     .minimum_version_id = 1,
 238     .minimum_version_id_old = 1,
 239     .fields      = (VMStateField []) {
 240         VMSTATE_UINT8(id, IOAPICState),
 241         VMSTATE_UINT8(ioregsel, IOAPICState),
 242         VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
 243         VMSTATE_END_OF_LIST()
 244     }
 245 };
 246
 247 static void ioapic_reset(DeviceState *d)
 248 {
 249     IOAPICState *s = DO_UPCAST(IOAPICState, busdev.qdev, d);
 250     int i;
 251
 252     s->id = 0;
 253     s->ioregsel = 0;
 254     s->irr = 0;
 255     for(i = 0; i < IOAPIC_NUM_PINS; i++)
 256         s->ioredtbl[i] = 1 << 16; /* mask LVT */
 257 }
 258
 259 static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
 260     ioapic_mem_readl,
 261     ioapic_mem_readl,
 262     ioapic_mem_readl,
 263 };
 264
 265 static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
 266     ioapic_mem_writel,
 267     ioapic_mem_writel,
 268     ioapic_mem_writel,
 269 };
 270
 271 static int ioapic_init1(SysBusDevice *dev)
 272 {
 273     IOAPICState *s = FROM_SYSBUS(IOAPICState, dev);
 274     int io_memory;
 275     static int ioapic_no;
 276
 277     if (ioapic_no >= MAX_IOAPICS) {
 278         return -1;
 279     }
 280
 281     io_memory = cpu_register_io_memory(ioapic_mem_read,
 282                                        ioapic_mem_write, s,
 283                                        DEVICE_NATIVE_ENDIAN);
 284     sysbus_init_mmio(dev, 0x1000, io_memory);
 285
 286     qdev_init_gpio_in(&dev->qdev, ioapic_set_irq, IOAPIC_NUM_PINS);
 287
 288     ioapics[ioapic_no++] = s;
 289
 290     return 0;
 291 }
 292
 293 static SysBusDeviceInfo ioapic_info = {
 294     .init = ioapic_init1,
 295     .qdev.name = "ioapic",
 296     .qdev.size = sizeof(IOAPICState),
 297     .qdev.vmsd = &vmstate_ioapic,
 298     .qdev.reset = ioapic_reset,
 299     .qdev.no_user = 1,
 300 };
 301
 302 static void ioapic_register_devices(void)
 303 {
 304     sysbus_register_withprop(&ioapic_info);
 305 }
 306
 307 device_init(ioapic_register_devices)