hw/ipmi/ipmi_bt.c

   1 /*
   2  * QEMU IPMI BT emulation
   3  *
   4  * Copyright (c) 2015 Corey Minyard, MontaVista Software, LLC
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "migration/vmstate.h"
  26 #include "qemu/log.h"
  27 #include "qapi/error.h"
  28 #include "hw/ipmi/ipmi_bt.h"
  29
  30 /* Control register */
  31 #define IPMI_BT_CLR_WR_BIT         0
  32 #define IPMI_BT_CLR_RD_BIT         1
  33 #define IPMI_BT_H2B_ATN_BIT        2
  34 #define IPMI_BT_B2H_ATN_BIT        3
  35 #define IPMI_BT_SMS_ATN_BIT        4
  36 #define IPMI_BT_HBUSY_BIT          6
  37 #define IPMI_BT_BBUSY_BIT          7
  38
  39 #define IPMI_BT_GET_CLR_WR(d)      (((d) >> IPMI_BT_CLR_WR_BIT) & 0x1)
  40
  41 #define IPMI_BT_GET_CLR_RD(d)      (((d) >> IPMI_BT_CLR_RD_BIT) & 0x1)
  42
  43 #define IPMI_BT_GET_H2B_ATN(d)     (((d) >> IPMI_BT_H2B_ATN_BIT) & 0x1)
  44
  45 #define IPMI_BT_B2H_ATN_MASK       (1 << IPMI_BT_B2H_ATN_BIT)
  46 #define IPMI_BT_GET_B2H_ATN(d)     (((d) >> IPMI_BT_B2H_ATN_BIT) & 0x1)
  47 #define IPMI_BT_SET_B2H_ATN(d, v)  ((d) = (((d) & ~IPMI_BT_B2H_ATN_MASK) | \
  48                                         (!!(v) << IPMI_BT_B2H_ATN_BIT)))
  49
  50 #define IPMI_BT_SMS_ATN_MASK       (1 << IPMI_BT_SMS_ATN_BIT)
  51 #define IPMI_BT_GET_SMS_ATN(d)     (((d) >> IPMI_BT_SMS_ATN_BIT) & 0x1)
  52 #define IPMI_BT_SET_SMS_ATN(d, v)  ((d) = (((d) & ~IPMI_BT_SMS_ATN_MASK) | \
  53                                         (!!(v) << IPMI_BT_SMS_ATN_BIT)))
  54
  55 #define IPMI_BT_HBUSY_MASK         (1 << IPMI_BT_HBUSY_BIT)
  56 #define IPMI_BT_GET_HBUSY(d)       (((d) >> IPMI_BT_HBUSY_BIT) & 0x1)
  57 #define IPMI_BT_SET_HBUSY(d, v)    ((d) = (((d) & ~IPMI_BT_HBUSY_MASK) | \
  58                                        (!!(v) << IPMI_BT_HBUSY_BIT)))
  59
  60 #define IPMI_BT_BBUSY_MASK         (1 << IPMI_BT_BBUSY_BIT)
  61 #define IPMI_BT_SET_BBUSY(d, v)    ((d) = (((d) & ~IPMI_BT_BBUSY_MASK) | \
  62                                        (!!(v) << IPMI_BT_BBUSY_BIT)))
  63
  64
  65 /* Mask register */
  66 #define IPMI_BT_B2H_IRQ_EN_BIT     0
  67 #define IPMI_BT_B2H_IRQ_BIT        1
  68
  69 #define IPMI_BT_B2H_IRQ_EN_MASK      (1 << IPMI_BT_B2H_IRQ_EN_BIT)
  70 #define IPMI_BT_GET_B2H_IRQ_EN(d)    (((d) >> IPMI_BT_B2H_IRQ_EN_BIT) & 0x1)
  71 #define IPMI_BT_SET_B2H_IRQ_EN(d, v) ((d) = (((d) & ~IPMI_BT_B2H_IRQ_EN_MASK) |\
  72                                         (!!(v) << IPMI_BT_B2H_IRQ_EN_BIT)))
  73
  74 #define IPMI_BT_B2H_IRQ_MASK         (1 << IPMI_BT_B2H_IRQ_BIT)
  75 #define IPMI_BT_GET_B2H_IRQ(d)       (((d) >> IPMI_BT_B2H_IRQ_BIT) & 0x1)
  76 #define IPMI_BT_SET_B2H_IRQ(d, v)    ((d) = (((d) & ~IPMI_BT_B2H_IRQ_MASK) | \
  77                                         (!!(v) << IPMI_BT_B2H_IRQ_BIT)))
  78
  79 #define IPMI_CMD_GET_BT_INTF_CAP        0x36
  80
  81 static void ipmi_bt_raise_irq(IPMIBT *ib)
  82 {
  83     if (ib->use_irq && ib->irqs_enabled && ib->raise_irq) {
  84         ib->raise_irq(ib);
  85     }
  86 }
  87
  88 static void ipmi_bt_lower_irq(IPMIBT *ib)
  89 {
  90     if (ib->lower_irq) {
  91         ib->lower_irq(ib);
  92     }
  93 }
  94
  95 static void ipmi_bt_handle_event(IPMIInterface *ii)
  96 {
  97     IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
  98     IPMIBT *ib = iic->get_backend_data(ii);
  99
 100     if (ib->inlen < 4) {
 101         goto out;
 102     }
 103     /* Note that overruns are handled by handle_command */
 104     if (ib->inmsg[0] != (ib->inlen - 1)) {
 105         /* Length mismatch, just ignore. */
 106         IPMI_BT_SET_BBUSY(ib->control_reg, 1);
 107         ib->inlen = 0;
 108         goto out;
 109     }
 110     if ((ib->inmsg[1] == (IPMI_NETFN_APP << 2)) &&
 111                         (ib->inmsg[3] == IPMI_CMD_GET_BT_INTF_CAP)) {
 112         /* We handle this one ourselves. */
 113         ib->outmsg[0] = 9;
 114         ib->outmsg[1] = ib->inmsg[1] | 0x04;
 115         ib->outmsg[2] = ib->inmsg[2];
 116         ib->outmsg[3] = ib->inmsg[3];
 117         ib->outmsg[4] = 0;
 118         ib->outmsg[5] = 1; /* Only support 1 outstanding request. */
 119         if (sizeof(ib->inmsg) > 0xff) { /* Input buffer size */
 120             ib->outmsg[6] = 0xff;
 121         } else {
 122             ib->outmsg[6] = (unsigned char) sizeof(ib->inmsg);
 123         }
 124         if (sizeof(ib->outmsg) > 0xff) { /* Output buffer size */
 125             ib->outmsg[7] = 0xff;
 126         } else {
 127             ib->outmsg[7] = (unsigned char) sizeof(ib->outmsg);
 128         }
 129         ib->outmsg[8] = 10; /* Max request to response time */
 130         ib->outmsg[9] = 0; /* Don't recommend retries */
 131         ib->outlen = 10;
 132         IPMI_BT_SET_BBUSY(ib->control_reg, 0);
 133         IPMI_BT_SET_B2H_ATN(ib->control_reg, 1);
 134         if (!IPMI_BT_GET_B2H_IRQ(ib->mask_reg) &&
 135                 IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) {
 136             IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1);
 137             ipmi_bt_raise_irq(ib);
 138         }
 139         goto out;
 140     }
 141     ib->waiting_seq = ib->inmsg[2];
 142     ib->inmsg[2] = ib->inmsg[1];
 143     {
 144         IPMIBmcClass *bk = IPMI_BMC_GET_CLASS(ib->bmc);
 145         bk->handle_command(ib->bmc, ib->inmsg + 2, ib->inlen - 2,
 146                            sizeof(ib->inmsg), ib->waiting_rsp);
 147     }
 148  out:
 149     return;
 150 }
 151
 152 static void ipmi_bt_handle_rsp(IPMIInterface *ii, uint8_t msg_id,
 153                                 unsigned char *rsp, unsigned int rsp_len)
 154 {
 155     IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
 156     IPMIBT *ib = iic->get_backend_data(ii);
 157
 158     if (ib->waiting_rsp == msg_id) {
 159         ib->waiting_rsp++;
 160         if (rsp_len > (sizeof(ib->outmsg) - 2)) {
 161             ib->outmsg[0] = 4;
 162             ib->outmsg[1] = rsp[0];
 163             ib->outmsg[2] = ib->waiting_seq;
 164             ib->outmsg[3] = rsp[1];
 165             ib->outmsg[4] = IPMI_CC_CANNOT_RETURN_REQ_NUM_BYTES;
 166             ib->outlen = 5;
 167         } else {
 168             ib->outmsg[0] = rsp_len + 1;
 169             ib->outmsg[1] = rsp[0];
 170             ib->outmsg[2] = ib->waiting_seq;
 171             memcpy(ib->outmsg + 3, rsp + 1, rsp_len - 1);
 172             ib->outlen = rsp_len + 2;
 173         }
 174         IPMI_BT_SET_BBUSY(ib->control_reg, 0);
 175         IPMI_BT_SET_B2H_ATN(ib->control_reg, 1);
 176         if (!IPMI_BT_GET_B2H_IRQ(ib->mask_reg) &&
 177                 IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) {
 178             IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1);
 179             ipmi_bt_raise_irq(ib);
 180         }
 181     }
 182 }
 183
 184
 185 static uint64_t ipmi_bt_ioport_read(void *opaque, hwaddr addr, unsigned size)
 186 {
 187     IPMIInterface *ii = opaque;
 188     IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
 189     IPMIBT *ib = iic->get_backend_data(ii);
 190     uint32_t ret = 0xff;
 191
 192     switch (addr & 3) {
 193     case 0:
 194         ret = ib->control_reg;
 195         break;
 196     case 1:
 197         if (ib->outpos < ib->outlen) {
 198             ret = ib->outmsg[ib->outpos];
 199             ib->outpos++;
 200             if (ib->outpos == ib->outlen) {
 201                 ib->outpos = 0;
 202                 ib->outlen = 0;
 203             }
 204         } else {
 205             ret = 0xff;
 206         }
 207         break;
 208     case 2:
 209         ret = ib->mask_reg;
 210         break;
 211     }
 212     return ret;
 213 }
 214
 215 static void ipmi_bt_signal(IPMIBT *ib, IPMIInterface *ii)
 216 {
 217     IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
 218
 219     ib->do_wake = 1;
 220     while (ib->do_wake) {
 221         ib->do_wake = 0;
 222         iic->handle_if_event(ii);
 223     }
 224 }
 225
 226 static void ipmi_bt_ioport_write(void *opaque, hwaddr addr, uint64_t val,
 227                                  unsigned size)
 228 {
 229     IPMIInterface *ii = opaque;
 230     IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
 231     IPMIBT *ib = iic->get_backend_data(ii);
 232
 233     switch (addr & 3) {
 234     case 0:
 235         if (IPMI_BT_GET_CLR_WR(val)) {
 236             ib->inlen = 0;
 237         }
 238         if (IPMI_BT_GET_CLR_RD(val)) {
 239             ib->outpos = 0;
 240         }
 241         if (IPMI_BT_GET_B2H_ATN(val)) {
 242             IPMI_BT_SET_B2H_ATN(ib->control_reg, 0);
 243         }
 244         if (IPMI_BT_GET_SMS_ATN(val)) {
 245             IPMI_BT_SET_SMS_ATN(ib->control_reg, 0);
 246         }
 247         if (IPMI_BT_GET_HBUSY(val)) {
 248             /* Toggle */
 249             IPMI_BT_SET_HBUSY(ib->control_reg,
 250                               !IPMI_BT_GET_HBUSY(ib->control_reg));
 251         }
 252         if (IPMI_BT_GET_H2B_ATN(val)) {
 253             IPMI_BT_SET_BBUSY(ib->control_reg, 1);
 254             ipmi_bt_signal(ib, ii);
 255         }
 256         break;
 257
 258     case 1:
 259         if (ib->inlen < sizeof(ib->inmsg)) {
 260             ib->inmsg[ib->inlen] = val;
 261         }
 262         ib->inlen++;
 263         break;
 264
 265     case 2:
 266         if (IPMI_BT_GET_B2H_IRQ_EN(val) !=
 267                         IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) {
 268             if (IPMI_BT_GET_B2H_IRQ_EN(val)) {
 269                 if (IPMI_BT_GET_B2H_ATN(ib->control_reg) ||
 270                         IPMI_BT_GET_SMS_ATN(ib->control_reg)) {
 271                     IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1);
 272                     ipmi_bt_raise_irq(ib);
 273                 }
 274                 IPMI_BT_SET_B2H_IRQ_EN(ib->mask_reg, 1);
 275             } else {
 276                 if (IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) {
 277                     IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0);
 278                     ipmi_bt_lower_irq(ib);
 279                 }
 280                 IPMI_BT_SET_B2H_IRQ_EN(ib->mask_reg, 0);
 281             }
 282         }
 283         if (IPMI_BT_GET_B2H_IRQ(val) && IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) {
 284             IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0);
 285             ipmi_bt_lower_irq(ib);
 286         }
 287         break;
 288     }
 289 }
 290
 291 static const MemoryRegionOps ipmi_bt_io_ops = {
 292     .read = ipmi_bt_ioport_read,
 293     .write = ipmi_bt_ioport_write,
 294     .impl = {
 295         .min_access_size = 1,
 296         .max_access_size = 1,
 297     },
 298     .endianness = DEVICE_LITTLE_ENDIAN,
 299 };
 300
 301 static void ipmi_bt_set_atn(IPMIInterface *ii, int val, int irq)
 302 {
 303     IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
 304     IPMIBT *ib = iic->get_backend_data(ii);
 305
 306     if (!!val == IPMI_BT_GET_SMS_ATN(ib->control_reg)) {
 307         return;
 308     }
 309
 310     IPMI_BT_SET_SMS_ATN(ib->control_reg, val);
 311     if (val) {
 312         if (irq && !IPMI_BT_GET_B2H_ATN(ib->control_reg) &&
 313                 IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) {
 314             IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1);
 315             ipmi_bt_raise_irq(ib);
 316         }
 317     } else {
 318         if (!IPMI_BT_GET_B2H_ATN(ib->control_reg) &&
 319                 IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) {
 320             IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0);
 321             ipmi_bt_lower_irq(ib);
 322         }
 323     }
 324 }
 325
 326 static void ipmi_bt_handle_reset(IPMIInterface *ii, bool is_cold)
 327 {
 328     IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
 329     IPMIBT *ib = iic->get_backend_data(ii);
 330
 331     if (is_cold) {
 332         /* Disable the BT interrupt on reset */
 333         if (IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) {
 334             IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0);
 335             ipmi_bt_lower_irq(ib);
 336         }
 337         IPMI_BT_SET_B2H_IRQ_EN(ib->mask_reg, 0);
 338     }
 339 }
 340
 341 static void ipmi_bt_set_irq_enable(IPMIInterface *ii, int val)
 342 {
 343     IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
 344     IPMIBT *ib = iic->get_backend_data(ii);
 345
 346     ib->irqs_enabled = val;
 347 }
 348
 349 static void ipmi_bt_init(IPMIInterface *ii, Error **errp)
 350 {
 351     IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii);
 352     IPMIBT *ib = iic->get_backend_data(ii);
 353
 354     ib->io_length = 3;
 355
 356     memory_region_init_io(&ib->io, NULL, &ipmi_bt_io_ops, ii, "ipmi-bt", 3);
 357 }
 358
 359 int ipmi_bt_vmstate_post_load(void *opaque, int version)
 360 {
 361     IPMIBT *ib = opaque;
 362
 363     /* Make sure all the values are sane. */
 364     if (ib->outpos >= MAX_IPMI_MSG_SIZE || ib->outlen >= MAX_IPMI_MSG_SIZE ||
 365         ib->outpos >= ib->outlen) {
 366         qemu_log_mask(LOG_GUEST_ERROR,
 367                       "ipmi:bt: vmstate transfer received bad out values: %d %d\n",
 368                       ib->outpos, ib->outlen);
 369         ib->outpos = 0;
 370         ib->outlen = 0;
 371     }
 372
 373     if (ib->inlen >= MAX_IPMI_MSG_SIZE) {
 374         qemu_log_mask(LOG_GUEST_ERROR,
 375                       "ipmi:bt: vmstate transfer received bad in value: %d\n",
 376                       ib->inlen);
 377         ib->inlen = 0;
 378     }
 379
 380     return 0;
 381 }
 382
 383 const VMStateDescription vmstate_IPMIBT = {
 384     .name = TYPE_IPMI_INTERFACE_PREFIX "bt",
 385     .version_id = 1,
 386     .minimum_version_id = 1,
 387     .post_load = ipmi_bt_vmstate_post_load,
 388     .fields      = (VMStateField[]) {
 389         VMSTATE_BOOL(obf_irq_set, IPMIBT),
 390         VMSTATE_BOOL(atn_irq_set, IPMIBT),
 391         VMSTATE_BOOL(irqs_enabled, IPMIBT),
 392         VMSTATE_UINT32(outpos, IPMIBT),
 393         VMSTATE_UINT32(outlen, IPMIBT),
 394         VMSTATE_UINT8_ARRAY(outmsg, IPMIBT, MAX_IPMI_MSG_SIZE),
 395         VMSTATE_UINT32(inlen, IPMIBT),
 396         VMSTATE_UINT8_ARRAY(inmsg, IPMIBT, MAX_IPMI_MSG_SIZE),
 397         VMSTATE_UINT8(control_reg, IPMIBT),
 398         VMSTATE_UINT8(mask_reg, IPMIBT),
 399         VMSTATE_UINT8(waiting_rsp, IPMIBT),
 400         VMSTATE_UINT8(waiting_seq, IPMIBT),
 401         VMSTATE_END_OF_LIST()
 402     }
 403 };
 404
 405 void ipmi_bt_get_fwinfo(struct IPMIBT *ib, IPMIFwInfo *info)
 406 {
 407     info->interface_name = "bt";
 408     info->interface_type = IPMI_SMBIOS_BT;
 409     info->ipmi_spec_major_revision = 2;
 410     info->ipmi_spec_minor_revision = 0;
 411     info->base_address = ib->io_base;
 412     info->register_length = ib->io_length;
 413     info->register_spacing = 1;
 414     info->memspace = IPMI_MEMSPACE_IO;
 415     info->irq_type = IPMI_LEVEL_IRQ;
 416 }
 417
 418 void ipmi_bt_class_init(IPMIInterfaceClass *iic)
 419 {
 420     iic->init = ipmi_bt_init;
 421     iic->set_atn = ipmi_bt_set_atn;
 422     iic->handle_rsp = ipmi_bt_handle_rsp;
 423     iic->handle_if_event = ipmi_bt_handle_event;
 424     iic->set_irq_enable = ipmi_bt_set_irq_enable;
 425     iic->reset = ipmi_bt_handle_reset;
 426 }