hw/isa/piix4.c

   1 /*
   2  * QEMU PIIX4 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2018 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/irq.h"
  28 #include "hw/i386/pc.h"
  29 #include "hw/pci/pci.h"
  30 #include "hw/isa/isa.h"
  31 #include "hw/sysbus.h"
  32 #include "hw/dma/i8257.h"
  33 #include "migration/vmstate.h"
  34 #include "sysemu/reset.h"
  35 #include "sysemu/runstate.h"
  36
  37 PCIDevice *piix4_dev;
  38
  39 typedef struct PIIX4State {
  40     PCIDevice dev;
  41     qemu_irq cpu_intr;
  42     qemu_irq *isa;
  43
  44     /* Reset Control Register */
  45     MemoryRegion rcr_mem;
  46     uint8_t rcr;
  47 } PIIX4State;
  48
  49 #define PIIX4_PCI_DEVICE(obj) \
  50     OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
  51
  52 static void piix4_isa_reset(DeviceState *dev)
  53 {
  54     PIIX4State *d = PIIX4_PCI_DEVICE(dev);
  55     uint8_t *pci_conf = d->dev.config;
  56
  57     pci_conf[0x04] = 0x07; // master, memory and I/O
  58     pci_conf[0x05] = 0x00;
  59     pci_conf[0x06] = 0x00;
  60     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
  61     pci_conf[0x4c] = 0x4d;
  62     pci_conf[0x4e] = 0x03;
  63     pci_conf[0x4f] = 0x00;
  64     pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
  65     pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
  66     pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
  67     pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
  68     pci_conf[0x69] = 0x02;
  69     pci_conf[0x70] = 0x80;
  70     pci_conf[0x76] = 0x0c;
  71     pci_conf[0x77] = 0x0c;
  72     pci_conf[0x78] = 0x02;
  73     pci_conf[0x79] = 0x00;
  74     pci_conf[0x80] = 0x00;
  75     pci_conf[0x82] = 0x00;
  76     pci_conf[0xa0] = 0x08;
  77     pci_conf[0xa2] = 0x00;
  78     pci_conf[0xa3] = 0x00;
  79     pci_conf[0xa4] = 0x00;
  80     pci_conf[0xa5] = 0x00;
  81     pci_conf[0xa6] = 0x00;
  82     pci_conf[0xa7] = 0x00;
  83     pci_conf[0xa8] = 0x0f;
  84     pci_conf[0xaa] = 0x00;
  85     pci_conf[0xab] = 0x00;
  86     pci_conf[0xac] = 0x00;
  87     pci_conf[0xae] = 0x00;
  88 }
  89
  90 static const VMStateDescription vmstate_piix4 = {
  91     .name = "PIIX4",
  92     .version_id = 2,
  93     .minimum_version_id = 2,
  94     .fields = (VMStateField[]) {
  95         VMSTATE_PCI_DEVICE(dev, PIIX4State),
  96         VMSTATE_END_OF_LIST()
  97     }
  98 };
  99
 100 static void piix4_request_i8259_irq(void *opaque, int irq, int level)
 101 {
 102     PIIX4State *s = opaque;
 103     qemu_set_irq(s->cpu_intr, level);
 104 }
 105
 106 static void piix4_set_i8259_irq(void *opaque, int irq, int level)
 107 {
 108     PIIX4State *s = opaque;
 109     qemu_set_irq(s->isa[irq], level);
 110 }
 111
 112 static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
 113                             unsigned int len)
 114 {
 115     PIIX4State *s = opaque;
 116
 117     if (val & 4) {
 118         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 119         return;
 120     }
 121
 122     s->rcr = val & 2; /* keep System Reset type only */
 123 }
 124
 125 static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
 126 {
 127     PIIX4State *s = opaque;
 128
 129     return s->rcr;
 130 }
 131
 132 static const MemoryRegionOps piix4_rcr_ops = {
 133     .read = piix4_rcr_read,
 134     .write = piix4_rcr_write,
 135     .endianness = DEVICE_LITTLE_ENDIAN,
 136     .impl = {
 137         .min_access_size = 1,
 138         .max_access_size = 1,
 139     },
 140 };
 141
 142 static void piix4_realize(PCIDevice *dev, Error **errp)
 143 {
 144     PIIX4State *s = PIIX4_PCI_DEVICE(dev);
 145     ISABus *isa_bus;
 146     qemu_irq *i8259_out_irq;
 147
 148     isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
 149                           pci_address_space_io(dev), errp);
 150     if (!isa_bus) {
 151         return;
 152     }
 153
 154     qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
 155                             "isa", ISA_NUM_IRQS);
 156     qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
 157                              "intr", 1);
 158
 159     memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
 160                           "reset-control", 1);
 161     memory_region_add_subregion_overlap(pci_address_space_io(dev),
 162                                         RCR_IOPORT, &s->rcr_mem, 1);
 163
 164     /* initialize i8259 pic */
 165     i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
 166     s->isa = i8259_init(isa_bus, *i8259_out_irq);
 167
 168     /* initialize ISA irqs */
 169     isa_bus_irqs(isa_bus, s->isa);
 170
 171     /* DMA */
 172     i8257_dma_init(isa_bus, 0);
 173
 174     piix4_dev = dev;
 175 }
 176
 177 static void piix4_class_init(ObjectClass *klass, void *data)
 178 {
 179     DeviceClass *dc = DEVICE_CLASS(klass);
 180     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 181
 182     k->realize = piix4_realize;
 183     k->vendor_id = PCI_VENDOR_ID_INTEL;
 184     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
 185     k->class_id = PCI_CLASS_BRIDGE_ISA;
 186     dc->reset = piix4_isa_reset;
 187     dc->desc = "ISA bridge";
 188     dc->vmsd = &vmstate_piix4;
 189     /*
 190      * Reason: part of PIIX4 southbridge, needs to be wired up,
 191      * e.g. by mips_malta_init()
 192      */
 193     dc->user_creatable = false;
 194     dc->hotpluggable = false;
 195 }
 196
 197 static const TypeInfo piix4_info = {
 198     .name          = TYPE_PIIX4_PCI_DEVICE,
 199     .parent        = TYPE_PCI_DEVICE,
 200     .instance_size = sizeof(PIIX4State),
 201     .class_init    = piix4_class_init,
 202     .interfaces = (InterfaceInfo[]) {
 203         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 204         { },
 205     },
 206 };
 207
 208 static void piix4_register_types(void)
 209 {
 210     type_register_static(&piix4_info);
 211 }
 212
 213 type_init(piix4_register_types)