hw/isa/piix4.c

   1 /*
   2  * QEMU PIIX4 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2018 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/i386/pc.h"
  28 #include "hw/pci/pci.h"
  29 #include "hw/isa/isa.h"
  30 #include "hw/sysbus.h"
  31 #include "migration/vmstate.h"
  32 #include "sysemu/reset.h"
  33 #include "sysemu/runstate.h"
  34
  35 PCIDevice *piix4_dev;
  36
  37 typedef struct PIIX4State {
  38     PCIDevice dev;
  39
  40     /* Reset Control Register */
  41     MemoryRegion rcr_mem;
  42     uint8_t rcr;
  43 } PIIX4State;
  44
  45 #define TYPE_PIIX4_PCI_DEVICE "PIIX4"
  46 #define PIIX4_PCI_DEVICE(obj) \
  47     OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
  48
  49 static void piix4_isa_reset(DeviceState *dev)
  50 {
  51     PIIX4State *d = PIIX4_PCI_DEVICE(dev);
  52     uint8_t *pci_conf = d->dev.config;
  53
  54     pci_conf[0x04] = 0x07; // master, memory and I/O
  55     pci_conf[0x05] = 0x00;
  56     pci_conf[0x06] = 0x00;
  57     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
  58     pci_conf[0x4c] = 0x4d;
  59     pci_conf[0x4e] = 0x03;
  60     pci_conf[0x4f] = 0x00;
  61     pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
  62     pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
  63     pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
  64     pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
  65     pci_conf[0x69] = 0x02;
  66     pci_conf[0x70] = 0x80;
  67     pci_conf[0x76] = 0x0c;
  68     pci_conf[0x77] = 0x0c;
  69     pci_conf[0x78] = 0x02;
  70     pci_conf[0x79] = 0x00;
  71     pci_conf[0x80] = 0x00;
  72     pci_conf[0x82] = 0x00;
  73     pci_conf[0xa0] = 0x08;
  74     pci_conf[0xa2] = 0x00;
  75     pci_conf[0xa3] = 0x00;
  76     pci_conf[0xa4] = 0x00;
  77     pci_conf[0xa5] = 0x00;
  78     pci_conf[0xa6] = 0x00;
  79     pci_conf[0xa7] = 0x00;
  80     pci_conf[0xa8] = 0x0f;
  81     pci_conf[0xaa] = 0x00;
  82     pci_conf[0xab] = 0x00;
  83     pci_conf[0xac] = 0x00;
  84     pci_conf[0xae] = 0x00;
  85 }
  86
  87 static const VMStateDescription vmstate_piix4 = {
  88     .name = "PIIX4",
  89     .version_id = 2,
  90     .minimum_version_id = 2,
  91     .fields = (VMStateField[]) {
  92         VMSTATE_PCI_DEVICE(dev, PIIX4State),
  93         VMSTATE_END_OF_LIST()
  94     }
  95 };
  96
  97 static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
  98                             unsigned int len)
  99 {
 100     PIIX4State *s = opaque;
 101
 102     if (val & 4) {
 103         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 104         return;
 105     }
 106
 107     s->rcr = val & 2; /* keep System Reset type only */
 108 }
 109
 110 static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
 111 {
 112     PIIX4State *s = opaque;
 113
 114     return s->rcr;
 115 }
 116
 117 static const MemoryRegionOps piix4_rcr_ops = {
 118     .read = piix4_rcr_read,
 119     .write = piix4_rcr_write,
 120     .endianness = DEVICE_LITTLE_ENDIAN,
 121     .impl = {
 122         .min_access_size = 1,
 123         .max_access_size = 1,
 124     },
 125 };
 126
 127 static void piix4_realize(PCIDevice *dev, Error **errp)
 128 {
 129     PIIX4State *s = PIIX4_PCI_DEVICE(dev);
 130
 131     if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
 132                      pci_address_space_io(dev), errp)) {
 133         return;
 134     }
 135
 136     memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
 137                           "reset-control", 1);
 138     memory_region_add_subregion_overlap(pci_address_space_io(dev),
 139                                         RCR_IOPORT, &s->rcr_mem, 1);
 140
 141     piix4_dev = dev;
 142 }
 143
 144 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
 145 {
 146     PCIDevice *d;
 147
 148     d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
 149     *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
 150     return d->devfn;
 151 }
 152
 153 static void piix4_class_init(ObjectClass *klass, void *data)
 154 {
 155     DeviceClass *dc = DEVICE_CLASS(klass);
 156     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 157
 158     k->realize = piix4_realize;
 159     k->vendor_id = PCI_VENDOR_ID_INTEL;
 160     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
 161     k->class_id = PCI_CLASS_BRIDGE_ISA;
 162     dc->reset = piix4_isa_reset;
 163     dc->desc = "ISA bridge";
 164     dc->vmsd = &vmstate_piix4;
 165     /*
 166      * Reason: part of PIIX4 southbridge, needs to be wired up,
 167      * e.g. by mips_malta_init()
 168      */
 169     dc->user_creatable = false;
 170     dc->hotpluggable = false;
 171 }
 172
 173 static const TypeInfo piix4_info = {
 174     .name          = TYPE_PIIX4_PCI_DEVICE,
 175     .parent        = TYPE_PCI_DEVICE,
 176     .instance_size = sizeof(PIIX4State),
 177     .class_init    = piix4_class_init,
 178     .interfaces = (InterfaceInfo[]) {
 179         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 180         { },
 181     },
 182 };
 183
 184 static void piix4_register_types(void)
 185 {
 186     type_register_static(&piix4_info);
 187 }
 188
 189 type_init(piix4_register_types)