hw/isa/piix4.c

   1 /*
   2  * QEMU PIIX4 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  * Copyright (c) 2018 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qapi/error.h"
  28 #include "hw/irq.h"
  29 #include "hw/southbridge/piix.h"
  30 #include "hw/pci/pci.h"
  31 #include "hw/isa/isa.h"
  32 #include "hw/intc/i8259.h"
  33 #include "hw/dma/i8257.h"
  34 #include "hw/timer/i8254.h"
  35 #include "hw/rtc/mc146818rtc.h"
  36 #include "hw/ide/pci.h"
  37 #include "migration/vmstate.h"
  38 #include "sysemu/reset.h"
  39 #include "sysemu/runstate.h"
  40 #include "qom/object.h"
  41
  42 struct PIIX4State {
  43     PCIDevice dev;
  44     qemu_irq cpu_intr;
  45     qemu_irq *isa;
  46
  47     RTCState rtc;
  48     /* Reset Control Register */
  49     MemoryRegion rcr_mem;
  50     uint8_t rcr;
  51 };
  52
  53 OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
  54
  55 static void piix4_set_irq(void *opaque, int irq_num, int level)
  56 {
  57     int i, pic_irq, pic_level;
  58     PIIX4State *s = opaque;
  59     PCIBus *bus = pci_get_bus(&s->dev);
  60
  61     /* now we change the pic irq level according to the piix irq mappings */
  62     /* XXX: optimize */
  63     pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
  64     if (pic_irq < ISA_NUM_IRQS) {
  65         /* The pic level is the logical OR of all the PCI irqs mapped to it. */
  66         pic_level = 0;
  67         for (i = 0; i < PIIX_NUM_PIRQS; i++) {
  68             if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
  69                 pic_level |= pci_bus_get_irq_level(bus, i);
  70             }
  71         }
  72         qemu_set_irq(s->isa[pic_irq], pic_level);
  73     }
  74 }
  75
  76 static void piix4_isa_reset(DeviceState *dev)
  77 {
  78     PIIX4State *d = PIIX4_PCI_DEVICE(dev);
  79     uint8_t *pci_conf = d->dev.config;
  80
  81     pci_conf[0x04] = 0x07; // master, memory and I/O
  82     pci_conf[0x05] = 0x00;
  83     pci_conf[0x06] = 0x00;
  84     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
  85     pci_conf[0x4c] = 0x4d;
  86     pci_conf[0x4e] = 0x03;
  87     pci_conf[0x4f] = 0x00;
  88     pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
  89     pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
  90     pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
  91     pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
  92     pci_conf[0x69] = 0x02;
  93     pci_conf[0x70] = 0x80;
  94     pci_conf[0x76] = 0x0c;
  95     pci_conf[0x77] = 0x0c;
  96     pci_conf[0x78] = 0x02;
  97     pci_conf[0x79] = 0x00;
  98     pci_conf[0x80] = 0x00;
  99     pci_conf[0x82] = 0x00;
 100     pci_conf[0xa0] = 0x08;
 101     pci_conf[0xa2] = 0x00;
 102     pci_conf[0xa3] = 0x00;
 103     pci_conf[0xa4] = 0x00;
 104     pci_conf[0xa5] = 0x00;
 105     pci_conf[0xa6] = 0x00;
 106     pci_conf[0xa7] = 0x00;
 107     pci_conf[0xa8] = 0x0f;
 108     pci_conf[0xaa] = 0x00;
 109     pci_conf[0xab] = 0x00;
 110     pci_conf[0xac] = 0x00;
 111     pci_conf[0xae] = 0x00;
 112 }
 113
 114 static int piix4_ide_post_load(void *opaque, int version_id)
 115 {
 116     PIIX4State *s = opaque;
 117
 118     if (version_id == 2) {
 119         s->rcr = 0;
 120     }
 121
 122     return 0;
 123 }
 124
 125 static const VMStateDescription vmstate_piix4 = {
 126     .name = "PIIX4",
 127     .version_id = 3,
 128     .minimum_version_id = 2,
 129     .post_load = piix4_ide_post_load,
 130     .fields = (VMStateField[]) {
 131         VMSTATE_PCI_DEVICE(dev, PIIX4State),
 132         VMSTATE_UINT8_V(rcr, PIIX4State, 3),
 133         VMSTATE_END_OF_LIST()
 134     }
 135 };
 136
 137 static void piix4_request_i8259_irq(void *opaque, int irq, int level)
 138 {
 139     PIIX4State *s = opaque;
 140     qemu_set_irq(s->cpu_intr, level);
 141 }
 142
 143 static void piix4_set_i8259_irq(void *opaque, int irq, int level)
 144 {
 145     PIIX4State *s = opaque;
 146     qemu_set_irq(s->isa[irq], level);
 147 }
 148
 149 static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
 150                             unsigned int len)
 151 {
 152     PIIX4State *s = opaque;
 153
 154     if (val & 4) {
 155         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 156         return;
 157     }
 158
 159     s->rcr = val & 2; /* keep System Reset type only */
 160 }
 161
 162 static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
 163 {
 164     PIIX4State *s = opaque;
 165
 166     return s->rcr;
 167 }
 168
 169 static const MemoryRegionOps piix4_rcr_ops = {
 170     .read = piix4_rcr_read,
 171     .write = piix4_rcr_write,
 172     .endianness = DEVICE_LITTLE_ENDIAN,
 173     .impl = {
 174         .min_access_size = 1,
 175         .max_access_size = 1,
 176     },
 177 };
 178
 179 static void piix4_realize(PCIDevice *dev, Error **errp)
 180 {
 181     PIIX4State *s = PIIX4_PCI_DEVICE(dev);
 182     ISABus *isa_bus;
 183     qemu_irq *i8259_out_irq;
 184
 185     isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
 186                           pci_address_space_io(dev), errp);
 187     if (!isa_bus) {
 188         return;
 189     }
 190
 191     qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
 192                             "isa", ISA_NUM_IRQS);
 193     qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
 194                              "intr", 1);
 195
 196     memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
 197                           "reset-control", 1);
 198     memory_region_add_subregion_overlap(pci_address_space_io(dev),
 199                                         PIIX_RCR_IOPORT, &s->rcr_mem, 1);
 200
 201     /* initialize i8259 pic */
 202     i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
 203     s->isa = i8259_init(isa_bus, *i8259_out_irq);
 204
 205     /* initialize ISA irqs */
 206     isa_bus_irqs(isa_bus, s->isa);
 207
 208     /* initialize pit */
 209     i8254_pit_init(isa_bus, 0x40, 0, NULL);
 210
 211     /* DMA */
 212     i8257_dma_init(isa_bus, 0);
 213
 214     /* RTC */
 215     qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
 216     if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
 217         return;
 218     }
 219     s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq);
 220 }
 221
 222 static void piix4_init(Object *obj)
 223 {
 224     PIIX4State *s = PIIX4_PCI_DEVICE(obj);
 225
 226     object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
 227 }
 228
 229 static void piix4_class_init(ObjectClass *klass, void *data)
 230 {
 231     DeviceClass *dc = DEVICE_CLASS(klass);
 232     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 233
 234     k->realize = piix4_realize;
 235     k->vendor_id = PCI_VENDOR_ID_INTEL;
 236     k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
 237     k->class_id = PCI_CLASS_BRIDGE_ISA;
 238     dc->reset = piix4_isa_reset;
 239     dc->desc = "ISA bridge";
 240     dc->vmsd = &vmstate_piix4;
 241     /*
 242      * Reason: part of PIIX4 southbridge, needs to be wired up,
 243      * e.g. by mips_malta_init()
 244      */
 245     dc->user_creatable = false;
 246     dc->hotpluggable = false;
 247 }
 248
 249 static const TypeInfo piix4_info = {
 250     .name          = TYPE_PIIX4_PCI_DEVICE,
 251     .parent        = TYPE_PCI_DEVICE,
 252     .instance_size = sizeof(PIIX4State),
 253     .instance_init = piix4_init,
 254     .class_init    = piix4_class_init,
 255     .interfaces = (InterfaceInfo[]) {
 256         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 257         { },
 258     },
 259 };
 260
 261 static void piix4_register_types(void)
 262 {
 263     type_register_static(&piix4_info);
 264 }
 265
 266 type_init(piix4_register_types)
 267
 268 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
 269 {
 270     int slot;
 271
 272     slot = PCI_SLOT(pci_dev->devfn);
 273
 274     switch (slot) {
 275     /* PIIX4 USB */
 276     case 10:
 277         return 3;
 278     /* AMD 79C973 Ethernet */
 279     case 11:
 280         return 1;
 281     /* Crystal 4281 Sound */
 282     case 12:
 283         return 2;
 284     /* PCI slot 1 to 4 */
 285     case 18 ... 21:
 286         return ((slot - 18) + irq_num) & 0x03;
 287     /* Unknown device, don't do any translation */
 288     default:
 289         return irq_num;
 290     }
 291 }
 292
 293 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
 294 {
 295     PIIX4State *s;
 296     PCIDevice *pci;
 297     DeviceState *dev;
 298     int devfn = PCI_DEVFN(10, 0);
 299
 300     pci = pci_create_simple_multifunction(pci_bus, devfn,  true,
 301                                           TYPE_PIIX4_PCI_DEVICE);
 302     dev = DEVICE(pci);
 303     s = PIIX4_PCI_DEVICE(pci);
 304     if (isa_bus) {
 305         *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
 306     }
 307
 308     pci = pci_create_simple(pci_bus, devfn + 1, "piix4-ide");
 309     pci_ide_create_devs(pci);
 310
 311     pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
 312     if (smbus) {
 313         *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
 314                                qdev_get_gpio_in_named(dev, "isa", 9),
 315                                NULL, 0, NULL);
 316     }
 317
 318     pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
 319
 320     return dev;
 321 }