2 * VT82C686B south bridge support
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
7 * This code is licensed under the GNU GPL v2.
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
13 #include "qemu/osdep.h"
14 #include "hw/isa/vt82c686.h"
15 #include "hw/i2c/i2c.h"
16 #include "hw/pci/pci.h"
17 #include "hw/qdev-properties.h"
18 #include "hw/isa/isa.h"
19 #include "hw/isa/superio.h"
20 #include "hw/sysbus.h"
21 #include "migration/vmstate.h"
22 #include "hw/mips/mips.h"
23 #include "hw/isa/apm.h"
24 #include "hw/acpi/acpi.h"
25 #include "hw/i2c/pm_smbus.h"
26 #include "sysemu/reset.h"
27 #include "sysemu/sysemu.h"
28 #include "qemu/module.h"
29 #include "qemu/timer.h"
30 #include "exec/address-spaces.h"
32 //#define DEBUG_VT82C686B
34 #ifdef DEBUG_VT82C686B
35 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
37 #define DPRINTF(fmt, ...)
40 typedef struct SuperIOConfig
42 uint8_t config
[0x100];
47 typedef struct VT82C686BState
{
50 SuperIOConfig superio_conf
;
53 #define TYPE_VT82C686B_DEVICE "VT82C686B"
54 #define VT82C686B_DEVICE(obj) \
55 OBJECT_CHECK(VT82C686BState, (obj), TYPE_VT82C686B_DEVICE)
57 static void superio_ioport_writeb(void *opaque
, hwaddr addr
, uint64_t data
,
60 SuperIOConfig
*superio_conf
= opaque
;
62 DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr
, data
);
64 superio_conf
->index
= data
& 0xff;
66 bool can_write
= true;
68 switch (superio_conf
->index
) {
81 if ((data
& 0xff) != 0xfe) {
82 DPRINTF("change uart 1 base. unsupported yet\n");
87 if ((data
& 0xff) != 0xbe) {
88 DPRINTF("change uart 2 base. unsupported yet\n");
97 superio_conf
->config
[superio_conf
->index
] = data
& 0xff;
102 static uint64_t superio_ioport_readb(void *opaque
, hwaddr addr
, unsigned size
)
104 SuperIOConfig
*superio_conf
= opaque
;
106 DPRINTF("superio_ioport_readb address 0x%x\n", addr
);
107 return (superio_conf
->config
[superio_conf
->index
]);
110 static const MemoryRegionOps superio_ops
= {
111 .read
= superio_ioport_readb
,
112 .write
= superio_ioport_writeb
,
113 .endianness
= DEVICE_NATIVE_ENDIAN
,
115 .min_access_size
= 1,
116 .max_access_size
= 1,
120 static void vt82c686b_reset(void * opaque
)
122 PCIDevice
*d
= opaque
;
123 uint8_t *pci_conf
= d
->config
;
124 VT82C686BState
*vt82c
= VT82C686B_DEVICE(d
);
126 pci_set_long(pci_conf
+ PCI_CAPABILITY_LIST
, 0x000000c0);
127 pci_set_word(pci_conf
+ PCI_COMMAND
, PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
128 PCI_COMMAND_MASTER
| PCI_COMMAND_SPECIAL
);
129 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
);
131 pci_conf
[0x48] = 0x01; /* Miscellaneous Control 3 */
132 pci_conf
[0x4a] = 0x04; /* IDE interrupt Routing */
133 pci_conf
[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
134 pci_conf
[0x50] = 0x2d; /* PnP DMA Request Control */
135 pci_conf
[0x59] = 0x04;
136 pci_conf
[0x5a] = 0x04; /* KBC/RTC Control*/
137 pci_conf
[0x5f] = 0x04;
138 pci_conf
[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
140 vt82c
->superio_conf
.config
[0xe0] = 0x3c;
141 vt82c
->superio_conf
.config
[0xe2] = 0x03;
142 vt82c
->superio_conf
.config
[0xe3] = 0xfc;
143 vt82c
->superio_conf
.config
[0xe6] = 0xde;
144 vt82c
->superio_conf
.config
[0xe7] = 0xfe;
145 vt82c
->superio_conf
.config
[0xe8] = 0xbe;
148 /* write config pci function0 registers. PCI-ISA bridge */
149 static void vt82c686b_write_config(PCIDevice
* d
, uint32_t address
,
150 uint32_t val
, int len
)
152 VT82C686BState
*vt686
= VT82C686B_DEVICE(d
);
154 DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
157 pci_default_write_config(d
, address
, val
, len
);
158 if (address
== 0x85) { /* enable or disable super IO configure */
159 memory_region_set_enabled(&vt686
->superio
, val
& 0x2);
163 #define ACPI_DBG_IO_ADDR 0xb044
165 typedef struct VT686PMState
{
171 uint32_t smb_io_base
;
174 typedef struct VT686AC97State
{
178 typedef struct VT686MC97State
{
182 #define TYPE_VT82C686B_PM_DEVICE "VT82C686B_PM"
183 #define VT82C686B_PM_DEVICE(obj) \
184 OBJECT_CHECK(VT686PMState, (obj), TYPE_VT82C686B_PM_DEVICE)
186 #define TYPE_VT82C686B_MC97_DEVICE "VT82C686B_MC97"
187 #define VT82C686B_MC97_DEVICE(obj) \
188 OBJECT_CHECK(VT686MC97State, (obj), TYPE_VT82C686B_MC97_DEVICE)
190 #define TYPE_VT82C686B_AC97_DEVICE "VT82C686B_AC97"
191 #define VT82C686B_AC97_DEVICE(obj) \
192 OBJECT_CHECK(VT686AC97State, (obj), TYPE_VT82C686B_AC97_DEVICE)
194 static void pm_update_sci(VT686PMState
*s
)
196 int sci_level
, pmsts
;
198 pmsts
= acpi_pm1_evt_get_sts(&s
->ar
);
199 sci_level
= (((pmsts
& s
->ar
.pm1
.evt
.en
) &
200 (ACPI_BITMASK_RT_CLOCK_ENABLE
|
201 ACPI_BITMASK_POWER_BUTTON_ENABLE
|
202 ACPI_BITMASK_GLOBAL_LOCK_ENABLE
|
203 ACPI_BITMASK_TIMER_ENABLE
)) != 0);
204 pci_set_irq(&s
->dev
, sci_level
);
205 /* schedule a timer interruption if needed */
206 acpi_pm_tmr_update(&s
->ar
, (s
->ar
.pm1
.evt
.en
& ACPI_BITMASK_TIMER_ENABLE
) &&
207 !(pmsts
& ACPI_BITMASK_TIMER_STATUS
));
210 static void pm_tmr_timer(ACPIREGS
*ar
)
212 VT686PMState
*s
= container_of(ar
, VT686PMState
, ar
);
216 static void pm_io_space_update(VT686PMState
*s
)
220 pm_io_base
= pci_get_long(s
->dev
.config
+ 0x40);
221 pm_io_base
&= 0xffc0;
223 memory_region_transaction_begin();
224 memory_region_set_enabled(&s
->io
, s
->dev
.config
[0x80] & 1);
225 memory_region_set_address(&s
->io
, pm_io_base
);
226 memory_region_transaction_commit();
229 static void pm_write_config(PCIDevice
*d
,
230 uint32_t address
, uint32_t val
, int len
)
232 DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
234 pci_default_write_config(d
, address
, val
, len
);
237 static int vmstate_acpi_post_load(void *opaque
, int version_id
)
239 VT686PMState
*s
= opaque
;
241 pm_io_space_update(s
);
245 static const VMStateDescription vmstate_acpi
= {
246 .name
= "vt82c686b_pm",
248 .minimum_version_id
= 1,
249 .post_load
= vmstate_acpi_post_load
,
250 .fields
= (VMStateField
[]) {
251 VMSTATE_PCI_DEVICE(dev
, VT686PMState
),
252 VMSTATE_UINT16(ar
.pm1
.evt
.sts
, VT686PMState
),
253 VMSTATE_UINT16(ar
.pm1
.evt
.en
, VT686PMState
),
254 VMSTATE_UINT16(ar
.pm1
.cnt
.cnt
, VT686PMState
),
255 VMSTATE_STRUCT(apm
, VT686PMState
, 0, vmstate_apm
, APMState
),
256 VMSTATE_TIMER_PTR(ar
.tmr
.timer
, VT686PMState
),
257 VMSTATE_INT64(ar
.tmr
.overflow_time
, VT686PMState
),
258 VMSTATE_END_OF_LIST()
263 * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
264 * just register a PCI device now, functionalities will be implemented later.
267 static void vt82c686b_ac97_realize(PCIDevice
*dev
, Error
**errp
)
269 VT686AC97State
*s
= VT82C686B_AC97_DEVICE(dev
);
270 uint8_t *pci_conf
= s
->dev
.config
;
272 pci_set_word(pci_conf
+ PCI_COMMAND
, PCI_COMMAND_INVALIDATE
|
274 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_CAP_LIST
|
275 PCI_STATUS_DEVSEL_MEDIUM
);
276 pci_set_long(pci_conf
+ PCI_INTERRUPT_PIN
, 0x03);
279 void vt82c686b_ac97_init(PCIBus
*bus
, int devfn
)
283 dev
= pci_create(bus
, devfn
, TYPE_VT82C686B_AC97_DEVICE
);
284 qdev_init_nofail(&dev
->qdev
);
287 static void via_ac97_class_init(ObjectClass
*klass
, void *data
)
289 DeviceClass
*dc
= DEVICE_CLASS(klass
);
290 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
292 k
->realize
= vt82c686b_ac97_realize
;
293 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
294 k
->device_id
= PCI_DEVICE_ID_VIA_AC97
;
296 k
->class_id
= PCI_CLASS_MULTIMEDIA_AUDIO
;
297 set_bit(DEVICE_CATEGORY_SOUND
, dc
->categories
);
301 static const TypeInfo via_ac97_info
= {
302 .name
= TYPE_VT82C686B_AC97_DEVICE
,
303 .parent
= TYPE_PCI_DEVICE
,
304 .instance_size
= sizeof(VT686AC97State
),
305 .class_init
= via_ac97_class_init
,
306 .interfaces
= (InterfaceInfo
[]) {
307 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
312 static void vt82c686b_mc97_realize(PCIDevice
*dev
, Error
**errp
)
314 VT686MC97State
*s
= VT82C686B_MC97_DEVICE(dev
);
315 uint8_t *pci_conf
= s
->dev
.config
;
317 pci_set_word(pci_conf
+ PCI_COMMAND
, PCI_COMMAND_INVALIDATE
|
318 PCI_COMMAND_VGA_PALETTE
);
319 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_DEVSEL_MEDIUM
);
320 pci_set_long(pci_conf
+ PCI_INTERRUPT_PIN
, 0x03);
323 void vt82c686b_mc97_init(PCIBus
*bus
, int devfn
)
327 dev
= pci_create(bus
, devfn
, TYPE_VT82C686B_MC97_DEVICE
);
328 qdev_init_nofail(&dev
->qdev
);
331 static void via_mc97_class_init(ObjectClass
*klass
, void *data
)
333 DeviceClass
*dc
= DEVICE_CLASS(klass
);
334 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
336 k
->realize
= vt82c686b_mc97_realize
;
337 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
338 k
->device_id
= PCI_DEVICE_ID_VIA_MC97
;
339 k
->class_id
= PCI_CLASS_COMMUNICATION_OTHER
;
341 set_bit(DEVICE_CATEGORY_NETWORK
, dc
->categories
);
345 static const TypeInfo via_mc97_info
= {
346 .name
= TYPE_VT82C686B_MC97_DEVICE
,
347 .parent
= TYPE_PCI_DEVICE
,
348 .instance_size
= sizeof(VT686MC97State
),
349 .class_init
= via_mc97_class_init
,
350 .interfaces
= (InterfaceInfo
[]) {
351 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
356 /* vt82c686 pm init */
357 static void vt82c686b_pm_realize(PCIDevice
*dev
, Error
**errp
)
359 VT686PMState
*s
= VT82C686B_PM_DEVICE(dev
);
362 pci_conf
= s
->dev
.config
;
363 pci_set_word(pci_conf
+ PCI_COMMAND
, 0);
364 pci_set_word(pci_conf
+ PCI_STATUS
, PCI_STATUS_FAST_BACK
|
365 PCI_STATUS_DEVSEL_MEDIUM
);
367 /* 0x48-0x4B is Power Management I/O Base */
368 pci_set_long(pci_conf
+ 0x48, 0x00000001);
370 /* SMB ports:0xeee0~0xeeef */
371 s
->smb_io_base
=((s
->smb_io_base
& 0xfff0) + 0x0);
372 pci_conf
[0x90] = s
->smb_io_base
| 1;
373 pci_conf
[0x91] = s
->smb_io_base
>> 8;
374 pci_conf
[0xd2] = 0x90;
375 pm_smbus_init(DEVICE(s
), &s
->smb
, false);
376 memory_region_add_subregion(get_system_io(), s
->smb_io_base
, &s
->smb
.io
);
378 apm_init(dev
, &s
->apm
, NULL
, s
);
380 memory_region_init(&s
->io
, OBJECT(dev
), "vt82c686-pm", 64);
381 memory_region_set_enabled(&s
->io
, false);
382 memory_region_add_subregion(get_system_io(), 0, &s
->io
);
384 acpi_pm_tmr_init(&s
->ar
, pm_tmr_timer
, &s
->io
);
385 acpi_pm1_evt_init(&s
->ar
, pm_tmr_timer
, &s
->io
);
386 acpi_pm1_cnt_init(&s
->ar
, &s
->io
, false, false, 2);
389 I2CBus
*vt82c686b_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
395 dev
= pci_create(bus
, devfn
, TYPE_VT82C686B_PM_DEVICE
);
396 qdev_prop_set_uint32(&dev
->qdev
, "smb_io_base", smb_io_base
);
398 s
= VT82C686B_PM_DEVICE(dev
);
400 qdev_init_nofail(&dev
->qdev
);
405 static Property via_pm_properties
[] = {
406 DEFINE_PROP_UINT32("smb_io_base", VT686PMState
, smb_io_base
, 0),
407 DEFINE_PROP_END_OF_LIST(),
410 static void via_pm_class_init(ObjectClass
*klass
, void *data
)
412 DeviceClass
*dc
= DEVICE_CLASS(klass
);
413 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
415 k
->realize
= vt82c686b_pm_realize
;
416 k
->config_write
= pm_write_config
;
417 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
418 k
->device_id
= PCI_DEVICE_ID_VIA_ACPI
;
419 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
422 dc
->vmsd
= &vmstate_acpi
;
423 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
424 dc
->props
= via_pm_properties
;
427 static const TypeInfo via_pm_info
= {
428 .name
= TYPE_VT82C686B_PM_DEVICE
,
429 .parent
= TYPE_PCI_DEVICE
,
430 .instance_size
= sizeof(VT686PMState
),
431 .class_init
= via_pm_class_init
,
432 .interfaces
= (InterfaceInfo
[]) {
433 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
438 static const VMStateDescription vmstate_via
= {
441 .minimum_version_id
= 1,
442 .fields
= (VMStateField
[]) {
443 VMSTATE_PCI_DEVICE(dev
, VT82C686BState
),
444 VMSTATE_END_OF_LIST()
448 /* init the PCI-to-ISA bridge */
449 static void vt82c686b_realize(PCIDevice
*d
, Error
**errp
)
451 VT82C686BState
*vt82c
= VT82C686B_DEVICE(d
);
457 isa_bus
= isa_bus_new(DEVICE(d
), get_system_memory(),
458 pci_address_space_io(d
), errp
);
463 pci_conf
= d
->config
;
464 pci_config_set_prog_interface(pci_conf
, 0x0);
467 for (i
= 0x00; i
< 0xff; i
++) {
468 if (i
<=0x03 || (i
>=0x08 && i
<=0x3f)) {
473 memory_region_init_io(&vt82c
->superio
, OBJECT(d
), &superio_ops
,
474 &vt82c
->superio_conf
, "superio", 2);
475 memory_region_set_enabled(&vt82c
->superio
, false);
476 /* The floppy also uses 0x3f0 and 0x3f1.
477 * But we do not emulate a floppy, so just set it here. */
478 memory_region_add_subregion(isa_bus
->address_space_io
, 0x3f0,
481 qemu_register_reset(vt82c686b_reset
, d
);
484 ISABus
*vt82c686b_isa_init(PCIBus
*bus
, int devfn
)
488 d
= pci_create_simple_multifunction(bus
, devfn
, true,
489 TYPE_VT82C686B_DEVICE
);
491 return ISA_BUS(qdev_get_child_bus(DEVICE(d
), "isa.0"));
494 static void via_class_init(ObjectClass
*klass
, void *data
)
496 DeviceClass
*dc
= DEVICE_CLASS(klass
);
497 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
499 k
->realize
= vt82c686b_realize
;
500 k
->config_write
= vt82c686b_write_config
;
501 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
502 k
->device_id
= PCI_DEVICE_ID_VIA_ISA_BRIDGE
;
503 k
->class_id
= PCI_CLASS_BRIDGE_ISA
;
505 dc
->desc
= "ISA bridge";
506 dc
->vmsd
= &vmstate_via
;
508 * Reason: part of VIA VT82C686 southbridge, needs to be wired up,
509 * e.g. by mips_fulong2e_init()
511 dc
->user_creatable
= false;
514 static const TypeInfo via_info
= {
515 .name
= TYPE_VT82C686B_DEVICE
,
516 .parent
= TYPE_PCI_DEVICE
,
517 .instance_size
= sizeof(VT82C686BState
),
518 .class_init
= via_class_init
,
519 .interfaces
= (InterfaceInfo
[]) {
520 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
525 static void vt82c686b_superio_class_init(ObjectClass
*klass
, void *data
)
527 ISASuperIOClass
*sc
= ISA_SUPERIO_CLASS(klass
);
529 sc
->serial
.count
= 2;
530 sc
->parallel
.count
= 1;
532 sc
->floppy
.count
= 1;
535 static const TypeInfo via_superio_info
= {
536 .name
= TYPE_VT82C686B_SUPERIO
,
537 .parent
= TYPE_ISA_SUPERIO
,
538 .instance_size
= sizeof(ISASuperIODevice
),
539 .class_size
= sizeof(ISASuperIOClass
),
540 .class_init
= vt82c686b_superio_class_init
,
543 static void vt82c686b_register_types(void)
545 type_register_static(&via_ac97_info
);
546 type_register_static(&via_mc97_info
);
547 type_register_static(&via_pm_info
);
548 type_register_static(&via_superio_info
);
549 type_register_static(&via_info
);
552 type_init(vt82c686b_register_types
)