hw/lm32/lm32_boards.c

   1 /*
   2  *  QEMU models for LatticeMico32 uclinux and evr32 boards.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qemu-common.h"
  22 #include "cpu.h"
  23 #include "hw/sysbus.h"
  24 #include "hw/hw.h"
  25 #include "hw/block/flash.h"
  26 #include "hw/devices.h"
  27 #include "hw/boards.h"
  28 #include "hw/loader.h"
  29 #include "sysemu/block-backend.h"
  30 #include "elf.h"
  31 #include "lm32_hwsetup.h"
  32 #include "lm32.h"
  33 #include "exec/address-spaces.h"
  34
  35 typedef struct {
  36     LM32CPU *cpu;
  37     hwaddr bootstrap_pc;
  38     hwaddr flash_base;
  39     hwaddr hwsetup_base;
  40     hwaddr initrd_base;
  41     size_t initrd_size;
  42     hwaddr cmdline_base;
  43 } ResetInfo;
  44
  45 static void cpu_irq_handler(void *opaque, int irq, int level)
  46 {
  47     LM32CPU *cpu = opaque;
  48     CPUState *cs = CPU(cpu);
  49
  50     if (level) {
  51         cpu_interrupt(cs, CPU_INTERRUPT_HARD);
  52     } else {
  53         cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
  54     }
  55 }
  56
  57 static void main_cpu_reset(void *opaque)
  58 {
  59     ResetInfo *reset_info = opaque;
  60     CPULM32State *env = &reset_info->cpu->env;
  61
  62     cpu_reset(CPU(reset_info->cpu));
  63
  64     /* init defaults */
  65     env->pc = (uint32_t)reset_info->bootstrap_pc;
  66     env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
  67     env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
  68     env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
  69     env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
  70         reset_info->initrd_size);
  71     env->eba = reset_info->flash_base;
  72     env->deba = reset_info->flash_base;
  73 }
  74
  75 static void lm32_evr_init(MachineState *machine)
  76 {
  77     const char *cpu_model = machine->cpu_model;
  78     const char *kernel_filename = machine->kernel_filename;
  79     LM32CPU *cpu;
  80     CPULM32State *env;
  81     DriveInfo *dinfo;
  82     MemoryRegion *address_space_mem =  get_system_memory();
  83     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
  84     qemu_irq irq[32];
  85     ResetInfo *reset_info;
  86     int i;
  87
  88     /* memory map */
  89     hwaddr flash_base  = 0x04000000;
  90     size_t flash_sector_size       = 256 * 1024;
  91     size_t flash_size              = 32 * 1024 * 1024;
  92     hwaddr ram_base    = 0x08000000;
  93     size_t ram_size                = 64 * 1024 * 1024;
  94     hwaddr timer0_base = 0x80002000;
  95     hwaddr uart0_base  = 0x80006000;
  96     hwaddr timer1_base = 0x8000a000;
  97     int uart0_irq                  = 0;
  98     int timer0_irq                 = 1;
  99     int timer1_irq                 = 3;
 100
 101     reset_info = g_malloc0(sizeof(ResetInfo));
 102
 103     if (cpu_model == NULL) {
 104         cpu_model = "lm32-full";
 105     }
 106     cpu = cpu_lm32_init(cpu_model);
 107     if (cpu == NULL) {
 108         fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
 109         exit(1);
 110     }
 111
 112     env = &cpu->env;
 113     reset_info->cpu = cpu;
 114
 115     reset_info->flash_base = flash_base;
 116
 117     memory_region_allocate_system_memory(phys_ram, NULL, "lm32_evr.sdram",
 118                                          ram_size);
 119     memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
 120
 121     dinfo = drive_get(IF_PFLASH, 0, 0);
 122     /* Spansion S29NS128P */
 123     pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
 124                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 125                           flash_sector_size, flash_size / flash_sector_size,
 126                           1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 127
 128     /* create irq lines */
 129     env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, cpu, 0));
 130     for (i = 0; i < 32; i++) {
 131         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 132     }
 133
 134     sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
 135     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 136     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 137
 138     /* make sure juart isn't the first chardev */
 139     env->juart_state = lm32_juart_init();
 140
 141     reset_info->bootstrap_pc = flash_base;
 142
 143     if (kernel_filename) {
 144         uint64_t entry;
 145         int kernel_size;
 146
 147         kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
 148                                1, EM_LATTICEMICO32, 0, 0);
 149         reset_info->bootstrap_pc = entry;
 150
 151         if (kernel_size < 0) {
 152             kernel_size = load_image_targphys(kernel_filename, ram_base,
 153                                               ram_size);
 154             reset_info->bootstrap_pc = ram_base;
 155         }
 156
 157         if (kernel_size < 0) {
 158             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 159                     kernel_filename);
 160             exit(1);
 161         }
 162     }
 163
 164     qemu_register_reset(main_cpu_reset, reset_info);
 165 }
 166
 167 static void lm32_uclinux_init(MachineState *machine)
 168 {
 169     const char *cpu_model = machine->cpu_model;
 170     const char *kernel_filename = machine->kernel_filename;
 171     const char *kernel_cmdline = machine->kernel_cmdline;
 172     const char *initrd_filename = machine->initrd_filename;
 173     LM32CPU *cpu;
 174     CPULM32State *env;
 175     DriveInfo *dinfo;
 176     MemoryRegion *address_space_mem =  get_system_memory();
 177     MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
 178     qemu_irq irq[32];
 179     HWSetup *hw;
 180     ResetInfo *reset_info;
 181     int i;
 182
 183     /* memory map */
 184     hwaddr flash_base   = 0x04000000;
 185     size_t flash_sector_size        = 256 * 1024;
 186     size_t flash_size               = 32 * 1024 * 1024;
 187     hwaddr ram_base     = 0x08000000;
 188     size_t ram_size                 = 64 * 1024 * 1024;
 189     hwaddr uart0_base   = 0x80000000;
 190     hwaddr timer0_base  = 0x80002000;
 191     hwaddr timer1_base  = 0x80010000;
 192     hwaddr timer2_base  = 0x80012000;
 193     int uart0_irq                   = 0;
 194     int timer0_irq                  = 1;
 195     int timer1_irq                  = 20;
 196     int timer2_irq                  = 21;
 197     hwaddr hwsetup_base = 0x0bffe000;
 198     hwaddr cmdline_base = 0x0bfff000;
 199     hwaddr initrd_base  = 0x08400000;
 200     size_t initrd_max               = 0x01000000;
 201
 202     reset_info = g_malloc0(sizeof(ResetInfo));
 203
 204     if (cpu_model == NULL) {
 205         cpu_model = "lm32-full";
 206     }
 207     cpu = cpu_lm32_init(cpu_model);
 208     if (cpu == NULL) {
 209         fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
 210         exit(1);
 211     }
 212
 213     env = &cpu->env;
 214     reset_info->cpu = cpu;
 215
 216     reset_info->flash_base = flash_base;
 217
 218     memory_region_allocate_system_memory(phys_ram, NULL,
 219                                          "lm32_uclinux.sdram", ram_size);
 220     memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
 221
 222     dinfo = drive_get(IF_PFLASH, 0, 0);
 223     /* Spansion S29NS128P */
 224     pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
 225                           dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
 226                           flash_sector_size, flash_size / flash_sector_size,
 227                           1, 2, 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
 228
 229     /* create irq lines */
 230     env->pic_state = lm32_pic_init(qemu_allocate_irq(cpu_irq_handler, env, 0));
 231     for (i = 0; i < 32; i++) {
 232         irq[i] = qdev_get_gpio_in(env->pic_state, i);
 233     }
 234
 235     sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
 236     sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
 237     sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
 238     sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
 239
 240     /* make sure juart isn't the first chardev */
 241     env->juart_state = lm32_juart_init();
 242
 243     reset_info->bootstrap_pc = flash_base;
 244
 245     if (kernel_filename) {
 246         uint64_t entry;
 247         int kernel_size;
 248
 249         kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
 250                                1, EM_LATTICEMICO32, 0, 0);
 251         reset_info->bootstrap_pc = entry;
 252
 253         if (kernel_size < 0) {
 254             kernel_size = load_image_targphys(kernel_filename, ram_base,
 255                                               ram_size);
 256             reset_info->bootstrap_pc = ram_base;
 257         }
 258
 259         if (kernel_size < 0) {
 260             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 261                     kernel_filename);
 262             exit(1);
 263         }
 264     }
 265
 266     /* generate a rom with the hardware description */
 267     hw = hwsetup_init();
 268     hwsetup_add_cpu(hw, "LM32", 75000000);
 269     hwsetup_add_flash(hw, "flash", flash_base, flash_size);
 270     hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
 271     hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
 272     hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
 273     hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
 274     hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
 275     hwsetup_add_trailer(hw);
 276     hwsetup_create_rom(hw, hwsetup_base);
 277     hwsetup_free(hw);
 278
 279     reset_info->hwsetup_base = hwsetup_base;
 280
 281     if (kernel_cmdline && strlen(kernel_cmdline)) {
 282         pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
 283                 kernel_cmdline);
 284         reset_info->cmdline_base = cmdline_base;
 285     }
 286
 287     if (initrd_filename) {
 288         size_t initrd_size;
 289         initrd_size = load_image_targphys(initrd_filename, initrd_base,
 290                 initrd_max);
 291         reset_info->initrd_base = initrd_base;
 292         reset_info->initrd_size = initrd_size;
 293     }
 294
 295     qemu_register_reset(main_cpu_reset, reset_info);
 296 }
 297
 298 static void lm32_evr_class_init(ObjectClass *oc, void *data)
 299 {
 300     MachineClass *mc = MACHINE_CLASS(oc);
 301
 302     mc->desc = "LatticeMico32 EVR32 eval system";
 303     mc->init = lm32_evr_init;
 304     mc->is_default = 1;
 305 }
 306
 307 static const TypeInfo lm32_evr_type = {
 308     .name = MACHINE_TYPE_NAME("lm32-evr"),
 309     .parent = TYPE_MACHINE,
 310     .class_init = lm32_evr_class_init,
 311 };
 312
 313 static void lm32_uclinux_class_init(ObjectClass *oc, void *data)
 314 {
 315     MachineClass *mc = MACHINE_CLASS(oc);
 316
 317     mc->desc = "lm32 platform for uClinux and u-boot by Theobroma Systems";
 318     mc->init = lm32_uclinux_init;
 319     mc->is_default = 0;
 320 }
 321
 322 static const TypeInfo lm32_uclinux_type = {
 323     .name = MACHINE_TYPE_NAME("lm32-uclinux"),
 324     .parent = TYPE_MACHINE,
 325     .class_init = lm32_uclinux_class_init,
 326 };
 327
 328 static void lm32_machine_init(void)
 329 {
 330     type_register_static(&lm32_evr_type);
 331     type_register_static(&lm32_uclinux_type);
 332 }
 333
 334 type_init(lm32_machine_init)