2 * QEMU model of the LatticeMico32 timer block.
4 * Copyright (c) 2010 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 * Specification available at:
21 * http://www.latticesemi.com/documents/mico32timer.pdf
27 #include "qemu-timer.h"
28 #include "qemu-error.h"
30 #define DEFAULT_FREQUENCY (50*1000000)
52 struct LM32TimerState
{
64 typedef struct LM32TimerState LM32TimerState
;
66 static void timer_update_irq(LM32TimerState
*s
)
68 int state
= (s
->regs
[R_SR
] & SR_TO
) && (s
->regs
[R_CR
] & CR_ITO
);
70 trace_lm32_timer_irq_state(state
);
71 qemu_set_irq(s
->irq
, state
);
74 static uint64_t timer_read(void *opaque
, target_phys_addr_t addr
, unsigned size
)
76 LM32TimerState
*s
= opaque
;
87 r
= (uint32_t)ptimer_get_count(s
->ptimer
);
90 error_report("lm32_timer: read access to unknown register 0x"
91 TARGET_FMT_plx
, addr
<< 2);
95 trace_lm32_timer_memory_read(addr
<< 2, r
);
99 static void timer_write(void *opaque
, target_phys_addr_t addr
,
100 uint64_t value
, unsigned size
)
102 LM32TimerState
*s
= opaque
;
104 trace_lm32_timer_memory_write(addr
, value
);
109 s
->regs
[R_SR
] &= ~SR_TO
;
112 s
->regs
[R_CR
] = value
;
113 if (s
->regs
[R_CR
] & CR_START
) {
114 ptimer_run(s
->ptimer
, 1);
116 if (s
->regs
[R_CR
] & CR_STOP
) {
117 ptimer_stop(s
->ptimer
);
121 s
->regs
[R_PERIOD
] = value
;
122 ptimer_set_count(s
->ptimer
, value
);
125 error_report("lm32_timer: write access to read only register 0x"
126 TARGET_FMT_plx
, addr
<< 2);
129 error_report("lm32_timer: write access to unknown register 0x"
130 TARGET_FMT_plx
, addr
<< 2);
136 static const MemoryRegionOps timer_ops
= {
138 .write
= timer_write
,
139 .endianness
= DEVICE_NATIVE_ENDIAN
,
141 .min_access_size
= 4,
142 .max_access_size
= 4,
146 static void timer_hit(void *opaque
)
148 LM32TimerState
*s
= opaque
;
150 trace_lm32_timer_hit();
152 s
->regs
[R_SR
] |= SR_TO
;
154 if (s
->regs
[R_CR
] & CR_CONT
) {
155 ptimer_set_count(s
->ptimer
, s
->regs
[R_PERIOD
]);
156 ptimer_run(s
->ptimer
, 1);
161 static void timer_reset(DeviceState
*d
)
163 LM32TimerState
*s
= container_of(d
, LM32TimerState
, busdev
.qdev
);
166 for (i
= 0; i
< R_MAX
; i
++) {
169 ptimer_stop(s
->ptimer
);
172 static int lm32_timer_init(SysBusDevice
*dev
)
174 LM32TimerState
*s
= FROM_SYSBUS(typeof(*s
), dev
);
176 sysbus_init_irq(dev
, &s
->irq
);
178 s
->bh
= qemu_bh_new(timer_hit
, s
);
179 s
->ptimer
= ptimer_init(s
->bh
);
180 ptimer_set_freq(s
->ptimer
, s
->freq_hz
);
182 memory_region_init_io(&s
->iomem
, &timer_ops
, s
, "timer", R_MAX
* 4);
183 sysbus_init_mmio(dev
, &s
->iomem
);
188 static const VMStateDescription vmstate_lm32_timer
= {
189 .name
= "lm32-timer",
191 .minimum_version_id
= 1,
192 .minimum_version_id_old
= 1,
193 .fields
= (VMStateField
[]) {
194 VMSTATE_PTIMER(ptimer
, LM32TimerState
),
195 VMSTATE_UINT32(freq_hz
, LM32TimerState
),
196 VMSTATE_UINT32_ARRAY(regs
, LM32TimerState
, R_MAX
),
197 VMSTATE_END_OF_LIST()
201 static SysBusDeviceInfo lm32_timer_info
= {
202 .init
= lm32_timer_init
,
203 .qdev
.name
= "lm32-timer",
204 .qdev
.size
= sizeof(LM32TimerState
),
205 .qdev
.vmsd
= &vmstate_lm32_timer
,
206 .qdev
.reset
= timer_reset
,
207 .qdev
.props
= (Property
[]) {
209 "frequency", LM32TimerState
, freq_hz
, DEFAULT_FREQUENCY
211 DEFINE_PROP_END_OF_LIST(),
215 static void lm32_timer_register(void)
217 sysbus_register_withprop(&lm32_timer_info
);
220 device_init(lm32_timer_register
)