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lsi: move current_dev into lsi_request
[mirror_qemu.git] / hw / lsi53c895a.c
1 /*
2 * QEMU LSI53C895A SCSI Host Bus Adapter emulation
3 *
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licenced under the LGPL.
8 */
9
10 /* ??? Need to check if the {read,write}[wl] routines work properly on
11 big-endian targets. */
12
13 #include <assert.h>
14
15 #include "hw.h"
16 #include "pci.h"
17 #include "scsi.h"
18 #include "block_int.h"
19
20 //#define DEBUG_LSI
21 //#define DEBUG_LSI_REG
22
23 #ifdef DEBUG_LSI
24 #define DPRINTF(fmt, ...) \
25 do { printf("lsi_scsi: " fmt , ## __VA_ARGS__); } while (0)
26 #define BADF(fmt, ...) \
27 do { fprintf(stderr, "lsi_scsi: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
28 #else
29 #define DPRINTF(fmt, ...) do {} while(0)
30 #define BADF(fmt, ...) \
31 do { fprintf(stderr, "lsi_scsi: error: " fmt , ## __VA_ARGS__);} while (0)
32 #endif
33
34 #define LSI_MAX_DEVS 7
35
36 #define LSI_SCNTL0_TRG 0x01
37 #define LSI_SCNTL0_AAP 0x02
38 #define LSI_SCNTL0_EPC 0x08
39 #define LSI_SCNTL0_WATN 0x10
40 #define LSI_SCNTL0_START 0x20
41
42 #define LSI_SCNTL1_SST 0x01
43 #define LSI_SCNTL1_IARB 0x02
44 #define LSI_SCNTL1_AESP 0x04
45 #define LSI_SCNTL1_RST 0x08
46 #define LSI_SCNTL1_CON 0x10
47 #define LSI_SCNTL1_DHP 0x20
48 #define LSI_SCNTL1_ADB 0x40
49 #define LSI_SCNTL1_EXC 0x80
50
51 #define LSI_SCNTL2_WSR 0x01
52 #define LSI_SCNTL2_VUE0 0x02
53 #define LSI_SCNTL2_VUE1 0x04
54 #define LSI_SCNTL2_WSS 0x08
55 #define LSI_SCNTL2_SLPHBEN 0x10
56 #define LSI_SCNTL2_SLPMD 0x20
57 #define LSI_SCNTL2_CHM 0x40
58 #define LSI_SCNTL2_SDU 0x80
59
60 #define LSI_ISTAT0_DIP 0x01
61 #define LSI_ISTAT0_SIP 0x02
62 #define LSI_ISTAT0_INTF 0x04
63 #define LSI_ISTAT0_CON 0x08
64 #define LSI_ISTAT0_SEM 0x10
65 #define LSI_ISTAT0_SIGP 0x20
66 #define LSI_ISTAT0_SRST 0x40
67 #define LSI_ISTAT0_ABRT 0x80
68
69 #define LSI_ISTAT1_SI 0x01
70 #define LSI_ISTAT1_SRUN 0x02
71 #define LSI_ISTAT1_FLSH 0x04
72
73 #define LSI_SSTAT0_SDP0 0x01
74 #define LSI_SSTAT0_RST 0x02
75 #define LSI_SSTAT0_WOA 0x04
76 #define LSI_SSTAT0_LOA 0x08
77 #define LSI_SSTAT0_AIP 0x10
78 #define LSI_SSTAT0_OLF 0x20
79 #define LSI_SSTAT0_ORF 0x40
80 #define LSI_SSTAT0_ILF 0x80
81
82 #define LSI_SIST0_PAR 0x01
83 #define LSI_SIST0_RST 0x02
84 #define LSI_SIST0_UDC 0x04
85 #define LSI_SIST0_SGE 0x08
86 #define LSI_SIST0_RSL 0x10
87 #define LSI_SIST0_SEL 0x20
88 #define LSI_SIST0_CMP 0x40
89 #define LSI_SIST0_MA 0x80
90
91 #define LSI_SIST1_HTH 0x01
92 #define LSI_SIST1_GEN 0x02
93 #define LSI_SIST1_STO 0x04
94 #define LSI_SIST1_SBMC 0x10
95
96 #define LSI_SOCL_IO 0x01
97 #define LSI_SOCL_CD 0x02
98 #define LSI_SOCL_MSG 0x04
99 #define LSI_SOCL_ATN 0x08
100 #define LSI_SOCL_SEL 0x10
101 #define LSI_SOCL_BSY 0x20
102 #define LSI_SOCL_ACK 0x40
103 #define LSI_SOCL_REQ 0x80
104
105 #define LSI_DSTAT_IID 0x01
106 #define LSI_DSTAT_SIR 0x04
107 #define LSI_DSTAT_SSI 0x08
108 #define LSI_DSTAT_ABRT 0x10
109 #define LSI_DSTAT_BF 0x20
110 #define LSI_DSTAT_MDPE 0x40
111 #define LSI_DSTAT_DFE 0x80
112
113 #define LSI_DCNTL_COM 0x01
114 #define LSI_DCNTL_IRQD 0x02
115 #define LSI_DCNTL_STD 0x04
116 #define LSI_DCNTL_IRQM 0x08
117 #define LSI_DCNTL_SSM 0x10
118 #define LSI_DCNTL_PFEN 0x20
119 #define LSI_DCNTL_PFF 0x40
120 #define LSI_DCNTL_CLSE 0x80
121
122 #define LSI_DMODE_MAN 0x01
123 #define LSI_DMODE_BOF 0x02
124 #define LSI_DMODE_ERMP 0x04
125 #define LSI_DMODE_ERL 0x08
126 #define LSI_DMODE_DIOM 0x10
127 #define LSI_DMODE_SIOM 0x20
128
129 #define LSI_CTEST2_DACK 0x01
130 #define LSI_CTEST2_DREQ 0x02
131 #define LSI_CTEST2_TEOP 0x04
132 #define LSI_CTEST2_PCICIE 0x08
133 #define LSI_CTEST2_CM 0x10
134 #define LSI_CTEST2_CIO 0x20
135 #define LSI_CTEST2_SIGP 0x40
136 #define LSI_CTEST2_DDIR 0x80
137
138 #define LSI_CTEST5_BL2 0x04
139 #define LSI_CTEST5_DDIR 0x08
140 #define LSI_CTEST5_MASR 0x10
141 #define LSI_CTEST5_DFSN 0x20
142 #define LSI_CTEST5_BBCK 0x40
143 #define LSI_CTEST5_ADCK 0x80
144
145 #define LSI_CCNTL0_DILS 0x01
146 #define LSI_CCNTL0_DISFC 0x10
147 #define LSI_CCNTL0_ENNDJ 0x20
148 #define LSI_CCNTL0_PMJCTL 0x40
149 #define LSI_CCNTL0_ENPMJ 0x80
150
151 #define LSI_CCNTL1_EN64DBMV 0x01
152 #define LSI_CCNTL1_EN64TIBMV 0x02
153 #define LSI_CCNTL1_64TIMOD 0x04
154 #define LSI_CCNTL1_DDAC 0x08
155 #define LSI_CCNTL1_ZMOD 0x80
156
157 /* Enable Response to Reselection */
158 #define LSI_SCID_RRE 0x60
159
160 #define LSI_CCNTL1_40BIT (LSI_CCNTL1_EN64TIBMV|LSI_CCNTL1_64TIMOD)
161
162 #define PHASE_DO 0
163 #define PHASE_DI 1
164 #define PHASE_CMD 2
165 #define PHASE_ST 3
166 #define PHASE_MO 6
167 #define PHASE_MI 7
168 #define PHASE_MASK 7
169
170 /* Maximum length of MSG IN data. */
171 #define LSI_MAX_MSGIN_LEN 8
172
173 /* Flag set if this is a tagged command. */
174 #define LSI_TAG_VALID (1 << 16)
175
176 typedef struct lsi_request {
177 uint32_t tag;
178 SCSIDevice *dev;
179 uint32_t pending;
180 int out;
181 QTAILQ_ENTRY(lsi_request) next;
182 } lsi_request;
183
184 typedef struct {
185 PCIDevice dev;
186 int mmio_io_addr;
187 int ram_io_addr;
188 uint32_t script_ram_base;
189
190 int carry; /* ??? Should this be an a visible register somewhere? */
191 int sense;
192 /* Action to take at the end of a MSG IN phase.
193 0 = COMMAND, 1 = disconnect, 2 = DATA OUT, 3 = DATA IN. */
194 int msg_action;
195 int msg_len;
196 uint8_t msg[LSI_MAX_MSGIN_LEN];
197 /* 0 if SCRIPTS are running or stopped.
198 * 1 if a Wait Reselect instruction has been issued.
199 * 2 if processing DMA from lsi_execute_script.
200 * 3 if a DMA operation is in progress. */
201 int waiting;
202 SCSIBus bus;
203 SCSIDevice *select_dev;
204 int current_lun;
205 /* The tag is a combination of the device ID and the SCSI tag. */
206 uint32_t select_tag;
207 uint32_t current_dma_len;
208 int command_complete;
209 uint8_t *dma_buf;
210 QTAILQ_HEAD(, lsi_request) queue;
211 lsi_request *current;
212
213 uint32_t dsa;
214 uint32_t temp;
215 uint32_t dnad;
216 uint32_t dbc;
217 uint8_t istat0;
218 uint8_t istat1;
219 uint8_t dcmd;
220 uint8_t dstat;
221 uint8_t dien;
222 uint8_t sist0;
223 uint8_t sist1;
224 uint8_t sien0;
225 uint8_t sien1;
226 uint8_t mbox0;
227 uint8_t mbox1;
228 uint8_t dfifo;
229 uint8_t ctest2;
230 uint8_t ctest3;
231 uint8_t ctest4;
232 uint8_t ctest5;
233 uint8_t ccntl0;
234 uint8_t ccntl1;
235 uint32_t dsp;
236 uint32_t dsps;
237 uint8_t dmode;
238 uint8_t dcntl;
239 uint8_t scntl0;
240 uint8_t scntl1;
241 uint8_t scntl2;
242 uint8_t scntl3;
243 uint8_t sstat0;
244 uint8_t sstat1;
245 uint8_t scid;
246 uint8_t sxfer;
247 uint8_t socl;
248 uint8_t sdid;
249 uint8_t ssid;
250 uint8_t sfbr;
251 uint8_t stest1;
252 uint8_t stest2;
253 uint8_t stest3;
254 uint8_t sidl;
255 uint8_t stime0;
256 uint8_t respid0;
257 uint8_t respid1;
258 uint32_t mmrs;
259 uint32_t mmws;
260 uint32_t sfs;
261 uint32_t drs;
262 uint32_t sbms;
263 uint32_t dbms;
264 uint32_t dnad64;
265 uint32_t pmjad1;
266 uint32_t pmjad2;
267 uint32_t rbc;
268 uint32_t ua;
269 uint32_t ia;
270 uint32_t sbc;
271 uint32_t csbc;
272 uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
273 uint8_t sbr;
274
275 /* Script ram is stored as 32-bit words in host byteorder. */
276 uint32_t script_ram[2048];
277 } LSIState;
278
279 static inline int lsi_irq_on_rsl(LSIState *s)
280 {
281 return (s->sien0 & LSI_SIST0_RSL) && (s->scid & LSI_SCID_RRE);
282 }
283
284 static void lsi_soft_reset(LSIState *s)
285 {
286 DPRINTF("Reset\n");
287 s->carry = 0;
288
289 s->waiting = 0;
290 s->dsa = 0;
291 s->dnad = 0;
292 s->dbc = 0;
293 s->temp = 0;
294 memset(s->scratch, 0, sizeof(s->scratch));
295 s->istat0 = 0;
296 s->istat1 = 0;
297 s->dcmd = 0;
298 s->dstat = 0;
299 s->dien = 0;
300 s->sist0 = 0;
301 s->sist1 = 0;
302 s->sien0 = 0;
303 s->sien1 = 0;
304 s->mbox0 = 0;
305 s->mbox1 = 0;
306 s->dfifo = 0;
307 s->ctest2 = 0;
308 s->ctest3 = 0;
309 s->ctest4 = 0;
310 s->ctest5 = 0;
311 s->ccntl0 = 0;
312 s->ccntl1 = 0;
313 s->dsp = 0;
314 s->dsps = 0;
315 s->dmode = 0;
316 s->dcntl = 0;
317 s->scntl0 = 0xc0;
318 s->scntl1 = 0;
319 s->scntl2 = 0;
320 s->scntl3 = 0;
321 s->sstat0 = 0;
322 s->sstat1 = 0;
323 s->scid = 7;
324 s->sxfer = 0;
325 s->socl = 0;
326 s->stest1 = 0;
327 s->stest2 = 0;
328 s->stest3 = 0;
329 s->sidl = 0;
330 s->stime0 = 0;
331 s->respid0 = 0x80;
332 s->respid1 = 0;
333 s->mmrs = 0;
334 s->mmws = 0;
335 s->sfs = 0;
336 s->drs = 0;
337 s->sbms = 0;
338 s->dbms = 0;
339 s->dnad64 = 0;
340 s->pmjad1 = 0;
341 s->pmjad2 = 0;
342 s->rbc = 0;
343 s->ua = 0;
344 s->ia = 0;
345 s->sbc = 0;
346 s->csbc = 0;
347 s->sbr = 0;
348 }
349
350 static int lsi_dma_40bit(LSIState *s)
351 {
352 if ((s->ccntl1 & LSI_CCNTL1_40BIT) == LSI_CCNTL1_40BIT)
353 return 1;
354 return 0;
355 }
356
357 static int lsi_dma_ti64bit(LSIState *s)
358 {
359 if ((s->ccntl1 & LSI_CCNTL1_EN64TIBMV) == LSI_CCNTL1_EN64TIBMV)
360 return 1;
361 return 0;
362 }
363
364 static int lsi_dma_64bit(LSIState *s)
365 {
366 if ((s->ccntl1 & LSI_CCNTL1_EN64DBMV) == LSI_CCNTL1_EN64DBMV)
367 return 1;
368 return 0;
369 }
370
371 static uint8_t lsi_reg_readb(LSIState *s, int offset);
372 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val);
373 static void lsi_execute_script(LSIState *s);
374 static void lsi_reselect(LSIState *s, uint32_t tag);
375
376 static inline uint32_t read_dword(LSIState *s, uint32_t addr)
377 {
378 uint32_t buf;
379
380 /* Optimize reading from SCRIPTS RAM. */
381 if ((addr & 0xffffe000) == s->script_ram_base) {
382 return s->script_ram[(addr & 0x1fff) >> 2];
383 }
384 cpu_physical_memory_read(addr, (uint8_t *)&buf, 4);
385 return cpu_to_le32(buf);
386 }
387
388 static void lsi_stop_script(LSIState *s)
389 {
390 s->istat1 &= ~LSI_ISTAT1_SRUN;
391 }
392
393 static void lsi_update_irq(LSIState *s)
394 {
395 int level;
396 static int last_level;
397 lsi_request *p;
398
399 /* It's unclear whether the DIP/SIP bits should be cleared when the
400 Interrupt Status Registers are cleared or when istat0 is read.
401 We currently do the formwer, which seems to work. */
402 level = 0;
403 if (s->dstat) {
404 if (s->dstat & s->dien)
405 level = 1;
406 s->istat0 |= LSI_ISTAT0_DIP;
407 } else {
408 s->istat0 &= ~LSI_ISTAT0_DIP;
409 }
410
411 if (s->sist0 || s->sist1) {
412 if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1))
413 level = 1;
414 s->istat0 |= LSI_ISTAT0_SIP;
415 } else {
416 s->istat0 &= ~LSI_ISTAT0_SIP;
417 }
418 if (s->istat0 & LSI_ISTAT0_INTF)
419 level = 1;
420
421 if (level != last_level) {
422 DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
423 level, s->dstat, s->sist1, s->sist0);
424 last_level = level;
425 }
426 qemu_set_irq(s->dev.irq[0], level);
427
428 if (!level && lsi_irq_on_rsl(s) && !(s->scntl1 & LSI_SCNTL1_CON)) {
429 DPRINTF("Handled IRQs & disconnected, looking for pending "
430 "processes\n");
431 QTAILQ_FOREACH(p, &s->queue, next) {
432 if (p->pending) {
433 lsi_reselect(s, p->tag);
434 break;
435 }
436 }
437 }
438 }
439
440 /* Stop SCRIPTS execution and raise a SCSI interrupt. */
441 static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1)
442 {
443 uint32_t mask0;
444 uint32_t mask1;
445
446 DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
447 stat1, stat0, s->sist1, s->sist0);
448 s->sist0 |= stat0;
449 s->sist1 |= stat1;
450 /* Stop processor on fatal or unmasked interrupt. As a special hack
451 we don't stop processing when raising STO. Instead continue
452 execution and stop at the next insn that accesses the SCSI bus. */
453 mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL);
454 mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH);
455 mask1 &= ~LSI_SIST1_STO;
456 if (s->sist0 & mask0 || s->sist1 & mask1) {
457 lsi_stop_script(s);
458 }
459 lsi_update_irq(s);
460 }
461
462 /* Stop SCRIPTS execution and raise a DMA interrupt. */
463 static void lsi_script_dma_interrupt(LSIState *s, int stat)
464 {
465 DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat);
466 s->dstat |= stat;
467 lsi_update_irq(s);
468 lsi_stop_script(s);
469 }
470
471 static inline void lsi_set_phase(LSIState *s, int phase)
472 {
473 s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase;
474 }
475
476 static void lsi_bad_phase(LSIState *s, int out, int new_phase)
477 {
478 /* Trigger a phase mismatch. */
479 if (s->ccntl0 & LSI_CCNTL0_ENPMJ) {
480 if ((s->ccntl0 & LSI_CCNTL0_PMJCTL) || out) {
481 s->dsp = s->pmjad1;
482 } else {
483 s->dsp = s->pmjad2;
484 }
485 DPRINTF("Data phase mismatch jump to %08x\n", s->dsp);
486 } else {
487 DPRINTF("Phase mismatch interrupt\n");
488 lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
489 lsi_stop_script(s);
490 }
491 lsi_set_phase(s, new_phase);
492 }
493
494
495 /* Resume SCRIPTS execution after a DMA operation. */
496 static void lsi_resume_script(LSIState *s)
497 {
498 if (s->waiting != 2) {
499 s->waiting = 0;
500 lsi_execute_script(s);
501 } else {
502 s->waiting = 0;
503 }
504 }
505
506 /* Initiate a SCSI layer data transfer. */
507 static void lsi_do_dma(LSIState *s, int out)
508 {
509 uint32_t count;
510 target_phys_addr_t addr;
511
512 if (!s->current_dma_len) {
513 /* Wait until data is available. */
514 DPRINTF("DMA no data available\n");
515 return;
516 }
517
518 count = s->dbc;
519 if (count > s->current_dma_len)
520 count = s->current_dma_len;
521
522 addr = s->dnad;
523 /* both 40 and Table Indirect 64-bit DMAs store upper bits in dnad64 */
524 if (lsi_dma_40bit(s) || lsi_dma_ti64bit(s))
525 addr |= ((uint64_t)s->dnad64 << 32);
526 else if (s->dbms)
527 addr |= ((uint64_t)s->dbms << 32);
528 else if (s->sbms)
529 addr |= ((uint64_t)s->sbms << 32);
530
531 DPRINTF("DMA addr=0x" TARGET_FMT_plx " len=%d\n", addr, count);
532 s->csbc += count;
533 s->dnad += count;
534 s->dbc -= count;
535
536 if (s->dma_buf == NULL) {
537 s->dma_buf = s->current->dev->info->get_buf(s->current->dev,
538 s->current->tag);
539 }
540
541 /* ??? Set SFBR to first data byte. */
542 if (out) {
543 cpu_physical_memory_read(addr, s->dma_buf, count);
544 } else {
545 cpu_physical_memory_write(addr, s->dma_buf, count);
546 }
547 s->current_dma_len -= count;
548 if (s->current_dma_len == 0) {
549 s->dma_buf = NULL;
550 if (out) {
551 /* Write the data. */
552 s->current->dev->info->write_data(s->current->dev, s->current->tag);
553 } else {
554 /* Request any remaining data. */
555 s->current->dev->info->read_data(s->current->dev, s->current->tag);
556 }
557 } else {
558 s->dma_buf += count;
559 lsi_resume_script(s);
560 }
561 }
562
563
564 /* Add a command to the queue. */
565 static void lsi_queue_command(LSIState *s)
566 {
567 lsi_request *p = s->current;
568
569 DPRINTF("Queueing tag=0x%x\n", s->current_tag);
570 assert(s->current != NULL);
571 QTAILQ_INSERT_TAIL(&s->queue, s->current, next);
572 s->current = NULL;
573
574 p->pending = 0;
575 p->out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
576 }
577
578 /* Queue a byte for a MSG IN phase. */
579 static void lsi_add_msg_byte(LSIState *s, uint8_t data)
580 {
581 if (s->msg_len >= LSI_MAX_MSGIN_LEN) {
582 BADF("MSG IN data too long\n");
583 } else {
584 DPRINTF("MSG IN 0x%02x\n", data);
585 s->msg[s->msg_len++] = data;
586 }
587 }
588
589 /* Perform reselection to continue a command. */
590 static void lsi_reselect(LSIState *s, uint32_t tag)
591 {
592 lsi_request *p;
593 int id;
594
595 QTAILQ_FOREACH(p, &s->queue, next) {
596 if (p->tag == tag)
597 break;
598 }
599 if (p == NULL) {
600 BADF("Reselected non-existant command tag=0x%x\n", tag);
601 return;
602 }
603 assert(s->current == NULL);
604 QTAILQ_REMOVE(&s->queue, p, next);
605 s->current = p;
606
607 id = (tag >> 8) & 0xf;
608 s->ssid = id | 0x80;
609 /* LSI53C700 Family Compatibility, see LSI53C895A 4-73 */
610 if (!(s->dcntl & LSI_DCNTL_COM)) {
611 s->sfbr = 1 << (id & 0x7);
612 }
613 DPRINTF("Reselected target %d\n", id);
614 s->scntl1 |= LSI_SCNTL1_CON;
615 lsi_set_phase(s, PHASE_MI);
616 s->msg_action = p->out ? 2 : 3;
617 s->current_dma_len = p->pending;
618 s->dma_buf = NULL;
619 lsi_add_msg_byte(s, 0x80);
620 if (s->current->tag & LSI_TAG_VALID) {
621 lsi_add_msg_byte(s, 0x20);
622 lsi_add_msg_byte(s, tag & 0xff);
623 }
624
625 if (lsi_irq_on_rsl(s)) {
626 lsi_script_scsi_interrupt(s, LSI_SIST0_RSL, 0);
627 }
628 }
629
630 /* Record that data is available for a queued command. Returns zero if
631 the device was reselected, nonzero if the IO is deferred. */
632 static int lsi_queue_tag(LSIState *s, uint32_t tag, uint32_t arg)
633 {
634 lsi_request *p;
635
636 QTAILQ_FOREACH(p, &s->queue, next) {
637 if (p->tag == tag) {
638 if (p->pending) {
639 BADF("Multiple IO pending for tag %d\n", tag);
640 }
641 p->pending = arg;
642 /* Reselect if waiting for it, or if reselection triggers an IRQ
643 and the bus is free.
644 Since no interrupt stacking is implemented in the emulation, it
645 is also required that there are no pending interrupts waiting
646 for service from the device driver. */
647 if (s->waiting == 1 ||
648 (lsi_irq_on_rsl(s) && !(s->scntl1 & LSI_SCNTL1_CON) &&
649 !(s->istat0 & (LSI_ISTAT0_SIP | LSI_ISTAT0_DIP)))) {
650 /* Reselect device. */
651 lsi_reselect(s, tag);
652 return 0;
653 } else {
654 DPRINTF("Queueing IO tag=0x%x\n", tag);
655 p->pending = arg;
656 return 1;
657 }
658 }
659 }
660 BADF("IO with unknown tag %d\n", tag);
661 return 1;
662 }
663
664 /* Callback to indicate that the SCSI layer has completed a transfer. */
665 static void lsi_command_complete(SCSIBus *bus, int reason, uint32_t tag,
666 uint32_t arg)
667 {
668 LSIState *s = DO_UPCAST(LSIState, dev.qdev, bus->qbus.parent);
669 int out;
670
671 out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
672 if (reason == SCSI_REASON_DONE) {
673 DPRINTF("Command complete sense=%d\n", (int)arg);
674 s->sense = arg;
675 s->command_complete = 2;
676 if (s->waiting && s->dbc != 0) {
677 /* Raise phase mismatch for short transfers. */
678 lsi_bad_phase(s, out, PHASE_ST);
679 } else {
680 lsi_set_phase(s, PHASE_ST);
681 }
682
683 qemu_free(s->current);
684 s->current = NULL;
685
686 lsi_resume_script(s);
687 return;
688 }
689
690 if (s->waiting == 1 || tag != s->current->tag ||
691 (lsi_irq_on_rsl(s) && !(s->scntl1 & LSI_SCNTL1_CON))) {
692 if (lsi_queue_tag(s, tag, arg))
693 return;
694 }
695
696 /* host adapter (re)connected */
697 DPRINTF("Data ready tag=0x%x len=%d\n", tag, arg);
698 s->current_dma_len = arg;
699 s->command_complete = 1;
700 if (!s->waiting)
701 return;
702 if (s->waiting == 1 || s->dbc == 0) {
703 lsi_resume_script(s);
704 } else {
705 lsi_do_dma(s, out);
706 }
707 }
708
709 static void lsi_do_command(LSIState *s)
710 {
711 uint8_t buf[16];
712 int n;
713
714 DPRINTF("Send command len=%d\n", s->dbc);
715 if (s->dbc > 16)
716 s->dbc = 16;
717 cpu_physical_memory_read(s->dnad, buf, s->dbc);
718 s->sfbr = buf[0];
719 s->command_complete = 0;
720
721 assert(s->current == NULL);
722 s->current = qemu_mallocz(sizeof(lsi_request));
723 s->current->tag = s->select_tag;
724 s->current->dev = s->select_dev;
725
726 n = s->current->dev->info->send_command(s->current->dev, s->current->tag, buf,
727 s->current_lun);
728 if (n > 0) {
729 lsi_set_phase(s, PHASE_DI);
730 s->current->dev->info->read_data(s->current->dev, s->current->tag);
731 } else if (n < 0) {
732 lsi_set_phase(s, PHASE_DO);
733 s->current->dev->info->write_data(s->current->dev, s->current->tag);
734 }
735
736 if (!s->command_complete) {
737 if (n) {
738 /* Command did not complete immediately so disconnect. */
739 lsi_add_msg_byte(s, 2); /* SAVE DATA POINTER */
740 lsi_add_msg_byte(s, 4); /* DISCONNECT */
741 /* wait data */
742 lsi_set_phase(s, PHASE_MI);
743 s->msg_action = 1;
744 lsi_queue_command(s);
745 } else {
746 /* wait command complete */
747 lsi_set_phase(s, PHASE_DI);
748 }
749 }
750 }
751
752 static void lsi_do_status(LSIState *s)
753 {
754 uint8_t sense;
755 DPRINTF("Get status len=%d sense=%d\n", s->dbc, s->sense);
756 if (s->dbc != 1)
757 BADF("Bad Status move\n");
758 s->dbc = 1;
759 sense = s->sense;
760 s->sfbr = sense;
761 cpu_physical_memory_write(s->dnad, &sense, 1);
762 lsi_set_phase(s, PHASE_MI);
763 s->msg_action = 1;
764 lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
765 }
766
767 static void lsi_disconnect(LSIState *s)
768 {
769 s->scntl1 &= ~LSI_SCNTL1_CON;
770 s->sstat1 &= ~PHASE_MASK;
771 }
772
773 static void lsi_do_msgin(LSIState *s)
774 {
775 int len;
776 DPRINTF("Message in len=%d/%d\n", s->dbc, s->msg_len);
777 s->sfbr = s->msg[0];
778 len = s->msg_len;
779 if (len > s->dbc)
780 len = s->dbc;
781 cpu_physical_memory_write(s->dnad, s->msg, len);
782 /* Linux drivers rely on the last byte being in the SIDL. */
783 s->sidl = s->msg[len - 1];
784 s->msg_len -= len;
785 if (s->msg_len) {
786 memmove(s->msg, s->msg + len, s->msg_len);
787 } else {
788 /* ??? Check if ATN (not yet implemented) is asserted and maybe
789 switch to PHASE_MO. */
790 switch (s->msg_action) {
791 case 0:
792 lsi_set_phase(s, PHASE_CMD);
793 break;
794 case 1:
795 lsi_disconnect(s);
796 break;
797 case 2:
798 lsi_set_phase(s, PHASE_DO);
799 break;
800 case 3:
801 lsi_set_phase(s, PHASE_DI);
802 break;
803 default:
804 abort();
805 }
806 }
807 }
808
809 /* Read the next byte during a MSGOUT phase. */
810 static uint8_t lsi_get_msgbyte(LSIState *s)
811 {
812 uint8_t data;
813 cpu_physical_memory_read(s->dnad, &data, 1);
814 s->dnad++;
815 s->dbc--;
816 return data;
817 }
818
819 static void lsi_do_msgout(LSIState *s)
820 {
821 uint8_t msg;
822 int len;
823
824 DPRINTF("MSG out len=%d\n", s->dbc);
825 while (s->dbc) {
826 msg = lsi_get_msgbyte(s);
827 s->sfbr = msg;
828
829 switch (msg) {
830 case 0x04:
831 DPRINTF("MSG: Disconnect\n");
832 lsi_disconnect(s);
833 break;
834 case 0x08:
835 DPRINTF("MSG: No Operation\n");
836 lsi_set_phase(s, PHASE_CMD);
837 break;
838 case 0x01:
839 len = lsi_get_msgbyte(s);
840 msg = lsi_get_msgbyte(s);
841 DPRINTF("Extended message 0x%x (len %d)\n", msg, len);
842 switch (msg) {
843 case 1:
844 DPRINTF("SDTR (ignored)\n");
845 s->dbc -= 2;
846 break;
847 case 3:
848 DPRINTF("WDTR (ignored)\n");
849 s->dbc -= 1;
850 break;
851 default:
852 goto bad;
853 }
854 break;
855 case 0x20: /* SIMPLE queue */
856 s->select_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
857 DPRINTF("SIMPLE queue tag=0x%x\n", s->current_tag & 0xff);
858 break;
859 case 0x21: /* HEAD of queue */
860 BADF("HEAD queue not implemented\n");
861 s->select_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
862 break;
863 case 0x22: /* ORDERED queue */
864 BADF("ORDERED queue not implemented\n");
865 s->select_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
866 break;
867 default:
868 if ((msg & 0x80) == 0) {
869 goto bad;
870 }
871 s->current_lun = msg & 7;
872 DPRINTF("Select LUN %d\n", s->current_lun);
873 lsi_set_phase(s, PHASE_CMD);
874 break;
875 }
876 }
877 return;
878 bad:
879 BADF("Unimplemented message 0x%02x\n", msg);
880 lsi_set_phase(s, PHASE_MI);
881 lsi_add_msg_byte(s, 7); /* MESSAGE REJECT */
882 s->msg_action = 0;
883 }
884
885 /* Sign extend a 24-bit value. */
886 static inline int32_t sxt24(int32_t n)
887 {
888 return (n << 8) >> 8;
889 }
890
891 #define LSI_BUF_SIZE 4096
892 static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count)
893 {
894 int n;
895 uint8_t buf[LSI_BUF_SIZE];
896
897 DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
898 while (count) {
899 n = (count > LSI_BUF_SIZE) ? LSI_BUF_SIZE : count;
900 cpu_physical_memory_read(src, buf, n);
901 cpu_physical_memory_write(dest, buf, n);
902 src += n;
903 dest += n;
904 count -= n;
905 }
906 }
907
908 static void lsi_wait_reselect(LSIState *s)
909 {
910 lsi_request *p;
911
912 DPRINTF("Wait Reselect\n");
913 if (s->current_dma_len)
914 BADF("Reselect with pending DMA\n");
915
916 QTAILQ_FOREACH(p, &s->queue, next) {
917 if (p->pending) {
918 lsi_reselect(s, p->tag);
919 break;
920 }
921 }
922 if (s->current_dma_len == 0) {
923 s->waiting = 1;
924 }
925 }
926
927 static void lsi_execute_script(LSIState *s)
928 {
929 uint32_t insn;
930 uint32_t addr, addr_high;
931 int opcode;
932 int insn_processed = 0;
933
934 s->istat1 |= LSI_ISTAT1_SRUN;
935 again:
936 insn_processed++;
937 insn = read_dword(s, s->dsp);
938 if (!insn) {
939 /* If we receive an empty opcode increment the DSP by 4 bytes
940 instead of 8 and execute the next opcode at that location */
941 s->dsp += 4;
942 goto again;
943 }
944 addr = read_dword(s, s->dsp + 4);
945 addr_high = 0;
946 DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s->dsp, insn, addr);
947 s->dsps = addr;
948 s->dcmd = insn >> 24;
949 s->dsp += 8;
950 switch (insn >> 30) {
951 case 0: /* Block move. */
952 if (s->sist1 & LSI_SIST1_STO) {
953 DPRINTF("Delayed select timeout\n");
954 lsi_stop_script(s);
955 break;
956 }
957 s->dbc = insn & 0xffffff;
958 s->rbc = s->dbc;
959 /* ??? Set ESA. */
960 s->ia = s->dsp - 8;
961 if (insn & (1 << 29)) {
962 /* Indirect addressing. */
963 addr = read_dword(s, addr);
964 } else if (insn & (1 << 28)) {
965 uint32_t buf[2];
966 int32_t offset;
967 /* Table indirect addressing. */
968
969 /* 32-bit Table indirect */
970 offset = sxt24(addr);
971 cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
972 /* byte count is stored in bits 0:23 only */
973 s->dbc = cpu_to_le32(buf[0]) & 0xffffff;
974 s->rbc = s->dbc;
975 addr = cpu_to_le32(buf[1]);
976
977 /* 40-bit DMA, upper addr bits [39:32] stored in first DWORD of
978 * table, bits [31:24] */
979 if (lsi_dma_40bit(s))
980 addr_high = cpu_to_le32(buf[0]) >> 24;
981 else if (lsi_dma_ti64bit(s)) {
982 int selector = (cpu_to_le32(buf[0]) >> 24) & 0x1f;
983 switch (selector) {
984 case 0 ... 0x0f:
985 /* offset index into scratch registers since
986 * TI64 mode can use registers C to R */
987 addr_high = s->scratch[2 + selector];
988 break;
989 case 0x10:
990 addr_high = s->mmrs;
991 break;
992 case 0x11:
993 addr_high = s->mmws;
994 break;
995 case 0x12:
996 addr_high = s->sfs;
997 break;
998 case 0x13:
999 addr_high = s->drs;
1000 break;
1001 case 0x14:
1002 addr_high = s->sbms;
1003 break;
1004 case 0x15:
1005 addr_high = s->dbms;
1006 break;
1007 default:
1008 BADF("Illegal selector specified (0x%x > 0x15)"
1009 " for 64-bit DMA block move", selector);
1010 break;
1011 }
1012 }
1013 } else if (lsi_dma_64bit(s)) {
1014 /* fetch a 3rd dword if 64-bit direct move is enabled and
1015 only if we're not doing table indirect or indirect addressing */
1016 s->dbms = read_dword(s, s->dsp);
1017 s->dsp += 4;
1018 s->ia = s->dsp - 12;
1019 }
1020 if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) {
1021 DPRINTF("Wrong phase got %d expected %d\n",
1022 s->sstat1 & PHASE_MASK, (insn >> 24) & 7);
1023 lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
1024 break;
1025 }
1026 s->dnad = addr;
1027 s->dnad64 = addr_high;
1028 switch (s->sstat1 & 0x7) {
1029 case PHASE_DO:
1030 s->waiting = 2;
1031 lsi_do_dma(s, 1);
1032 if (s->waiting)
1033 s->waiting = 3;
1034 break;
1035 case PHASE_DI:
1036 s->waiting = 2;
1037 lsi_do_dma(s, 0);
1038 if (s->waiting)
1039 s->waiting = 3;
1040 break;
1041 case PHASE_CMD:
1042 lsi_do_command(s);
1043 break;
1044 case PHASE_ST:
1045 lsi_do_status(s);
1046 break;
1047 case PHASE_MO:
1048 lsi_do_msgout(s);
1049 break;
1050 case PHASE_MI:
1051 lsi_do_msgin(s);
1052 break;
1053 default:
1054 BADF("Unimplemented phase %d\n", s->sstat1 & PHASE_MASK);
1055 exit(1);
1056 }
1057 s->dfifo = s->dbc & 0xff;
1058 s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3);
1059 s->sbc = s->dbc;
1060 s->rbc -= s->dbc;
1061 s->ua = addr + s->dbc;
1062 break;
1063
1064 case 1: /* IO or Read/Write instruction. */
1065 opcode = (insn >> 27) & 7;
1066 if (opcode < 5) {
1067 uint32_t id;
1068
1069 if (insn & (1 << 25)) {
1070 id = read_dword(s, s->dsa + sxt24(insn));
1071 } else {
1072 id = insn;
1073 }
1074 id = (id >> 16) & 0xf;
1075 if (insn & (1 << 26)) {
1076 addr = s->dsp + sxt24(addr);
1077 }
1078 s->dnad = addr;
1079 switch (opcode) {
1080 case 0: /* Select */
1081 s->sdid = id;
1082 if (s->scntl1 & LSI_SCNTL1_CON) {
1083 DPRINTF("Already reselected, jumping to alternative address\n");
1084 s->dsp = s->dnad;
1085 break;
1086 }
1087 s->sstat0 |= LSI_SSTAT0_WOA;
1088 s->scntl1 &= ~LSI_SCNTL1_IARB;
1089 if (id >= LSI_MAX_DEVS || !s->bus.devs[id]) {
1090 DPRINTF("Selected absent target %d\n", id);
1091 lsi_script_scsi_interrupt(s, 0, LSI_SIST1_STO);
1092 lsi_disconnect(s);
1093 break;
1094 }
1095 DPRINTF("Selected target %d%s\n",
1096 id, insn & (1 << 3) ? " ATN" : "");
1097 /* ??? Linux drivers compain when this is set. Maybe
1098 it only applies in low-level mode (unimplemented).
1099 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
1100 s->select_dev = s->bus.devs[id];
1101 s->select_tag = id << 8;
1102 s->scntl1 |= LSI_SCNTL1_CON;
1103 if (insn & (1 << 3)) {
1104 s->socl |= LSI_SOCL_ATN;
1105 }
1106 lsi_set_phase(s, PHASE_MO);
1107 break;
1108 case 1: /* Disconnect */
1109 DPRINTF("Wait Disconnect\n");
1110 s->scntl1 &= ~LSI_SCNTL1_CON;
1111 break;
1112 case 2: /* Wait Reselect */
1113 if (!lsi_irq_on_rsl(s)) {
1114 lsi_wait_reselect(s);
1115 }
1116 break;
1117 case 3: /* Set */
1118 DPRINTF("Set%s%s%s%s\n",
1119 insn & (1 << 3) ? " ATN" : "",
1120 insn & (1 << 6) ? " ACK" : "",
1121 insn & (1 << 9) ? " TM" : "",
1122 insn & (1 << 10) ? " CC" : "");
1123 if (insn & (1 << 3)) {
1124 s->socl |= LSI_SOCL_ATN;
1125 lsi_set_phase(s, PHASE_MO);
1126 }
1127 if (insn & (1 << 9)) {
1128 BADF("Target mode not implemented\n");
1129 exit(1);
1130 }
1131 if (insn & (1 << 10))
1132 s->carry = 1;
1133 break;
1134 case 4: /* Clear */
1135 DPRINTF("Clear%s%s%s%s\n",
1136 insn & (1 << 3) ? " ATN" : "",
1137 insn & (1 << 6) ? " ACK" : "",
1138 insn & (1 << 9) ? " TM" : "",
1139 insn & (1 << 10) ? " CC" : "");
1140 if (insn & (1 << 3)) {
1141 s->socl &= ~LSI_SOCL_ATN;
1142 }
1143 if (insn & (1 << 10))
1144 s->carry = 0;
1145 break;
1146 }
1147 } else {
1148 uint8_t op0;
1149 uint8_t op1;
1150 uint8_t data8;
1151 int reg;
1152 int operator;
1153 #ifdef DEBUG_LSI
1154 static const char *opcode_names[3] =
1155 {"Write", "Read", "Read-Modify-Write"};
1156 static const char *operator_names[8] =
1157 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
1158 #endif
1159
1160 reg = ((insn >> 16) & 0x7f) | (insn & 0x80);
1161 data8 = (insn >> 8) & 0xff;
1162 opcode = (insn >> 27) & 7;
1163 operator = (insn >> 24) & 7;
1164 DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
1165 opcode_names[opcode - 5], reg,
1166 operator_names[operator], data8, s->sfbr,
1167 (insn & (1 << 23)) ? " SFBR" : "");
1168 op0 = op1 = 0;
1169 switch (opcode) {
1170 case 5: /* From SFBR */
1171 op0 = s->sfbr;
1172 op1 = data8;
1173 break;
1174 case 6: /* To SFBR */
1175 if (operator)
1176 op0 = lsi_reg_readb(s, reg);
1177 op1 = data8;
1178 break;
1179 case 7: /* Read-modify-write */
1180 if (operator)
1181 op0 = lsi_reg_readb(s, reg);
1182 if (insn & (1 << 23)) {
1183 op1 = s->sfbr;
1184 } else {
1185 op1 = data8;
1186 }
1187 break;
1188 }
1189
1190 switch (operator) {
1191 case 0: /* move */
1192 op0 = op1;
1193 break;
1194 case 1: /* Shift left */
1195 op1 = op0 >> 7;
1196 op0 = (op0 << 1) | s->carry;
1197 s->carry = op1;
1198 break;
1199 case 2: /* OR */
1200 op0 |= op1;
1201 break;
1202 case 3: /* XOR */
1203 op0 ^= op1;
1204 break;
1205 case 4: /* AND */
1206 op0 &= op1;
1207 break;
1208 case 5: /* SHR */
1209 op1 = op0 & 1;
1210 op0 = (op0 >> 1) | (s->carry << 7);
1211 s->carry = op1;
1212 break;
1213 case 6: /* ADD */
1214 op0 += op1;
1215 s->carry = op0 < op1;
1216 break;
1217 case 7: /* ADC */
1218 op0 += op1 + s->carry;
1219 if (s->carry)
1220 s->carry = op0 <= op1;
1221 else
1222 s->carry = op0 < op1;
1223 break;
1224 }
1225
1226 switch (opcode) {
1227 case 5: /* From SFBR */
1228 case 7: /* Read-modify-write */
1229 lsi_reg_writeb(s, reg, op0);
1230 break;
1231 case 6: /* To SFBR */
1232 s->sfbr = op0;
1233 break;
1234 }
1235 }
1236 break;
1237
1238 case 2: /* Transfer Control. */
1239 {
1240 int cond;
1241 int jmp;
1242
1243 if ((insn & 0x002e0000) == 0) {
1244 DPRINTF("NOP\n");
1245 break;
1246 }
1247 if (s->sist1 & LSI_SIST1_STO) {
1248 DPRINTF("Delayed select timeout\n");
1249 lsi_stop_script(s);
1250 break;
1251 }
1252 cond = jmp = (insn & (1 << 19)) != 0;
1253 if (cond == jmp && (insn & (1 << 21))) {
1254 DPRINTF("Compare carry %d\n", s->carry == jmp);
1255 cond = s->carry != 0;
1256 }
1257 if (cond == jmp && (insn & (1 << 17))) {
1258 DPRINTF("Compare phase %d %c= %d\n",
1259 (s->sstat1 & PHASE_MASK),
1260 jmp ? '=' : '!',
1261 ((insn >> 24) & 7));
1262 cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7);
1263 }
1264 if (cond == jmp && (insn & (1 << 18))) {
1265 uint8_t mask;
1266
1267 mask = (~insn >> 8) & 0xff;
1268 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1269 s->sfbr, mask, jmp ? '=' : '!', insn & mask);
1270 cond = (s->sfbr & mask) == (insn & mask);
1271 }
1272 if (cond == jmp) {
1273 if (insn & (1 << 23)) {
1274 /* Relative address. */
1275 addr = s->dsp + sxt24(addr);
1276 }
1277 switch ((insn >> 27) & 7) {
1278 case 0: /* Jump */
1279 DPRINTF("Jump to 0x%08x\n", addr);
1280 s->dsp = addr;
1281 break;
1282 case 1: /* Call */
1283 DPRINTF("Call 0x%08x\n", addr);
1284 s->temp = s->dsp;
1285 s->dsp = addr;
1286 break;
1287 case 2: /* Return */
1288 DPRINTF("Return to 0x%08x\n", s->temp);
1289 s->dsp = s->temp;
1290 break;
1291 case 3: /* Interrupt */
1292 DPRINTF("Interrupt 0x%08x\n", s->dsps);
1293 if ((insn & (1 << 20)) != 0) {
1294 s->istat0 |= LSI_ISTAT0_INTF;
1295 lsi_update_irq(s);
1296 } else {
1297 lsi_script_dma_interrupt(s, LSI_DSTAT_SIR);
1298 }
1299 break;
1300 default:
1301 DPRINTF("Illegal transfer control\n");
1302 lsi_script_dma_interrupt(s, LSI_DSTAT_IID);
1303 break;
1304 }
1305 } else {
1306 DPRINTF("Control condition failed\n");
1307 }
1308 }
1309 break;
1310
1311 case 3:
1312 if ((insn & (1 << 29)) == 0) {
1313 /* Memory move. */
1314 uint32_t dest;
1315 /* ??? The docs imply the destination address is loaded into
1316 the TEMP register. However the Linux drivers rely on
1317 the value being presrved. */
1318 dest = read_dword(s, s->dsp);
1319 s->dsp += 4;
1320 lsi_memcpy(s, dest, addr, insn & 0xffffff);
1321 } else {
1322 uint8_t data[7];
1323 int reg;
1324 int n;
1325 int i;
1326
1327 if (insn & (1 << 28)) {
1328 addr = s->dsa + sxt24(addr);
1329 }
1330 n = (insn & 7);
1331 reg = (insn >> 16) & 0xff;
1332 if (insn & (1 << 24)) {
1333 cpu_physical_memory_read(addr, data, n);
1334 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
1335 addr, *(int *)data);
1336 for (i = 0; i < n; i++) {
1337 lsi_reg_writeb(s, reg + i, data[i]);
1338 }
1339 } else {
1340 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
1341 for (i = 0; i < n; i++) {
1342 data[i] = lsi_reg_readb(s, reg + i);
1343 }
1344 cpu_physical_memory_write(addr, data, n);
1345 }
1346 }
1347 }
1348 if (insn_processed > 10000 && !s->waiting) {
1349 /* Some windows drivers make the device spin waiting for a memory
1350 location to change. If we have been executed a lot of code then
1351 assume this is the case and force an unexpected device disconnect.
1352 This is apparently sufficient to beat the drivers into submission.
1353 */
1354 if (!(s->sien0 & LSI_SIST0_UDC))
1355 fprintf(stderr, "inf. loop with UDC masked\n");
1356 lsi_script_scsi_interrupt(s, LSI_SIST0_UDC, 0);
1357 lsi_disconnect(s);
1358 } else if (s->istat1 & LSI_ISTAT1_SRUN && !s->waiting) {
1359 if (s->dcntl & LSI_DCNTL_SSM) {
1360 lsi_script_dma_interrupt(s, LSI_DSTAT_SSI);
1361 } else {
1362 goto again;
1363 }
1364 }
1365 DPRINTF("SCRIPTS execution stopped\n");
1366 }
1367
1368 static uint8_t lsi_reg_readb(LSIState *s, int offset)
1369 {
1370 uint8_t tmp;
1371 #define CASE_GET_REG24(name, addr) \
1372 case addr: return s->name & 0xff; \
1373 case addr + 1: return (s->name >> 8) & 0xff; \
1374 case addr + 2: return (s->name >> 16) & 0xff;
1375
1376 #define CASE_GET_REG32(name, addr) \
1377 case addr: return s->name & 0xff; \
1378 case addr + 1: return (s->name >> 8) & 0xff; \
1379 case addr + 2: return (s->name >> 16) & 0xff; \
1380 case addr + 3: return (s->name >> 24) & 0xff;
1381
1382 #ifdef DEBUG_LSI_REG
1383 DPRINTF("Read reg %x\n", offset);
1384 #endif
1385 switch (offset) {
1386 case 0x00: /* SCNTL0 */
1387 return s->scntl0;
1388 case 0x01: /* SCNTL1 */
1389 return s->scntl1;
1390 case 0x02: /* SCNTL2 */
1391 return s->scntl2;
1392 case 0x03: /* SCNTL3 */
1393 return s->scntl3;
1394 case 0x04: /* SCID */
1395 return s->scid;
1396 case 0x05: /* SXFER */
1397 return s->sxfer;
1398 case 0x06: /* SDID */
1399 return s->sdid;
1400 case 0x07: /* GPREG0 */
1401 return 0x7f;
1402 case 0x08: /* Revision ID */
1403 return 0x00;
1404 case 0xa: /* SSID */
1405 return s->ssid;
1406 case 0xb: /* SBCL */
1407 /* ??? This is not correct. However it's (hopefully) only
1408 used for diagnostics, so should be ok. */
1409 return 0;
1410 case 0xc: /* DSTAT */
1411 tmp = s->dstat | 0x80;
1412 if ((s->istat0 & LSI_ISTAT0_INTF) == 0)
1413 s->dstat = 0;
1414 lsi_update_irq(s);
1415 return tmp;
1416 case 0x0d: /* SSTAT0 */
1417 return s->sstat0;
1418 case 0x0e: /* SSTAT1 */
1419 return s->sstat1;
1420 case 0x0f: /* SSTAT2 */
1421 return s->scntl1 & LSI_SCNTL1_CON ? 0 : 2;
1422 CASE_GET_REG32(dsa, 0x10)
1423 case 0x14: /* ISTAT0 */
1424 return s->istat0;
1425 case 0x15: /* ISTAT1 */
1426 return s->istat1;
1427 case 0x16: /* MBOX0 */
1428 return s->mbox0;
1429 case 0x17: /* MBOX1 */
1430 return s->mbox1;
1431 case 0x18: /* CTEST0 */
1432 return 0xff;
1433 case 0x19: /* CTEST1 */
1434 return 0;
1435 case 0x1a: /* CTEST2 */
1436 tmp = s->ctest2 | LSI_CTEST2_DACK | LSI_CTEST2_CM;
1437 if (s->istat0 & LSI_ISTAT0_SIGP) {
1438 s->istat0 &= ~LSI_ISTAT0_SIGP;
1439 tmp |= LSI_CTEST2_SIGP;
1440 }
1441 return tmp;
1442 case 0x1b: /* CTEST3 */
1443 return s->ctest3;
1444 CASE_GET_REG32(temp, 0x1c)
1445 case 0x20: /* DFIFO */
1446 return 0;
1447 case 0x21: /* CTEST4 */
1448 return s->ctest4;
1449 case 0x22: /* CTEST5 */
1450 return s->ctest5;
1451 case 0x23: /* CTEST6 */
1452 return 0;
1453 CASE_GET_REG24(dbc, 0x24)
1454 case 0x27: /* DCMD */
1455 return s->dcmd;
1456 CASE_GET_REG32(dnad, 0x28)
1457 CASE_GET_REG32(dsp, 0x2c)
1458 CASE_GET_REG32(dsps, 0x30)
1459 CASE_GET_REG32(scratch[0], 0x34)
1460 case 0x38: /* DMODE */
1461 return s->dmode;
1462 case 0x39: /* DIEN */
1463 return s->dien;
1464 case 0x3a: /* SBR */
1465 return s->sbr;
1466 case 0x3b: /* DCNTL */
1467 return s->dcntl;
1468 case 0x40: /* SIEN0 */
1469 return s->sien0;
1470 case 0x41: /* SIEN1 */
1471 return s->sien1;
1472 case 0x42: /* SIST0 */
1473 tmp = s->sist0;
1474 s->sist0 = 0;
1475 lsi_update_irq(s);
1476 return tmp;
1477 case 0x43: /* SIST1 */
1478 tmp = s->sist1;
1479 s->sist1 = 0;
1480 lsi_update_irq(s);
1481 return tmp;
1482 case 0x46: /* MACNTL */
1483 return 0x0f;
1484 case 0x47: /* GPCNTL0 */
1485 return 0x0f;
1486 case 0x48: /* STIME0 */
1487 return s->stime0;
1488 case 0x4a: /* RESPID0 */
1489 return s->respid0;
1490 case 0x4b: /* RESPID1 */
1491 return s->respid1;
1492 case 0x4d: /* STEST1 */
1493 return s->stest1;
1494 case 0x4e: /* STEST2 */
1495 return s->stest2;
1496 case 0x4f: /* STEST3 */
1497 return s->stest3;
1498 case 0x50: /* SIDL */
1499 /* This is needed by the linux drivers. We currently only update it
1500 during the MSG IN phase. */
1501 return s->sidl;
1502 case 0x52: /* STEST4 */
1503 return 0xe0;
1504 case 0x56: /* CCNTL0 */
1505 return s->ccntl0;
1506 case 0x57: /* CCNTL1 */
1507 return s->ccntl1;
1508 case 0x58: /* SBDL */
1509 /* Some drivers peek at the data bus during the MSG IN phase. */
1510 if ((s->sstat1 & PHASE_MASK) == PHASE_MI)
1511 return s->msg[0];
1512 return 0;
1513 case 0x59: /* SBDL high */
1514 return 0;
1515 CASE_GET_REG32(mmrs, 0xa0)
1516 CASE_GET_REG32(mmws, 0xa4)
1517 CASE_GET_REG32(sfs, 0xa8)
1518 CASE_GET_REG32(drs, 0xac)
1519 CASE_GET_REG32(sbms, 0xb0)
1520 CASE_GET_REG32(dbms, 0xb4)
1521 CASE_GET_REG32(dnad64, 0xb8)
1522 CASE_GET_REG32(pmjad1, 0xc0)
1523 CASE_GET_REG32(pmjad2, 0xc4)
1524 CASE_GET_REG32(rbc, 0xc8)
1525 CASE_GET_REG32(ua, 0xcc)
1526 CASE_GET_REG32(ia, 0xd4)
1527 CASE_GET_REG32(sbc, 0xd8)
1528 CASE_GET_REG32(csbc, 0xdc)
1529 }
1530 if (offset >= 0x5c && offset < 0xa0) {
1531 int n;
1532 int shift;
1533 n = (offset - 0x58) >> 2;
1534 shift = (offset & 3) * 8;
1535 return (s->scratch[n] >> shift) & 0xff;
1536 }
1537 BADF("readb 0x%x\n", offset);
1538 exit(1);
1539 #undef CASE_GET_REG24
1540 #undef CASE_GET_REG32
1541 }
1542
1543 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
1544 {
1545 #define CASE_SET_REG24(name, addr) \
1546 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1547 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1548 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break;
1549
1550 #define CASE_SET_REG32(name, addr) \
1551 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1552 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1553 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1554 case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1555
1556 #ifdef DEBUG_LSI_REG
1557 DPRINTF("Write reg %x = %02x\n", offset, val);
1558 #endif
1559 switch (offset) {
1560 case 0x00: /* SCNTL0 */
1561 s->scntl0 = val;
1562 if (val & LSI_SCNTL0_START) {
1563 BADF("Start sequence not implemented\n");
1564 }
1565 break;
1566 case 0x01: /* SCNTL1 */
1567 s->scntl1 = val & ~LSI_SCNTL1_SST;
1568 if (val & LSI_SCNTL1_IARB) {
1569 BADF("Immediate Arbritration not implemented\n");
1570 }
1571 if (val & LSI_SCNTL1_RST) {
1572 s->sstat0 |= LSI_SSTAT0_RST;
1573 lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
1574 } else {
1575 s->sstat0 &= ~LSI_SSTAT0_RST;
1576 }
1577 break;
1578 case 0x02: /* SCNTL2 */
1579 val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS);
1580 s->scntl2 = val;
1581 break;
1582 case 0x03: /* SCNTL3 */
1583 s->scntl3 = val;
1584 break;
1585 case 0x04: /* SCID */
1586 s->scid = val;
1587 break;
1588 case 0x05: /* SXFER */
1589 s->sxfer = val;
1590 break;
1591 case 0x06: /* SDID */
1592 if ((val & 0xf) != (s->ssid & 0xf))
1593 BADF("Destination ID does not match SSID\n");
1594 s->sdid = val & 0xf;
1595 break;
1596 case 0x07: /* GPREG0 */
1597 break;
1598 case 0x08: /* SFBR */
1599 /* The CPU is not allowed to write to this register. However the
1600 SCRIPTS register move instructions are. */
1601 s->sfbr = val;
1602 break;
1603 case 0x0a: case 0x0b:
1604 /* Openserver writes to these readonly registers on startup */
1605 return;
1606 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1607 /* Linux writes to these readonly registers on startup. */
1608 return;
1609 CASE_SET_REG32(dsa, 0x10)
1610 case 0x14: /* ISTAT0 */
1611 s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0);
1612 if (val & LSI_ISTAT0_ABRT) {
1613 lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT);
1614 }
1615 if (val & LSI_ISTAT0_INTF) {
1616 s->istat0 &= ~LSI_ISTAT0_INTF;
1617 lsi_update_irq(s);
1618 }
1619 if (s->waiting == 1 && val & LSI_ISTAT0_SIGP) {
1620 DPRINTF("Woken by SIGP\n");
1621 s->waiting = 0;
1622 s->dsp = s->dnad;
1623 lsi_execute_script(s);
1624 }
1625 if (val & LSI_ISTAT0_SRST) {
1626 lsi_soft_reset(s);
1627 }
1628 break;
1629 case 0x16: /* MBOX0 */
1630 s->mbox0 = val;
1631 break;
1632 case 0x17: /* MBOX1 */
1633 s->mbox1 = val;
1634 break;
1635 case 0x1a: /* CTEST2 */
1636 s->ctest2 = val & LSI_CTEST2_PCICIE;
1637 break;
1638 case 0x1b: /* CTEST3 */
1639 s->ctest3 = val & 0x0f;
1640 break;
1641 CASE_SET_REG32(temp, 0x1c)
1642 case 0x21: /* CTEST4 */
1643 if (val & 7) {
1644 BADF("Unimplemented CTEST4-FBL 0x%x\n", val);
1645 }
1646 s->ctest4 = val;
1647 break;
1648 case 0x22: /* CTEST5 */
1649 if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) {
1650 BADF("CTEST5 DMA increment not implemented\n");
1651 }
1652 s->ctest5 = val;
1653 break;
1654 CASE_SET_REG24(dbc, 0x24)
1655 CASE_SET_REG32(dnad, 0x28)
1656 case 0x2c: /* DSP[0:7] */
1657 s->dsp &= 0xffffff00;
1658 s->dsp |= val;
1659 break;
1660 case 0x2d: /* DSP[8:15] */
1661 s->dsp &= 0xffff00ff;
1662 s->dsp |= val << 8;
1663 break;
1664 case 0x2e: /* DSP[16:23] */
1665 s->dsp &= 0xff00ffff;
1666 s->dsp |= val << 16;
1667 break;
1668 case 0x2f: /* DSP[24:31] */
1669 s->dsp &= 0x00ffffff;
1670 s->dsp |= val << 24;
1671 if ((s->dmode & LSI_DMODE_MAN) == 0
1672 && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1673 lsi_execute_script(s);
1674 break;
1675 CASE_SET_REG32(dsps, 0x30)
1676 CASE_SET_REG32(scratch[0], 0x34)
1677 case 0x38: /* DMODE */
1678 if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
1679 BADF("IO mappings not implemented\n");
1680 }
1681 s->dmode = val;
1682 break;
1683 case 0x39: /* DIEN */
1684 s->dien = val;
1685 lsi_update_irq(s);
1686 break;
1687 case 0x3a: /* SBR */
1688 s->sbr = val;
1689 break;
1690 case 0x3b: /* DCNTL */
1691 s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD);
1692 if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1693 lsi_execute_script(s);
1694 break;
1695 case 0x40: /* SIEN0 */
1696 s->sien0 = val;
1697 lsi_update_irq(s);
1698 break;
1699 case 0x41: /* SIEN1 */
1700 s->sien1 = val;
1701 lsi_update_irq(s);
1702 break;
1703 case 0x47: /* GPCNTL0 */
1704 break;
1705 case 0x48: /* STIME0 */
1706 s->stime0 = val;
1707 break;
1708 case 0x49: /* STIME1 */
1709 if (val & 0xf) {
1710 DPRINTF("General purpose timer not implemented\n");
1711 /* ??? Raising the interrupt immediately seems to be sufficient
1712 to keep the FreeBSD driver happy. */
1713 lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN);
1714 }
1715 break;
1716 case 0x4a: /* RESPID0 */
1717 s->respid0 = val;
1718 break;
1719 case 0x4b: /* RESPID1 */
1720 s->respid1 = val;
1721 break;
1722 case 0x4d: /* STEST1 */
1723 s->stest1 = val;
1724 break;
1725 case 0x4e: /* STEST2 */
1726 if (val & 1) {
1727 BADF("Low level mode not implemented\n");
1728 }
1729 s->stest2 = val;
1730 break;
1731 case 0x4f: /* STEST3 */
1732 if (val & 0x41) {
1733 BADF("SCSI FIFO test mode not implemented\n");
1734 }
1735 s->stest3 = val;
1736 break;
1737 case 0x56: /* CCNTL0 */
1738 s->ccntl0 = val;
1739 break;
1740 case 0x57: /* CCNTL1 */
1741 s->ccntl1 = val;
1742 break;
1743 CASE_SET_REG32(mmrs, 0xa0)
1744 CASE_SET_REG32(mmws, 0xa4)
1745 CASE_SET_REG32(sfs, 0xa8)
1746 CASE_SET_REG32(drs, 0xac)
1747 CASE_SET_REG32(sbms, 0xb0)
1748 CASE_SET_REG32(dbms, 0xb4)
1749 CASE_SET_REG32(dnad64, 0xb8)
1750 CASE_SET_REG32(pmjad1, 0xc0)
1751 CASE_SET_REG32(pmjad2, 0xc4)
1752 CASE_SET_REG32(rbc, 0xc8)
1753 CASE_SET_REG32(ua, 0xcc)
1754 CASE_SET_REG32(ia, 0xd4)
1755 CASE_SET_REG32(sbc, 0xd8)
1756 CASE_SET_REG32(csbc, 0xdc)
1757 default:
1758 if (offset >= 0x5c && offset < 0xa0) {
1759 int n;
1760 int shift;
1761 n = (offset - 0x58) >> 2;
1762 shift = (offset & 3) * 8;
1763 s->scratch[n] &= ~(0xff << shift);
1764 s->scratch[n] |= (val & 0xff) << shift;
1765 } else {
1766 BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
1767 }
1768 }
1769 #undef CASE_SET_REG24
1770 #undef CASE_SET_REG32
1771 }
1772
1773 static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1774 {
1775 LSIState *s = opaque;
1776
1777 lsi_reg_writeb(s, addr & 0xff, val);
1778 }
1779
1780 static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1781 {
1782 LSIState *s = opaque;
1783
1784 addr &= 0xff;
1785 lsi_reg_writeb(s, addr, val & 0xff);
1786 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1787 }
1788
1789 static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1790 {
1791 LSIState *s = opaque;
1792
1793 addr &= 0xff;
1794 lsi_reg_writeb(s, addr, val & 0xff);
1795 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1796 lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1797 lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1798 }
1799
1800 static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
1801 {
1802 LSIState *s = opaque;
1803
1804 return lsi_reg_readb(s, addr & 0xff);
1805 }
1806
1807 static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
1808 {
1809 LSIState *s = opaque;
1810 uint32_t val;
1811
1812 addr &= 0xff;
1813 val = lsi_reg_readb(s, addr);
1814 val |= lsi_reg_readb(s, addr + 1) << 8;
1815 return val;
1816 }
1817
1818 static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
1819 {
1820 LSIState *s = opaque;
1821 uint32_t val;
1822 addr &= 0xff;
1823 val = lsi_reg_readb(s, addr);
1824 val |= lsi_reg_readb(s, addr + 1) << 8;
1825 val |= lsi_reg_readb(s, addr + 2) << 16;
1826 val |= lsi_reg_readb(s, addr + 3) << 24;
1827 return val;
1828 }
1829
1830 static CPUReadMemoryFunc * const lsi_mmio_readfn[3] = {
1831 lsi_mmio_readb,
1832 lsi_mmio_readw,
1833 lsi_mmio_readl,
1834 };
1835
1836 static CPUWriteMemoryFunc * const lsi_mmio_writefn[3] = {
1837 lsi_mmio_writeb,
1838 lsi_mmio_writew,
1839 lsi_mmio_writel,
1840 };
1841
1842 static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1843 {
1844 LSIState *s = opaque;
1845 uint32_t newval;
1846 int shift;
1847
1848 addr &= 0x1fff;
1849 newval = s->script_ram[addr >> 2];
1850 shift = (addr & 3) * 8;
1851 newval &= ~(0xff << shift);
1852 newval |= val << shift;
1853 s->script_ram[addr >> 2] = newval;
1854 }
1855
1856 static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1857 {
1858 LSIState *s = opaque;
1859 uint32_t newval;
1860
1861 addr &= 0x1fff;
1862 newval = s->script_ram[addr >> 2];
1863 if (addr & 2) {
1864 newval = (newval & 0xffff) | (val << 16);
1865 } else {
1866 newval = (newval & 0xffff0000) | val;
1867 }
1868 s->script_ram[addr >> 2] = newval;
1869 }
1870
1871
1872 static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1873 {
1874 LSIState *s = opaque;
1875
1876 addr &= 0x1fff;
1877 s->script_ram[addr >> 2] = val;
1878 }
1879
1880 static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
1881 {
1882 LSIState *s = opaque;
1883 uint32_t val;
1884
1885 addr &= 0x1fff;
1886 val = s->script_ram[addr >> 2];
1887 val >>= (addr & 3) * 8;
1888 return val & 0xff;
1889 }
1890
1891 static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
1892 {
1893 LSIState *s = opaque;
1894 uint32_t val;
1895
1896 addr &= 0x1fff;
1897 val = s->script_ram[addr >> 2];
1898 if (addr & 2)
1899 val >>= 16;
1900 return le16_to_cpu(val);
1901 }
1902
1903 static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
1904 {
1905 LSIState *s = opaque;
1906
1907 addr &= 0x1fff;
1908 return le32_to_cpu(s->script_ram[addr >> 2]);
1909 }
1910
1911 static CPUReadMemoryFunc * const lsi_ram_readfn[3] = {
1912 lsi_ram_readb,
1913 lsi_ram_readw,
1914 lsi_ram_readl,
1915 };
1916
1917 static CPUWriteMemoryFunc * const lsi_ram_writefn[3] = {
1918 lsi_ram_writeb,
1919 lsi_ram_writew,
1920 lsi_ram_writel,
1921 };
1922
1923 static uint32_t lsi_io_readb(void *opaque, uint32_t addr)
1924 {
1925 LSIState *s = opaque;
1926 return lsi_reg_readb(s, addr & 0xff);
1927 }
1928
1929 static uint32_t lsi_io_readw(void *opaque, uint32_t addr)
1930 {
1931 LSIState *s = opaque;
1932 uint32_t val;
1933 addr &= 0xff;
1934 val = lsi_reg_readb(s, addr);
1935 val |= lsi_reg_readb(s, addr + 1) << 8;
1936 return val;
1937 }
1938
1939 static uint32_t lsi_io_readl(void *opaque, uint32_t addr)
1940 {
1941 LSIState *s = opaque;
1942 uint32_t val;
1943 addr &= 0xff;
1944 val = lsi_reg_readb(s, addr);
1945 val |= lsi_reg_readb(s, addr + 1) << 8;
1946 val |= lsi_reg_readb(s, addr + 2) << 16;
1947 val |= lsi_reg_readb(s, addr + 3) << 24;
1948 return val;
1949 }
1950
1951 static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val)
1952 {
1953 LSIState *s = opaque;
1954 lsi_reg_writeb(s, addr & 0xff, val);
1955 }
1956
1957 static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val)
1958 {
1959 LSIState *s = opaque;
1960 addr &= 0xff;
1961 lsi_reg_writeb(s, addr, val & 0xff);
1962 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1963 }
1964
1965 static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val)
1966 {
1967 LSIState *s = opaque;
1968 addr &= 0xff;
1969 lsi_reg_writeb(s, addr, val & 0xff);
1970 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1971 lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1972 lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1973 }
1974
1975 static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
1976 pcibus_t addr, pcibus_t size, int type)
1977 {
1978 LSIState *s = DO_UPCAST(LSIState, dev, pci_dev);
1979
1980 DPRINTF("Mapping IO at %08"FMT_PCIBUS"\n", addr);
1981
1982 register_ioport_write(addr, 256, 1, lsi_io_writeb, s);
1983 register_ioport_read(addr, 256, 1, lsi_io_readb, s);
1984 register_ioport_write(addr, 256, 2, lsi_io_writew, s);
1985 register_ioport_read(addr, 256, 2, lsi_io_readw, s);
1986 register_ioport_write(addr, 256, 4, lsi_io_writel, s);
1987 register_ioport_read(addr, 256, 4, lsi_io_readl, s);
1988 }
1989
1990 static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
1991 pcibus_t addr, pcibus_t size, int type)
1992 {
1993 LSIState *s = DO_UPCAST(LSIState, dev, pci_dev);
1994
1995 DPRINTF("Mapping ram at %08"FMT_PCIBUS"\n", addr);
1996 s->script_ram_base = addr;
1997 cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr);
1998 }
1999
2000 static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
2001 pcibus_t addr, pcibus_t size, int type)
2002 {
2003 LSIState *s = DO_UPCAST(LSIState, dev, pci_dev);
2004
2005 DPRINTF("Mapping registers at %08"FMT_PCIBUS"\n", addr);
2006 cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr);
2007 }
2008
2009 static void lsi_pre_save(void *opaque)
2010 {
2011 LSIState *s = opaque;
2012
2013 assert(s->dma_buf == NULL);
2014 assert(s->current_dma_len == 0);
2015 assert(QTAILQ_EMPTY(&s->queue));
2016 }
2017
2018 static const VMStateDescription vmstate_lsi_scsi = {
2019 .name = "lsiscsi",
2020 .version_id = 0,
2021 .minimum_version_id = 0,
2022 .minimum_version_id_old = 0,
2023 .pre_save = lsi_pre_save,
2024 .fields = (VMStateField []) {
2025 VMSTATE_PCI_DEVICE(dev, LSIState),
2026
2027 VMSTATE_INT32(carry, LSIState),
2028 VMSTATE_INT32(sense, LSIState),
2029 VMSTATE_INT32(msg_action, LSIState),
2030 VMSTATE_INT32(msg_len, LSIState),
2031 VMSTATE_BUFFER(msg, LSIState),
2032 VMSTATE_INT32(waiting, LSIState),
2033
2034 VMSTATE_UINT32(dsa, LSIState),
2035 VMSTATE_UINT32(temp, LSIState),
2036 VMSTATE_UINT32(dnad, LSIState),
2037 VMSTATE_UINT32(dbc, LSIState),
2038 VMSTATE_UINT8(istat0, LSIState),
2039 VMSTATE_UINT8(istat1, LSIState),
2040 VMSTATE_UINT8(dcmd, LSIState),
2041 VMSTATE_UINT8(dstat, LSIState),
2042 VMSTATE_UINT8(dien, LSIState),
2043 VMSTATE_UINT8(sist0, LSIState),
2044 VMSTATE_UINT8(sist1, LSIState),
2045 VMSTATE_UINT8(sien0, LSIState),
2046 VMSTATE_UINT8(sien1, LSIState),
2047 VMSTATE_UINT8(mbox0, LSIState),
2048 VMSTATE_UINT8(mbox1, LSIState),
2049 VMSTATE_UINT8(dfifo, LSIState),
2050 VMSTATE_UINT8(ctest2, LSIState),
2051 VMSTATE_UINT8(ctest3, LSIState),
2052 VMSTATE_UINT8(ctest4, LSIState),
2053 VMSTATE_UINT8(ctest5, LSIState),
2054 VMSTATE_UINT8(ccntl0, LSIState),
2055 VMSTATE_UINT8(ccntl1, LSIState),
2056 VMSTATE_UINT32(dsp, LSIState),
2057 VMSTATE_UINT32(dsps, LSIState),
2058 VMSTATE_UINT8(dmode, LSIState),
2059 VMSTATE_UINT8(dcntl, LSIState),
2060 VMSTATE_UINT8(scntl0, LSIState),
2061 VMSTATE_UINT8(scntl1, LSIState),
2062 VMSTATE_UINT8(scntl2, LSIState),
2063 VMSTATE_UINT8(scntl3, LSIState),
2064 VMSTATE_UINT8(sstat0, LSIState),
2065 VMSTATE_UINT8(sstat1, LSIState),
2066 VMSTATE_UINT8(scid, LSIState),
2067 VMSTATE_UINT8(sxfer, LSIState),
2068 VMSTATE_UINT8(socl, LSIState),
2069 VMSTATE_UINT8(sdid, LSIState),
2070 VMSTATE_UINT8(ssid, LSIState),
2071 VMSTATE_UINT8(sfbr, LSIState),
2072 VMSTATE_UINT8(stest1, LSIState),
2073 VMSTATE_UINT8(stest2, LSIState),
2074 VMSTATE_UINT8(stest3, LSIState),
2075 VMSTATE_UINT8(sidl, LSIState),
2076 VMSTATE_UINT8(stime0, LSIState),
2077 VMSTATE_UINT8(respid0, LSIState),
2078 VMSTATE_UINT8(respid1, LSIState),
2079 VMSTATE_UINT32(mmrs, LSIState),
2080 VMSTATE_UINT32(mmws, LSIState),
2081 VMSTATE_UINT32(sfs, LSIState),
2082 VMSTATE_UINT32(drs, LSIState),
2083 VMSTATE_UINT32(sbms, LSIState),
2084 VMSTATE_UINT32(dbms, LSIState),
2085 VMSTATE_UINT32(dnad64, LSIState),
2086 VMSTATE_UINT32(pmjad1, LSIState),
2087 VMSTATE_UINT32(pmjad2, LSIState),
2088 VMSTATE_UINT32(rbc, LSIState),
2089 VMSTATE_UINT32(ua, LSIState),
2090 VMSTATE_UINT32(ia, LSIState),
2091 VMSTATE_UINT32(sbc, LSIState),
2092 VMSTATE_UINT32(csbc, LSIState),
2093 VMSTATE_BUFFER_UNSAFE(scratch, LSIState, 0, 18 * sizeof(uint32_t)),
2094 VMSTATE_UINT8(sbr, LSIState),
2095
2096 VMSTATE_BUFFER_UNSAFE(script_ram, LSIState, 0, 2048 * sizeof(uint32_t)),
2097 VMSTATE_END_OF_LIST()
2098 }
2099 };
2100
2101 static int lsi_scsi_uninit(PCIDevice *d)
2102 {
2103 LSIState *s = DO_UPCAST(LSIState, dev, d);
2104
2105 cpu_unregister_io_memory(s->mmio_io_addr);
2106 cpu_unregister_io_memory(s->ram_io_addr);
2107
2108 return 0;
2109 }
2110
2111 static int lsi_scsi_init(PCIDevice *dev)
2112 {
2113 LSIState *s = DO_UPCAST(LSIState, dev, dev);
2114 uint8_t *pci_conf;
2115
2116 pci_conf = s->dev.config;
2117
2118 /* PCI Vendor ID (word) */
2119 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_LSI_LOGIC);
2120 /* PCI device ID (word) */
2121 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_LSI_53C895A);
2122 /* PCI base class code */
2123 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_SCSI);
2124 /* PCI subsystem ID */
2125 pci_conf[PCI_SUBSYSTEM_ID] = 0x00;
2126 pci_conf[PCI_SUBSYSTEM_ID + 1] = 0x10;
2127 /* PCI latency timer = 255 */
2128 pci_conf[PCI_LATENCY_TIMER] = 0xff;
2129 /* TODO: RST# value should be 0 */
2130 /* Interrupt pin 1 */
2131 pci_conf[PCI_INTERRUPT_PIN] = 0x01;
2132
2133 s->mmio_io_addr = cpu_register_io_memory(lsi_mmio_readfn,
2134 lsi_mmio_writefn, s);
2135 s->ram_io_addr = cpu_register_io_memory(lsi_ram_readfn,
2136 lsi_ram_writefn, s);
2137
2138 /* TODO: use dev and get rid of cast below */
2139 pci_register_bar((struct PCIDevice *)s, 0, 256,
2140 PCI_BASE_ADDRESS_SPACE_IO, lsi_io_mapfunc);
2141 pci_register_bar((struct PCIDevice *)s, 1, 0x400,
2142 PCI_BASE_ADDRESS_SPACE_MEMORY, lsi_mmio_mapfunc);
2143 pci_register_bar((struct PCIDevice *)s, 2, 0x2000,
2144 PCI_BASE_ADDRESS_SPACE_MEMORY, lsi_ram_mapfunc);
2145 QTAILQ_INIT(&s->queue);
2146
2147 lsi_soft_reset(s);
2148
2149 scsi_bus_new(&s->bus, &dev->qdev, 1, LSI_MAX_DEVS, lsi_command_complete);
2150 if (!dev->qdev.hotplugged) {
2151 scsi_bus_legacy_handle_cmdline(&s->bus);
2152 }
2153 return 0;
2154 }
2155
2156 static PCIDeviceInfo lsi_info = {
2157 .qdev.name = "lsi53c895a",
2158 .qdev.alias = "lsi",
2159 .qdev.size = sizeof(LSIState),
2160 .qdev.vmsd = &vmstate_lsi_scsi,
2161 .init = lsi_scsi_init,
2162 .exit = lsi_scsi_uninit,
2163 };
2164
2165 static void lsi53c895a_register_devices(void)
2166 {
2167 pci_qdev_register(&lsi_info);
2168 }
2169
2170 device_init(lsi53c895a_register_devices);
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