]>
git.proxmox.com Git - mirror_qemu.git/blob - hw/m48t59.c
2 * QEMU M48T59 NVRAM emulation for PPC PREP platform
4 * Copyright (c) 2003-2004 Jocelyn Mayer
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 #if defined(DEBUG_NVRAM)
30 #define NVRAM_PRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
32 #define NVRAM_PRINTF(fmt, args...) do { } while (0)
36 /* Hardware parameters */
43 /* Alarm & watchdog */
45 struct QEMUTimer
*alrm_timer
;
46 struct QEMUTimer
*wd_timer
;
53 /* Fake timer functions */
54 /* Generic helpers for BCD */
55 static inline uint8_t toBCD (uint8_t value
)
57 return (((value
/ 10) % 10) << 4) | (value
% 10);
60 static inline uint8_t fromBCD (uint8_t BCD
)
62 return ((BCD
>> 4) * 10) + (BCD
& 0x0F);
65 /* RTC management helpers */
66 static void get_time (m48t59_t
*NVRAM
, struct tm
*tm
)
70 t
= time(NULL
) + NVRAM
->time_offset
;
72 memcpy(tm
,localtime(&t
),sizeof(*tm
));
74 localtime_r (&t
, tm
) ;
78 static void set_time (m48t59_t
*NVRAM
, struct tm
*tm
)
82 new_time
= mktime(tm
);
84 NVRAM
->time_offset
= new_time
- now
;
87 /* Alarm management */
88 static void alarm_cb (void *opaque
)
92 m48t59_t
*NVRAM
= opaque
;
94 pic_set_irq(NVRAM
->IRQ
, 1);
95 if ((NVRAM
->buffer
[0x1FF5] & 0x80) == 0 &&
96 (NVRAM
->buffer
[0x1FF4] & 0x80) == 0 &&
97 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
98 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
99 /* Repeat once a month */
100 get_time(NVRAM
, &tm_now
);
101 memcpy(&tm
, &tm_now
, sizeof(struct tm
));
103 if (tm
.tm_mon
== 13) {
107 next_time
= mktime(&tm
);
108 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
109 (NVRAM
->buffer
[0x1FF4] & 0x80) == 0 &&
110 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
111 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
112 /* Repeat once a day */
113 next_time
= 24 * 60 * 60 + mktime(&tm_now
);
114 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
115 (NVRAM
->buffer
[0x1FF4] & 0x80) != 0 &&
116 (NVRAM
->buffer
[0x1FF3] & 0x80) == 0 &&
117 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
118 /* Repeat once an hour */
119 next_time
= 60 * 60 + mktime(&tm_now
);
120 } else if ((NVRAM
->buffer
[0x1FF5] & 0x80) != 0 &&
121 (NVRAM
->buffer
[0x1FF4] & 0x80) != 0 &&
122 (NVRAM
->buffer
[0x1FF3] & 0x80) != 0 &&
123 (NVRAM
->buffer
[0x1FF2] & 0x80) == 0) {
124 /* Repeat once a minute */
125 next_time
= 60 + mktime(&tm_now
);
127 /* Repeat once a second */
128 next_time
= 1 + mktime(&tm_now
);
130 qemu_mod_timer(NVRAM
->alrm_timer
, next_time
* 1000);
131 pic_set_irq(NVRAM
->IRQ
, 0);
135 static void get_alarm (m48t59_t
*NVRAM
, struct tm
*tm
)
138 memcpy(tm
,localtime(&NVRAM
->alarm
),sizeof(*tm
));
140 localtime_r (&NVRAM
->alarm
, tm
);
144 static void set_alarm (m48t59_t
*NVRAM
, struct tm
*tm
)
146 NVRAM
->alarm
= mktime(tm
);
147 if (NVRAM
->alrm_timer
!= NULL
) {
148 qemu_del_timer(NVRAM
->alrm_timer
);
149 NVRAM
->alrm_timer
= NULL
;
151 if (NVRAM
->alarm
- time(NULL
) > 0)
152 qemu_mod_timer(NVRAM
->alrm_timer
, NVRAM
->alarm
* 1000);
155 /* Watchdog management */
156 static void watchdog_cb (void *opaque
)
158 m48t59_t
*NVRAM
= opaque
;
160 NVRAM
->buffer
[0x1FF0] |= 0x80;
161 if (NVRAM
->buffer
[0x1FF7] & 0x80) {
162 NVRAM
->buffer
[0x1FF7] = 0x00;
163 NVRAM
->buffer
[0x1FFC] &= ~0x40;
164 /* May it be a hw CPU Reset instead ? */
165 qemu_system_reset_request();
167 pic_set_irq(NVRAM
->IRQ
, 1);
168 pic_set_irq(NVRAM
->IRQ
, 0);
172 static void set_up_watchdog (m48t59_t
*NVRAM
, uint8_t value
)
174 uint64_t interval
; /* in 1/16 seconds */
176 if (NVRAM
->wd_timer
!= NULL
) {
177 qemu_del_timer(NVRAM
->wd_timer
);
178 NVRAM
->wd_timer
= NULL
;
180 NVRAM
->buffer
[0x1FF0] &= ~0x80;
182 interval
= (1 << (2 * (value
& 0x03))) * ((value
>> 2) & 0x1F);
183 qemu_mod_timer(NVRAM
->wd_timer
, ((uint64_t)time(NULL
) * 1000) +
184 ((interval
* 1000) >> 4));
188 /* Direct access to NVRAM */
189 void m48t59_write (m48t59_t
*NVRAM
, uint32_t val
)
194 if (NVRAM
->addr
> 0x1FF8 && NVRAM
->addr
< 0x2000)
195 NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__
, NVRAM
->addr
, val
);
196 switch (NVRAM
->addr
) {
198 /* flags register : read-only */
205 tmp
= fromBCD(val
& 0x7F);
206 if (tmp
>= 0 && tmp
<= 59) {
207 get_alarm(NVRAM
, &tm
);
209 NVRAM
->buffer
[0x1FF2] = val
;
210 set_alarm(NVRAM
, &tm
);
215 tmp
= fromBCD(val
& 0x7F);
216 if (tmp
>= 0 && tmp
<= 59) {
217 get_alarm(NVRAM
, &tm
);
219 NVRAM
->buffer
[0x1FF3] = val
;
220 set_alarm(NVRAM
, &tm
);
225 tmp
= fromBCD(val
& 0x3F);
226 if (tmp
>= 0 && tmp
<= 23) {
227 get_alarm(NVRAM
, &tm
);
229 NVRAM
->buffer
[0x1FF4] = val
;
230 set_alarm(NVRAM
, &tm
);
235 tmp
= fromBCD(val
& 0x1F);
237 get_alarm(NVRAM
, &tm
);
239 NVRAM
->buffer
[0x1FF5] = val
;
240 set_alarm(NVRAM
, &tm
);
245 NVRAM
->buffer
[0x1FF6] = val
;
249 NVRAM
->buffer
[0x1FF7] = val
;
250 set_up_watchdog(NVRAM
, val
);
254 NVRAM
->buffer
[0x1FF8] = (val
& ~0xA0) | 0x90;
258 tmp
= fromBCD(val
& 0x7F);
259 if (tmp
>= 0 && tmp
<= 59) {
260 get_time(NVRAM
, &tm
);
262 set_time(NVRAM
, &tm
);
264 if ((val
& 0x80) ^ (NVRAM
->buffer
[0x1FF9] & 0x80)) {
266 NVRAM
->stop_time
= time(NULL
);
268 NVRAM
->time_offset
+= NVRAM
->stop_time
- time(NULL
);
269 NVRAM
->stop_time
= 0;
272 NVRAM
->buffer
[0x1FF9] = val
& 0x80;
276 tmp
= fromBCD(val
& 0x7F);
277 if (tmp
>= 0 && tmp
<= 59) {
278 get_time(NVRAM
, &tm
);
280 set_time(NVRAM
, &tm
);
285 tmp
= fromBCD(val
& 0x3F);
286 if (tmp
>= 0 && tmp
<= 23) {
287 get_time(NVRAM
, &tm
);
289 set_time(NVRAM
, &tm
);
293 /* day of the week / century */
294 tmp
= fromBCD(val
& 0x07);
295 get_time(NVRAM
, &tm
);
297 set_time(NVRAM
, &tm
);
298 NVRAM
->buffer
[0x1FFC] = val
& 0x40;
302 tmp
= fromBCD(val
& 0x1F);
304 get_time(NVRAM
, &tm
);
306 set_time(NVRAM
, &tm
);
311 tmp
= fromBCD(val
& 0x1F);
312 if (tmp
>= 1 && tmp
<= 12) {
313 get_time(NVRAM
, &tm
);
315 set_time(NVRAM
, &tm
);
321 if (tmp
>= 0 && tmp
<= 99) {
322 get_time(NVRAM
, &tm
);
323 tm
.tm_year
= fromBCD(val
);
324 set_time(NVRAM
, &tm
);
328 /* Check lock registers state */
329 if (NVRAM
->addr
>= 0x20 && NVRAM
->addr
<= 0x2F && (NVRAM
->lock
& 1))
331 if (NVRAM
->addr
>= 0x30 && NVRAM
->addr
<= 0x3F && (NVRAM
->lock
& 2))
333 if (NVRAM
->addr
< 0x1FF0 ||
334 (NVRAM
->addr
> 0x1FFF && NVRAM
->addr
< NVRAM
->size
)) {
335 NVRAM
->buffer
[NVRAM
->addr
] = val
& 0xFF;
341 uint32_t m48t59_read (m48t59_t
*NVRAM
)
344 uint32_t retval
= 0xFF;
346 switch (NVRAM
->addr
) {
370 /* A read resets the watchdog */
371 set_up_watchdog(NVRAM
, NVRAM
->buffer
[0x1FF7]);
378 get_time(NVRAM
, &tm
);
379 retval
= (NVRAM
->buffer
[0x1FF9] & 0x80) | toBCD(tm
.tm_sec
);
383 get_time(NVRAM
, &tm
);
384 retval
= toBCD(tm
.tm_min
);
388 get_time(NVRAM
, &tm
);
389 retval
= toBCD(tm
.tm_hour
);
392 /* day of the week / century */
393 get_time(NVRAM
, &tm
);
394 retval
= NVRAM
->buffer
[0x1FFC] | tm
.tm_wday
;
398 get_time(NVRAM
, &tm
);
399 retval
= toBCD(tm
.tm_mday
);
403 get_time(NVRAM
, &tm
);
404 retval
= toBCD(tm
.tm_mon
+ 1);
408 get_time(NVRAM
, &tm
);
409 retval
= toBCD(tm
.tm_year
);
412 /* Check lock registers state */
413 if (NVRAM
->addr
>= 0x20 && NVRAM
->addr
<= 0x2F && (NVRAM
->lock
& 1))
415 if (NVRAM
->addr
>= 0x30 && NVRAM
->addr
<= 0x3F && (NVRAM
->lock
& 2))
417 if (NVRAM
->addr
< 0x1FF0 ||
418 (NVRAM
->addr
> 0x1FFF && NVRAM
->addr
< NVRAM
->size
)) {
420 retval
= NVRAM
->buffer
[NVRAM
->addr
];
424 if (NVRAM
->addr
> 0x1FF9 && NVRAM
->addr
< 0x2000)
425 NVRAM_PRINTF("0x%08x <= 0x%08x\n", NVRAM
->addr
, retval
);
430 void m48t59_set_addr (m48t59_t
*NVRAM
, uint32_t addr
)
435 void m48t59_toggle_lock (m48t59_t
*NVRAM
, int lock
)
437 NVRAM
->lock
^= 1 << lock
;
440 /* IO access to NVRAM */
441 static void NVRAM_writeb (void *opaque
, uint32_t addr
, uint32_t val
)
443 m48t59_t
*NVRAM
= opaque
;
445 addr
-= NVRAM
->io_base
;
446 NVRAM_PRINTF("0x%08x => 0x%08x\n", addr
, val
);
449 NVRAM
->addr
&= ~0x00FF;
453 NVRAM
->addr
&= ~0xFF00;
454 NVRAM
->addr
|= val
<< 8;
457 m48t59_write(NVRAM
, val
);
458 NVRAM
->addr
= 0x0000;
465 static uint32_t NVRAM_readb (void *opaque
, uint32_t addr
)
467 m48t59_t
*NVRAM
= opaque
;
470 addr
-= NVRAM
->io_base
;
473 retval
= m48t59_read(NVRAM
);
479 NVRAM_PRINTF("0x%08x <= 0x%08x\n", addr
, retval
);
484 /* Initialisation routine */
485 m48t59_t
*m48t59_init (int IRQ
, uint32_t io_base
, uint16_t size
)
489 s
= qemu_mallocz(sizeof(m48t59_t
));
492 s
->buffer
= qemu_mallocz(size
);
499 s
->io_base
= io_base
;
501 register_ioport_read(io_base
, 0x04, 1, NVRAM_readb
, s
);
502 register_ioport_write(io_base
, 0x04, 1, NVRAM_writeb
, s
);
503 s
->alrm_timer
= qemu_new_timer(vm_clock
, &alarm_cb
, s
);
504 s
->wd_timer
= qemu_new_timer(vm_clock
, &watchdog_cb
, s
);