2 * ColdFire Interrupt Controller emulation.
4 * Copyright (c) 2007 CodeSourcery.
6 * This code is licensed under the GPL
9 #include "qemu/osdep.h"
10 #include "qapi/error.h"
11 #include "qemu/module.h"
16 #include "hw/sysbus.h"
17 #include "hw/m68k/mcf.h"
18 #include "qom/object.h"
20 #define TYPE_MCF_INTC "mcf-intc"
21 typedef struct mcf_intc_state mcf_intc_state
;
22 DECLARE_INSTANCE_CHECKER(mcf_intc_state
, MCF_INTC
,
25 struct mcf_intc_state
{
26 SysBusDevice parent_obj
;
38 static void mcf_intc_update(mcf_intc_state
*s
)
45 active
= (s
->ipr
| s
->ifr
) & s
->enabled
& ~s
->imr
;
49 for (i
= 0; i
< 64; i
++) {
50 if ((active
& 1) != 0 && s
->icr
[i
] >= best_level
) {
51 best_level
= s
->icr
[i
];
57 s
->active_vector
= ((best
== 64) ? 24 : (best
+ 64));
58 m68k_set_irq_level(s
->cpu
, best_level
, s
->active_vector
);
61 static uint64_t mcf_intc_read(void *opaque
, hwaddr addr
,
65 mcf_intc_state
*s
= (mcf_intc_state
*)opaque
;
67 if (offset
>= 0x40 && offset
< 0x80) {
68 return s
->icr
[offset
- 0x40];
72 return (uint32_t)(s
->ipr
>> 32);
74 return (uint32_t)s
->ipr
;
76 return (uint32_t)(s
->imr
>> 32);
78 return (uint32_t)s
->imr
;
80 return (uint32_t)(s
->ifr
>> 32);
82 return (uint32_t)s
->ifr
;
83 case 0xe0: /* SWIACK. */
84 return s
->active_vector
;
85 case 0xe1: case 0xe2: case 0xe3: case 0xe4:
86 case 0xe5: case 0xe6: case 0xe7:
88 qemu_log_mask(LOG_UNIMP
, "%s: LnIACK not implemented (offset 0x%02x)\n",
96 static void mcf_intc_write(void *opaque
, hwaddr addr
,
97 uint64_t val
, unsigned size
)
100 mcf_intc_state
*s
= (mcf_intc_state
*)opaque
;
101 offset
= addr
& 0xff;
102 if (offset
>= 0x40 && offset
< 0x80) {
103 int n
= offset
- 0x40;
106 s
->enabled
&= ~(1ull << n
);
108 s
->enabled
|= (1ull << n
);
113 case 0x00: case 0x04:
114 /* Ignore IPR writes. */
117 s
->imr
= (s
->imr
& 0xffffffff) | ((uint64_t)val
<< 32);
120 s
->imr
= (s
->imr
& 0xffffffff00000000ull
) | (uint32_t)val
;
126 s
->imr
|= (0x1ull
<< (val
& 0x3f));
133 s
->imr
&= ~(0x1ull
<< (val
& 0x3f));
137 qemu_log_mask(LOG_GUEST_ERROR
, "%s: Bad offset 0x%02x\n",
144 static void mcf_intc_set_irq(void *opaque
, int irq
, int level
)
146 mcf_intc_state
*s
= (mcf_intc_state
*)opaque
;
150 s
->ipr
|= 1ull << irq
;
152 s
->ipr
&= ~(1ull << irq
);
156 static void mcf_intc_reset(DeviceState
*dev
)
158 mcf_intc_state
*s
= MCF_INTC(dev
);
164 memset(s
->icr
, 0, 64);
165 s
->active_vector
= 24;
168 static const MemoryRegionOps mcf_intc_ops
= {
169 .read
= mcf_intc_read
,
170 .write
= mcf_intc_write
,
171 .endianness
= DEVICE_NATIVE_ENDIAN
,
174 static void mcf_intc_instance_init(Object
*obj
)
176 mcf_intc_state
*s
= MCF_INTC(obj
);
178 memory_region_init_io(&s
->iomem
, obj
, &mcf_intc_ops
, s
, "mcf", 0x100);
181 static void mcf_intc_class_init(ObjectClass
*oc
, void *data
)
183 DeviceClass
*dc
= DEVICE_CLASS(oc
);
185 set_bit(DEVICE_CATEGORY_MISC
, dc
->categories
);
186 dc
->reset
= mcf_intc_reset
;
189 static const TypeInfo mcf_intc_gate_info
= {
190 .name
= TYPE_MCF_INTC
,
191 .parent
= TYPE_SYS_BUS_DEVICE
,
192 .instance_size
= sizeof(mcf_intc_state
),
193 .instance_init
= mcf_intc_instance_init
,
194 .class_init
= mcf_intc_class_init
,
197 static void mcf_intc_register_types(void)
199 type_register_static(&mcf_intc_gate_info
);
202 type_init(mcf_intc_register_types
)
204 qemu_irq
*mcf_intc_init(MemoryRegion
*sysmem
,
211 dev
= qdev_new(TYPE_MCF_INTC
);
212 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
217 memory_region_add_subregion(sysmem
, base
, &s
->iomem
);
219 return qemu_allocate_irqs(mcf_intc_set_irq
, s
, 64);