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q800: allow accesses to RAM area even if less memory is available
[mirror_qemu.git] / hw / m68k / q800.c
1 /*
2 * QEMU Motorla 680x0 Macintosh hardware System Emulator
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
20 * THE SOFTWARE.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qemu/units.h"
25 #include "qemu/datadir.h"
26 #include "qemu/guest-random.h"
27 #include "sysemu/sysemu.h"
28 #include "cpu.h"
29 #include "hw/boards.h"
30 #include "hw/or-irq.h"
31 #include "elf.h"
32 #include "hw/loader.h"
33 #include "ui/console.h"
34 #include "hw/char/escc.h"
35 #include "hw/sysbus.h"
36 #include "hw/scsi/esp.h"
37 #include "standard-headers/asm-m68k/bootinfo.h"
38 #include "standard-headers/asm-m68k/bootinfo-mac.h"
39 #include "bootinfo.h"
40 #include "hw/m68k/q800.h"
41 #include "hw/m68k/q800-glue.h"
42 #include "hw/misc/mac_via.h"
43 #include "hw/misc/djmemc.h"
44 #include "hw/misc/iosb.h"
45 #include "hw/input/adb.h"
46 #include "hw/nubus/mac-nubus-bridge.h"
47 #include "hw/display/macfb.h"
48 #include "hw/block/swim.h"
49 #include "net/net.h"
50 #include "qapi/error.h"
51 #include "qemu/error-report.h"
52 #include "sysemu/qtest.h"
53 #include "sysemu/runstate.h"
54 #include "sysemu/reset.h"
55 #include "migration/vmstate.h"
56
57 #define MACROM_ADDR 0x40800000
58 #define MACROM_SIZE 0x00100000
59
60 #define MACROM_FILENAME "MacROM.bin"
61
62 #define IO_BASE 0x50000000
63 #define IO_SLICE 0x00040000
64 #define IO_SLICE_MASK (IO_SLICE - 1)
65 #define IO_SIZE 0x04000000
66
67 #define VIA_BASE (IO_BASE + 0x00000)
68 #define SONIC_PROM_BASE (IO_BASE + 0x08000)
69 #define SONIC_BASE (IO_BASE + 0x0a000)
70 #define SCC_BASE (IO_BASE + 0x0c020)
71 #define DJMEMC_BASE (IO_BASE + 0x0e000)
72 #define ESP_BASE (IO_BASE + 0x10000)
73 #define ESP_PDMA (IO_BASE + 0x10100)
74 #define ASC_BASE (IO_BASE + 0x14000)
75 #define IOSB_BASE (IO_BASE + 0x18000)
76 #define SWIM_BASE (IO_BASE + 0x1E000)
77
78 #define SONIC_PROM_SIZE 0x1000
79
80 /*
81 * the video base, whereas it a Nubus address,
82 * is needed by the kernel to have early display and
83 * thus provided by the bootloader
84 */
85 #define VIDEO_BASE 0xf9000000
86
87 #define MAC_CLOCK 3686418
88
89 /* Size of whole RAM area */
90 #define RAM_SIZE 0x40000000
91
92 /*
93 * Slot 0x9 is reserved for use by the in-built framebuffer whilst only
94 * slots 0xc, 0xd and 0xe physically exist on the Quadra 800
95 */
96 #define Q800_NUBUS_SLOTS_AVAILABLE (BIT(0x9) | BIT(0xc) | BIT(0xd) | \
97 BIT(0xe))
98
99 /* Quadra 800 machine ID */
100 #define Q800_MACHINE_ID 0xa55a2bad
101
102
103 static void main_cpu_reset(void *opaque)
104 {
105 M68kCPU *cpu = opaque;
106 CPUState *cs = CPU(cpu);
107
108 cpu_reset(cs);
109 cpu->env.aregs[7] = ldl_phys(cs->as, 0);
110 cpu->env.pc = ldl_phys(cs->as, 4);
111 }
112
113 static void rerandomize_rng_seed(void *opaque)
114 {
115 struct bi_record *rng_seed = opaque;
116 qemu_guest_getrandom_nofail((void *)rng_seed->data + 2,
117 be16_to_cpu(*(uint16_t *)rng_seed->data));
118 }
119
120 static uint8_t fake_mac_rom[] = {
121 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
122
123 /* offset: 0xa - mac_reset */
124
125 /* via2[vDirB] |= VIA2B_vPower */
126 0x20, 0x7C, 0x50, 0xF0, 0x24, 0x00, /* moveal VIA2_BASE+vDirB,%a0 */
127 0x10, 0x10, /* moveb %a0@,%d0 */
128 0x00, 0x00, 0x00, 0x04, /* orib #4,%d0 */
129 0x10, 0x80, /* moveb %d0,%a0@ */
130
131 /* via2[vBufB] &= ~VIA2B_vPower */
132 0x20, 0x7C, 0x50, 0xF0, 0x20, 0x00, /* moveal VIA2_BASE+vBufB,%a0 */
133 0x10, 0x10, /* moveb %a0@,%d0 */
134 0x02, 0x00, 0xFF, 0xFB, /* andib #-5,%d0 */
135 0x10, 0x80, /* moveb %d0,%a0@ */
136
137 /* while (true) ; */
138 0x60, 0xFE /* bras [self] */
139 };
140
141 static MemTxResult macio_alias_read(void *opaque, hwaddr addr, uint64_t *data,
142 unsigned size, MemTxAttrs attrs)
143 {
144 MemTxResult r;
145 uint32_t val;
146
147 addr &= IO_SLICE_MASK;
148 addr |= IO_BASE;
149
150 switch (size) {
151 case 4:
152 val = address_space_ldl_be(&address_space_memory, addr, attrs, &r);
153 break;
154 case 2:
155 val = address_space_lduw_be(&address_space_memory, addr, attrs, &r);
156 break;
157 case 1:
158 val = address_space_ldub(&address_space_memory, addr, attrs, &r);
159 break;
160 default:
161 g_assert_not_reached();
162 }
163
164 *data = val;
165 return r;
166 }
167
168 static MemTxResult macio_alias_write(void *opaque, hwaddr addr, uint64_t value,
169 unsigned size, MemTxAttrs attrs)
170 {
171 MemTxResult r;
172
173 addr &= IO_SLICE_MASK;
174 addr |= IO_BASE;
175
176 switch (size) {
177 case 4:
178 address_space_stl_be(&address_space_memory, addr, value, attrs, &r);
179 break;
180 case 2:
181 address_space_stw_be(&address_space_memory, addr, value, attrs, &r);
182 break;
183 case 1:
184 address_space_stb(&address_space_memory, addr, value, attrs, &r);
185 break;
186 default:
187 g_assert_not_reached();
188 }
189
190 return r;
191 }
192
193 static const MemoryRegionOps macio_alias_ops = {
194 .read_with_attrs = macio_alias_read,
195 .write_with_attrs = macio_alias_write,
196 .endianness = DEVICE_BIG_ENDIAN,
197 .valid = {
198 .min_access_size = 1,
199 .max_access_size = 4,
200 },
201 };
202
203 static uint64_t machine_id_read(void *opaque, hwaddr addr, unsigned size)
204 {
205 return Q800_MACHINE_ID;
206 }
207
208 static void machine_id_write(void *opaque, hwaddr addr, uint64_t val,
209 unsigned size)
210 {
211 return;
212 }
213
214 static const MemoryRegionOps machine_id_ops = {
215 .read = machine_id_read,
216 .write = machine_id_write,
217 .endianness = DEVICE_BIG_ENDIAN,
218 .valid = {
219 .min_access_size = 4,
220 .max_access_size = 4,
221 },
222 };
223
224 static uint64_t ramio_read(void *opaque, hwaddr addr, unsigned size)
225 {
226 return 0x0;
227 }
228
229 static void ramio_write(void *opaque, hwaddr addr, uint64_t val,
230 unsigned size)
231 {
232 return;
233 }
234
235 static const MemoryRegionOps ramio_ops = {
236 .read = ramio_read,
237 .write = ramio_write,
238 .endianness = DEVICE_BIG_ENDIAN,
239 .valid = {
240 .min_access_size = 1,
241 .max_access_size = 4,
242 },
243 };
244
245 static void q800_machine_init(MachineState *machine)
246 {
247 Q800MachineState *m = Q800_MACHINE(machine);
248 int linux_boot;
249 int32_t kernel_size;
250 uint64_t elf_entry;
251 char *filename;
252 int bios_size;
253 ram_addr_t initrd_base;
254 int32_t initrd_size;
255 MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1);
256 uint8_t *prom;
257 int i, checksum;
258 MacFbMode *macfb_mode;
259 ram_addr_t ram_size = machine->ram_size;
260 const char *kernel_filename = machine->kernel_filename;
261 const char *initrd_filename = machine->initrd_filename;
262 const char *kernel_cmdline = machine->kernel_cmdline;
263 const char *bios_name = machine->firmware ?: MACROM_FILENAME;
264 hwaddr parameters_base;
265 CPUState *cs;
266 DeviceState *dev;
267 SysBusESPState *sysbus_esp;
268 ESPState *esp;
269 SysBusDevice *sysbus;
270 BusState *adb_bus;
271 NubusBus *nubus;
272 DriveInfo *dinfo;
273 uint8_t rng_seed[32];
274
275 linux_boot = (kernel_filename != NULL);
276
277 if (ram_size > 1 * GiB) {
278 error_report("Too much memory for this machine: %" PRId64 " MiB, "
279 "maximum 1024 MiB", ram_size / MiB);
280 exit(1);
281 }
282
283 /* init CPUs */
284 object_initialize_child(OBJECT(machine), "cpu", &m->cpu, machine->cpu_type);
285 qdev_realize(DEVICE(&m->cpu), NULL, &error_fatal);
286 qemu_register_reset(main_cpu_reset, &m->cpu);
287
288 /* RAM */
289 memory_region_init_io(&m->ramio, OBJECT(machine), &ramio_ops, &m->ramio,
290 "ram", RAM_SIZE);
291 memory_region_add_subregion(get_system_memory(), 0x0, &m->ramio);
292
293 memory_region_add_subregion(&m->ramio, 0, machine->ram);
294
295 /*
296 * Create container for all IO devices
297 */
298 memory_region_init(&m->macio, OBJECT(machine), "mac-io", IO_SLICE);
299 memory_region_add_subregion(get_system_memory(), IO_BASE, &m->macio);
300
301 /*
302 * Memory from IO_BASE to IO_BASE + IO_SLICE is repeated
303 * from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE
304 */
305 memory_region_init_io(&m->macio_alias, OBJECT(machine), &macio_alias_ops,
306 &m->macio, "mac-io.alias", IO_SIZE - IO_SLICE);
307 memory_region_add_subregion(get_system_memory(), IO_BASE + IO_SLICE,
308 &m->macio_alias);
309
310 memory_region_init_io(&m->machine_id, NULL, &machine_id_ops, NULL,
311 "Machine ID", 4);
312 memory_region_add_subregion(get_system_memory(), 0x5ffffffc,
313 &m->machine_id);
314
315 /* IRQ Glue */
316 object_initialize_child(OBJECT(machine), "glue", &m->glue, TYPE_GLUE);
317 object_property_set_link(OBJECT(&m->glue), "cpu", OBJECT(&m->cpu),
318 &error_abort);
319 sysbus_realize(SYS_BUS_DEVICE(&m->glue), &error_fatal);
320
321 /* djMEMC memory controller */
322 object_initialize_child(OBJECT(machine), "djmemc", &m->djmemc,
323 TYPE_DJMEMC);
324 sysbus = SYS_BUS_DEVICE(&m->djmemc);
325 sysbus_realize_and_unref(sysbus, &error_fatal);
326 memory_region_add_subregion(&m->macio, DJMEMC_BASE - IO_BASE,
327 sysbus_mmio_get_region(sysbus, 0));
328
329 /* IOSB subsystem */
330 object_initialize_child(OBJECT(machine), "iosb", &m->iosb, TYPE_IOSB);
331 sysbus = SYS_BUS_DEVICE(&m->iosb);
332 sysbus_realize_and_unref(sysbus, &error_fatal);
333 memory_region_add_subregion(&m->macio, IOSB_BASE - IO_BASE,
334 sysbus_mmio_get_region(sysbus, 0));
335
336 /* VIA 1 */
337 object_initialize_child(OBJECT(machine), "via1", &m->via1,
338 TYPE_MOS6522_Q800_VIA1);
339 dinfo = drive_get(IF_MTD, 0, 0);
340 if (dinfo) {
341 qdev_prop_set_drive(DEVICE(&m->via1), "drive",
342 blk_by_legacy_dinfo(dinfo));
343 }
344 sysbus = SYS_BUS_DEVICE(&m->via1);
345 sysbus_realize(sysbus, &error_fatal);
346 memory_region_add_subregion(&m->macio, VIA_BASE - IO_BASE,
347 sysbus_mmio_get_region(sysbus, 1));
348 sysbus_connect_irq(sysbus, 0,
349 qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_VIA1));
350 /* A/UX mode */
351 qdev_connect_gpio_out(DEVICE(&m->via1), 0,
352 qdev_get_gpio_in_named(DEVICE(&m->glue),
353 "auxmode", 0));
354
355 adb_bus = qdev_get_child_bus(DEVICE(&m->via1), "adb.0");
356 dev = qdev_new(TYPE_ADB_KEYBOARD);
357 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
358 dev = qdev_new(TYPE_ADB_MOUSE);
359 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
360
361 /* VIA 2 */
362 object_initialize_child(OBJECT(machine), "via2", &m->via2,
363 TYPE_MOS6522_Q800_VIA2);
364 sysbus = SYS_BUS_DEVICE(&m->via2);
365 sysbus_realize(sysbus, &error_fatal);
366 memory_region_add_subregion(&m->macio, VIA_BASE - IO_BASE + VIA_SIZE,
367 sysbus_mmio_get_region(sysbus, 1));
368 sysbus_connect_irq(sysbus, 0,
369 qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_VIA2));
370
371 /* MACSONIC */
372
373 if (nb_nics > 1) {
374 error_report("q800 can only have one ethernet interface");
375 exit(1);
376 }
377
378 qemu_check_nic_model(&nd_table[0], "dp83932");
379
380 /*
381 * MacSonic driver needs an Apple MAC address
382 * Valid prefix are:
383 * 00:05:02 Apple
384 * 00:80:19 Dayna Communications, Inc.
385 * 00:A0:40 Apple
386 * 08:00:07 Apple
387 * (Q800 use the last one)
388 */
389 nd_table[0].macaddr.a[0] = 0x08;
390 nd_table[0].macaddr.a[1] = 0x00;
391 nd_table[0].macaddr.a[2] = 0x07;
392
393 object_initialize_child(OBJECT(machine), "dp8393x", &m->dp8393x,
394 TYPE_DP8393X);
395 dev = DEVICE(&m->dp8393x);
396 qdev_set_nic_properties(dev, &nd_table[0]);
397 qdev_prop_set_uint8(dev, "it_shift", 2);
398 qdev_prop_set_bit(dev, "big_endian", true);
399 object_property_set_link(OBJECT(dev), "dma_mr",
400 OBJECT(get_system_memory()), &error_abort);
401 sysbus = SYS_BUS_DEVICE(dev);
402 sysbus_realize(sysbus, &error_fatal);
403 memory_region_add_subregion(&m->macio, SONIC_BASE - IO_BASE,
404 sysbus_mmio_get_region(sysbus, 0));
405 sysbus_connect_irq(sysbus, 0,
406 qdev_get_gpio_in(DEVICE(&m->glue), GLUE_IRQ_IN_SONIC));
407
408 memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-q800.prom",
409 SONIC_PROM_SIZE, &error_fatal);
410 memory_region_add_subregion(get_system_memory(), SONIC_PROM_BASE,
411 dp8393x_prom);
412
413 /* Add MAC address with valid checksum to PROM */
414 prom = memory_region_get_ram_ptr(dp8393x_prom);
415 checksum = 0;
416 for (i = 0; i < 6; i++) {
417 prom[i] = revbit8(nd_table[0].macaddr.a[i]);
418 checksum ^= prom[i];
419 }
420 prom[7] = 0xff - checksum;
421
422 /* SCC */
423
424 object_initialize_child(OBJECT(machine), "escc", &m->escc,
425 TYPE_ESCC);
426 dev = DEVICE(&m->escc);
427 qdev_prop_set_uint32(dev, "disabled", 0);
428 qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK);
429 qdev_prop_set_uint32(dev, "it_shift", 1);
430 qdev_prop_set_bit(dev, "bit_swap", true);
431 qdev_prop_set_chr(dev, "chrA", serial_hd(0));
432 qdev_prop_set_chr(dev, "chrB", serial_hd(1));
433 qdev_prop_set_uint32(dev, "chnBtype", 0);
434 qdev_prop_set_uint32(dev, "chnAtype", 0);
435 sysbus = SYS_BUS_DEVICE(dev);
436 sysbus_realize(sysbus, &error_fatal);
437
438 /* Logically OR both its IRQs together */
439 object_initialize_child(OBJECT(machine), "escc_orgate", &m->escc_orgate,
440 TYPE_OR_IRQ);
441 object_property_set_int(OBJECT(&m->escc_orgate), "num-lines", 2,
442 &error_fatal);
443 dev = DEVICE(&m->escc_orgate);
444 qdev_realize(dev, NULL, &error_fatal);
445 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(dev, 0));
446 sysbus_connect_irq(sysbus, 1, qdev_get_gpio_in(dev, 1));
447 qdev_connect_gpio_out(dev, 0,
448 qdev_get_gpio_in(DEVICE(&m->glue),
449 GLUE_IRQ_IN_ESCC));
450 memory_region_add_subregion(&m->macio, SCC_BASE - IO_BASE,
451 sysbus_mmio_get_region(sysbus, 0));
452
453 /* SCSI */
454
455 object_initialize_child(OBJECT(machine), "esp", &m->esp,
456 TYPE_SYSBUS_ESP);
457 sysbus_esp = SYSBUS_ESP(&m->esp);
458 esp = &sysbus_esp->esp;
459 esp->dma_memory_read = NULL;
460 esp->dma_memory_write = NULL;
461 esp->dma_opaque = NULL;
462 sysbus_esp->it_shift = 4;
463 esp->dma_enabled = 1;
464
465 sysbus = SYS_BUS_DEVICE(&m->esp);
466 sysbus_realize(sysbus, &error_fatal);
467 /* SCSI and SCSI data IRQs are negative edge triggered */
468 sysbus_connect_irq(sysbus, 0,
469 qemu_irq_invert(
470 qdev_get_gpio_in(DEVICE(&m->via2),
471 VIA2_IRQ_SCSI_BIT)));
472 sysbus_connect_irq(sysbus, 1,
473 qemu_irq_invert(
474 qdev_get_gpio_in(DEVICE(&m->via2),
475 VIA2_IRQ_SCSI_DATA_BIT)));
476 memory_region_add_subregion(&m->macio, ESP_BASE - IO_BASE,
477 sysbus_mmio_get_region(sysbus, 0));
478 memory_region_add_subregion(&m->macio, ESP_PDMA - IO_BASE,
479 sysbus_mmio_get_region(sysbus, 1));
480
481 scsi_bus_legacy_handle_cmdline(&esp->bus);
482
483 /* SWIM floppy controller */
484
485 object_initialize_child(OBJECT(machine), "swim", &m->swim,
486 TYPE_SWIM);
487 sysbus = SYS_BUS_DEVICE(&m->swim);
488 sysbus_realize(sysbus, &error_fatal);
489 memory_region_add_subregion(&m->macio, SWIM_BASE - IO_BASE,
490 sysbus_mmio_get_region(sysbus, 0));
491
492 /* NuBus */
493
494 object_initialize_child(OBJECT(machine), "mac-nubus-bridge",
495 &m->mac_nubus_bridge,
496 TYPE_MAC_NUBUS_BRIDGE);
497 sysbus = SYS_BUS_DEVICE(&m->mac_nubus_bridge);
498 dev = DEVICE(&m->mac_nubus_bridge);
499 qdev_prop_set_uint32(DEVICE(&m->mac_nubus_bridge), "slot-available-mask",
500 Q800_NUBUS_SLOTS_AVAILABLE);
501 sysbus_realize(sysbus, &error_fatal);
502 memory_region_add_subregion(get_system_memory(),
503 MAC_NUBUS_FIRST_SLOT * NUBUS_SUPER_SLOT_SIZE,
504 sysbus_mmio_get_region(sysbus, 0));
505 memory_region_add_subregion(get_system_memory(),
506 NUBUS_SLOT_BASE +
507 MAC_NUBUS_FIRST_SLOT * NUBUS_SLOT_SIZE,
508 sysbus_mmio_get_region(sysbus, 1));
509 qdev_connect_gpio_out(dev, 9,
510 qdev_get_gpio_in_named(DEVICE(&m->via2), "nubus-irq",
511 VIA2_NUBUS_IRQ_INTVIDEO));
512 for (i = 1; i < VIA2_NUBUS_IRQ_NB; i++) {
513 qdev_connect_gpio_out(dev, 9 + i,
514 qdev_get_gpio_in_named(DEVICE(&m->via2),
515 "nubus-irq",
516 VIA2_NUBUS_IRQ_9 + i));
517 }
518
519 /*
520 * Since the framebuffer in slot 0x9 uses a separate IRQ, wire the unused
521 * IRQ via GLUE for use by SONIC Ethernet in classic mode
522 */
523 qdev_connect_gpio_out(DEVICE(&m->glue), GLUE_IRQ_NUBUS_9,
524 qdev_get_gpio_in_named(DEVICE(&m->via2), "nubus-irq",
525 VIA2_NUBUS_IRQ_9));
526
527 nubus = NUBUS_BUS(qdev_get_child_bus(dev, "nubus-bus.0"));
528
529 /* framebuffer in nubus slot #9 */
530
531 object_initialize_child(OBJECT(machine), "macfb", &m->macfb,
532 TYPE_NUBUS_MACFB);
533 dev = DEVICE(&m->macfb);
534 qdev_prop_set_uint32(dev, "slot", 9);
535 qdev_prop_set_uint32(dev, "width", graphic_width);
536 qdev_prop_set_uint32(dev, "height", graphic_height);
537 qdev_prop_set_uint8(dev, "depth", graphic_depth);
538 if (graphic_width == 1152 && graphic_height == 870) {
539 qdev_prop_set_uint8(dev, "display", MACFB_DISPLAY_APPLE_21_COLOR);
540 } else {
541 qdev_prop_set_uint8(dev, "display", MACFB_DISPLAY_VGA);
542 }
543 qdev_realize(dev, BUS(nubus), &error_fatal);
544
545 macfb_mode = (NUBUS_MACFB(dev)->macfb).mode;
546
547 cs = CPU(&m->cpu);
548 if (linux_boot) {
549 uint64_t high;
550 void *param_blob, *param_ptr, *param_rng_seed;
551
552 if (kernel_cmdline) {
553 param_blob = g_malloc(strlen(kernel_cmdline) + 1024);
554 } else {
555 param_blob = g_malloc(1024);
556 }
557
558 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
559 &elf_entry, NULL, &high, NULL, 1,
560 EM_68K, 0, 0);
561 if (kernel_size < 0) {
562 error_report("could not load kernel '%s'", kernel_filename);
563 exit(1);
564 }
565 stl_phys(cs->as, 4, elf_entry); /* reset initial PC */
566 parameters_base = (high + 1) & ~1;
567 param_ptr = param_blob;
568
569 BOOTINFO1(param_ptr, BI_MACHTYPE, MACH_MAC);
570 BOOTINFO1(param_ptr, BI_FPUTYPE, FPU_68040);
571 BOOTINFO1(param_ptr, BI_MMUTYPE, MMU_68040);
572 BOOTINFO1(param_ptr, BI_CPUTYPE, CPU_68040);
573 BOOTINFO1(param_ptr, BI_MAC_CPUID, CPUB_68040);
574 BOOTINFO1(param_ptr, BI_MAC_MODEL, MAC_MODEL_Q800);
575 BOOTINFO1(param_ptr,
576 BI_MAC_MEMSIZE, ram_size >> 20); /* in MB */
577 BOOTINFO2(param_ptr, BI_MEMCHUNK, 0, ram_size);
578 BOOTINFO1(param_ptr, BI_MAC_VADDR,
579 VIDEO_BASE + macfb_mode->offset);
580 BOOTINFO1(param_ptr, BI_MAC_VDEPTH, graphic_depth);
581 BOOTINFO1(param_ptr, BI_MAC_VDIM,
582 (graphic_height << 16) | graphic_width);
583 BOOTINFO1(param_ptr, BI_MAC_VROW, macfb_mode->stride);
584 BOOTINFO1(param_ptr, BI_MAC_SCCBASE, SCC_BASE);
585
586 memory_region_init_ram_ptr(&m->rom, NULL, "m68k_fake_mac.rom",
587 sizeof(fake_mac_rom), fake_mac_rom);
588 memory_region_set_readonly(&m->rom, true);
589 memory_region_add_subregion(get_system_memory(), MACROM_ADDR, &m->rom);
590
591 if (kernel_cmdline) {
592 BOOTINFOSTR(param_ptr, BI_COMMAND_LINE,
593 kernel_cmdline);
594 }
595
596 /* Pass seed to RNG. */
597 param_rng_seed = param_ptr;
598 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
599 BOOTINFODATA(param_ptr, BI_RNG_SEED,
600 rng_seed, sizeof(rng_seed));
601
602 /* load initrd */
603 if (initrd_filename) {
604 initrd_size = get_image_size(initrd_filename);
605 if (initrd_size < 0) {
606 error_report("could not load initial ram disk '%s'",
607 initrd_filename);
608 exit(1);
609 }
610
611 initrd_base = (ram_size - initrd_size) & TARGET_PAGE_MASK;
612 load_image_targphys(initrd_filename, initrd_base,
613 ram_size - initrd_base);
614 BOOTINFO2(param_ptr, BI_RAMDISK, initrd_base,
615 initrd_size);
616 } else {
617 initrd_base = 0;
618 initrd_size = 0;
619 }
620 BOOTINFO0(param_ptr, BI_LAST);
621 rom_add_blob_fixed_as("bootinfo", param_blob, param_ptr - param_blob,
622 parameters_base, cs->as);
623 qemu_register_reset_nosnapshotload(rerandomize_rng_seed,
624 rom_ptr_for_as(cs->as, parameters_base,
625 param_ptr - param_blob) +
626 (param_rng_seed - param_blob));
627 g_free(param_blob);
628 } else {
629 uint8_t *ptr;
630 /* allocate and load BIOS */
631 memory_region_init_rom(&m->rom, NULL, "m68k_mac.rom", MACROM_SIZE,
632 &error_abort);
633 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
634 memory_region_add_subregion(get_system_memory(), MACROM_ADDR, &m->rom);
635
636 /* Load MacROM binary */
637 if (filename) {
638 bios_size = load_image_targphys(filename, MACROM_ADDR, MACROM_SIZE);
639 g_free(filename);
640 } else {
641 bios_size = -1;
642 }
643
644 /* Remove qtest_enabled() check once firmware files are in the tree */
645 if (!qtest_enabled()) {
646 if (bios_size <= 0 || bios_size > MACROM_SIZE) {
647 error_report("could not load MacROM '%s'", bios_name);
648 exit(1);
649 }
650
651 ptr = rom_ptr(MACROM_ADDR, bios_size);
652 assert(ptr != NULL);
653 stl_phys(cs->as, 0, ldl_p(ptr)); /* reset initial SP */
654 stl_phys(cs->as, 4,
655 MACROM_ADDR + ldl_p(ptr + 4)); /* reset initial PC */
656 }
657 }
658 }
659
660 static GlobalProperty hw_compat_q800[] = {
661 { "scsi-hd", "quirk_mode_page_vendor_specific_apple", "on" },
662 { "scsi-hd", "vendor", " SEAGATE" },
663 { "scsi-hd", "product", " ST225N" },
664 { "scsi-hd", "ver", "1.0 " },
665 { "scsi-cd", "quirk_mode_page_apple_vendor", "on" },
666 { "scsi-cd", "quirk_mode_sense_rom_use_dbd", "on" },
667 { "scsi-cd", "quirk_mode_page_vendor_specific_apple", "on" },
668 { "scsi-cd", "quirk_mode_page_truncated", "on" },
669 { "scsi-cd", "vendor", "MATSHITA" },
670 { "scsi-cd", "product", "CD-ROM CR-8005" },
671 { "scsi-cd", "ver", "1.0k" },
672 };
673 static const size_t hw_compat_q800_len = G_N_ELEMENTS(hw_compat_q800);
674
675 static const char *q800_machine_valid_cpu_types[] = {
676 M68K_CPU_TYPE_NAME("m68040"),
677 NULL
678 };
679
680 static void q800_machine_class_init(ObjectClass *oc, void *data)
681 {
682 MachineClass *mc = MACHINE_CLASS(oc);
683
684 mc->desc = "Macintosh Quadra 800";
685 mc->init = q800_machine_init;
686 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
687 mc->valid_cpu_types = q800_machine_valid_cpu_types;
688 mc->max_cpus = 1;
689 mc->block_default_type = IF_SCSI;
690 mc->default_ram_id = "m68k_mac.ram";
691 compat_props_add(mc->compat_props, hw_compat_q800, hw_compat_q800_len);
692 }
693
694 static const TypeInfo q800_machine_typeinfo = {
695 .name = MACHINE_TYPE_NAME("q800"),
696 .parent = TYPE_MACHINE,
697 .instance_size = sizeof(Q800MachineState),
698 .class_init = q800_machine_class_init,
699 };
700
701 static void q800_machine_register_types(void)
702 {
703 type_register_static(&q800_machine_typeinfo);
704 }
705
706 type_init(q800_machine_register_types)
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