2 * QEMU Motorla 680x0 Macintosh hardware System Emulator
4 * Permission is hereby granted, free of charge, to any person obtaining a copy
5 * of this software and associated documentation files (the "Software"), to deal
6 * in the Software without restriction, including without limitation the rights
7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
8 * copies of the Software, and to permit persons to whom the Software is
9 * furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 #include "qemu/osdep.h"
24 #include "qemu/units.h"
25 #include "qemu/datadir.h"
26 #include "qemu/guest-random.h"
27 #include "sysemu/sysemu.h"
29 #include "hw/boards.h"
30 #include "hw/or-irq.h"
33 #include "hw/loader.h"
34 #include "ui/console.h"
35 #include "hw/char/escc.h"
36 #include "hw/sysbus.h"
37 #include "hw/scsi/esp.h"
38 #include "standard-headers/asm-m68k/bootinfo.h"
39 #include "standard-headers/asm-m68k/bootinfo-mac.h"
41 #include "hw/m68k/q800.h"
42 #include "hw/misc/mac_via.h"
43 #include "hw/input/adb.h"
44 #include "hw/nubus/mac-nubus-bridge.h"
45 #include "hw/display/macfb.h"
46 #include "hw/block/swim.h"
48 #include "qapi/error.h"
49 #include "qemu/error-report.h"
50 #include "sysemu/qtest.h"
51 #include "sysemu/runstate.h"
52 #include "sysemu/reset.h"
53 #include "migration/vmstate.h"
55 #define MACROM_ADDR 0x40800000
56 #define MACROM_SIZE 0x00100000
58 #define MACROM_FILENAME "MacROM.bin"
60 #define IO_BASE 0x50000000
61 #define IO_SLICE 0x00040000
62 #define IO_SIZE 0x04000000
64 #define VIA_BASE (IO_BASE + 0x00000)
65 #define SONIC_PROM_BASE (IO_BASE + 0x08000)
66 #define SONIC_BASE (IO_BASE + 0x0a000)
67 #define SCC_BASE (IO_BASE + 0x0c020)
68 #define ESP_BASE (IO_BASE + 0x10000)
69 #define ESP_PDMA (IO_BASE + 0x10100)
70 #define ASC_BASE (IO_BASE + 0x14000)
71 #define SWIM_BASE (IO_BASE + 0x1E000)
73 #define SONIC_PROM_SIZE 0x1000
76 * the video base, whereas it a Nubus address,
77 * is needed by the kernel to have early display and
78 * thus provided by the bootloader
80 #define VIDEO_BASE 0xf9000000
82 #define MAC_CLOCK 3686418
85 * Slot 0x9 is reserved for use by the in-built framebuffer whilst only
86 * slots 0xc, 0xd and 0xe physically exist on the Quadra 800
88 #define Q800_NUBUS_SLOTS_AVAILABLE (BIT(0x9) | BIT(0xc) | BIT(0xd) | \
92 * The GLUE (General Logic Unit) is an Apple custom integrated circuit chip
93 * that performs a variety of functions (RAM management, clock generation, ...).
94 * The GLUE chip receives interrupt requests from various devices,
95 * assign priority to each, and asserts one or more interrupt line to the
99 #define TYPE_GLUE "q800-glue"
100 OBJECT_DECLARE_SIMPLE_TYPE(GLUEState
, GLUE
)
103 SysBusDevice parent_obj
;
109 QEMUTimer
*nmi_release
;
112 #define GLUE_IRQ_IN_VIA1 0
113 #define GLUE_IRQ_IN_VIA2 1
114 #define GLUE_IRQ_IN_SONIC 2
115 #define GLUE_IRQ_IN_ESCC 3
116 #define GLUE_IRQ_IN_NMI 4
118 #define GLUE_IRQ_NUBUS_9 0
121 * The GLUE logic on the Quadra 800 supports 2 different IRQ routing modes
122 * controlled from the VIA1 auxmode GPIO (port B bit 6) which are documented
123 * in NetBSD as follows:
125 * A/UX mode (Linux, NetBSD, auxmode GPIO low)
127 * Level 0: Spurious: ignored
129 * Level 2: VIA2 (except ethernet, sound)
131 * Level 4: Serial (SCC)
134 * Level 7: NMIs: parity errors, RESET button, YANCC error
136 * Classic mode (default: used by MacOS, A/UX 3.0.1, auxmode GPIO high)
138 * Level 0: Spurious: ignored
139 * Level 1: VIA1 (clock, ADB)
140 * Level 2: VIA2 (NuBus, SCSI)
142 * Level 4: Serial (SCC)
145 * Level 7: Non-maskable: parity errors, RESET button
147 * Note that despite references to A/UX mode in Linux and NetBSD, at least
148 * A/UX 3.0.1 still uses Classic mode.
151 static void GLUE_set_irq(void *opaque
, int irq
, int level
)
153 GLUEState
*s
= opaque
;
159 case GLUE_IRQ_IN_VIA1
:
163 case GLUE_IRQ_IN_VIA2
:
167 case GLUE_IRQ_IN_SONIC
:
168 /* Route to VIA2 instead */
169 qemu_set_irq(s
->irqs
[GLUE_IRQ_NUBUS_9
], level
);
172 case GLUE_IRQ_IN_ESCC
:
176 case GLUE_IRQ_IN_NMI
:
181 g_assert_not_reached();
186 case GLUE_IRQ_IN_VIA1
:
190 case GLUE_IRQ_IN_VIA2
:
194 case GLUE_IRQ_IN_SONIC
:
198 case GLUE_IRQ_IN_ESCC
:
202 case GLUE_IRQ_IN_NMI
:
207 g_assert_not_reached();
214 s
->ipr
&= ~(1 << irq
);
217 for (i
= 7; i
>= 0; i
--) {
218 if ((s
->ipr
>> i
) & 1) {
219 m68k_set_irq_level(s
->cpu
, i
+ 1, i
+ 25);
223 m68k_set_irq_level(s
->cpu
, 0, 0);
226 static void glue_auxmode_set_irq(void *opaque
, int irq
, int level
)
228 GLUEState
*s
= GLUE(opaque
);
233 static void glue_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
235 GLUEState
*s
= GLUE(n
);
237 /* Hold NMI active for 100ms */
238 GLUE_set_irq(s
, GLUE_IRQ_IN_NMI
, 1);
239 timer_mod(s
->nmi_release
, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + 100);
242 static void glue_nmi_release(void *opaque
)
244 GLUEState
*s
= GLUE(opaque
);
246 GLUE_set_irq(s
, GLUE_IRQ_IN_NMI
, 0);
249 static void glue_reset(DeviceState
*dev
)
251 GLUEState
*s
= GLUE(dev
);
256 timer_del(s
->nmi_release
);
259 static const VMStateDescription vmstate_glue
= {
262 .minimum_version_id
= 0,
263 .fields
= (VMStateField
[]) {
264 VMSTATE_UINT8(ipr
, GLUEState
),
265 VMSTATE_UINT8(auxmode
, GLUEState
),
266 VMSTATE_TIMER_PTR(nmi_release
, GLUEState
),
267 VMSTATE_END_OF_LIST(),
272 * If the m68k CPU implemented its inbound irq lines as GPIO lines
273 * rather than via the m68k_set_irq_level() function we would not need
274 * this cpu link property and could instead provide outbound IRQ lines
275 * that the board could wire up to the CPU.
277 static Property glue_properties
[] = {
278 DEFINE_PROP_LINK("cpu", GLUEState
, cpu
, TYPE_M68K_CPU
, M68kCPU
*),
279 DEFINE_PROP_END_OF_LIST(),
282 static void glue_finalize(Object
*obj
)
284 GLUEState
*s
= GLUE(obj
);
286 timer_free(s
->nmi_release
);
289 static void glue_init(Object
*obj
)
291 DeviceState
*dev
= DEVICE(obj
);
292 GLUEState
*s
= GLUE(dev
);
294 qdev_init_gpio_in(dev
, GLUE_set_irq
, 8);
295 qdev_init_gpio_in_named(dev
, glue_auxmode_set_irq
, "auxmode", 1);
297 qdev_init_gpio_out(dev
, s
->irqs
, 1);
299 /* NMI release timer */
300 s
->nmi_release
= timer_new_ms(QEMU_CLOCK_VIRTUAL
, glue_nmi_release
, s
);
303 static void glue_class_init(ObjectClass
*klass
, void *data
)
305 DeviceClass
*dc
= DEVICE_CLASS(klass
);
306 NMIClass
*nc
= NMI_CLASS(klass
);
308 dc
->vmsd
= &vmstate_glue
;
309 dc
->reset
= glue_reset
;
310 device_class_set_props(dc
, glue_properties
);
311 nc
->nmi_monitor_handler
= glue_nmi
;
314 static const TypeInfo glue_info
= {
316 .parent
= TYPE_SYS_BUS_DEVICE
,
317 .instance_size
= sizeof(GLUEState
),
318 .instance_init
= glue_init
,
319 .instance_finalize
= glue_finalize
,
320 .class_init
= glue_class_init
,
321 .interfaces
= (InterfaceInfo
[]) {
327 static void main_cpu_reset(void *opaque
)
329 M68kCPU
*cpu
= opaque
;
330 CPUState
*cs
= CPU(cpu
);
333 cpu
->env
.aregs
[7] = ldl_phys(cs
->as
, 0);
334 cpu
->env
.pc
= ldl_phys(cs
->as
, 4);
337 static void rerandomize_rng_seed(void *opaque
)
339 struct bi_record
*rng_seed
= opaque
;
340 qemu_guest_getrandom_nofail((void *)rng_seed
->data
+ 2,
341 be16_to_cpu(*(uint16_t *)rng_seed
->data
));
344 static uint8_t fake_mac_rom
[] = {
345 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
347 /* offset: 0xa - mac_reset */
349 /* via2[vDirB] |= VIA2B_vPower */
350 0x20, 0x7C, 0x50, 0xF0, 0x24, 0x00, /* moveal VIA2_BASE+vDirB,%a0 */
351 0x10, 0x10, /* moveb %a0@,%d0 */
352 0x00, 0x00, 0x00, 0x04, /* orib #4,%d0 */
353 0x10, 0x80, /* moveb %d0,%a0@ */
355 /* via2[vBufB] &= ~VIA2B_vPower */
356 0x20, 0x7C, 0x50, 0xF0, 0x20, 0x00, /* moveal VIA2_BASE+vBufB,%a0 */
357 0x10, 0x10, /* moveb %a0@,%d0 */
358 0x02, 0x00, 0xFF, 0xFB, /* andib #-5,%d0 */
359 0x10, 0x80, /* moveb %d0,%a0@ */
362 0x60, 0xFE /* bras [self] */
365 static void q800_init(MachineState
*machine
)
373 ram_addr_t initrd_base
;
377 MemoryRegion
*dp8393x_prom
= g_new(MemoryRegion
, 1);
379 const int io_slice_nb
= (IO_SIZE
/ IO_SLICE
) - 1;
381 MacFbMode
*macfb_mode
;
382 ram_addr_t ram_size
= machine
->ram_size
;
383 const char *kernel_filename
= machine
->kernel_filename
;
384 const char *initrd_filename
= machine
->initrd_filename
;
385 const char *kernel_cmdline
= machine
->kernel_cmdline
;
386 const char *bios_name
= machine
->firmware
?: MACROM_FILENAME
;
387 hwaddr parameters_base
;
390 DeviceState
*via1_dev
, *via2_dev
;
391 DeviceState
*escc_orgate
;
392 SysBusESPState
*sysbus_esp
;
394 SysBusDevice
*sysbus
;
399 uint8_t rng_seed
[32];
401 linux_boot
= (kernel_filename
!= NULL
);
403 if (ram_size
> 1 * GiB
) {
404 error_report("Too much memory for this machine: %" PRId64
" MiB, "
405 "maximum 1024 MiB", ram_size
/ MiB
);
410 cpu
= M68K_CPU(cpu_create(machine
->cpu_type
));
411 qemu_register_reset(main_cpu_reset
, cpu
);
414 memory_region_add_subregion(get_system_memory(), 0, machine
->ram
);
417 * Memory from IO_BASE to IO_BASE + IO_SLICE is repeated
418 * from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE
420 io
= g_new(MemoryRegion
, io_slice_nb
);
421 for (i
= 0; i
< io_slice_nb
; i
++) {
422 char *name
= g_strdup_printf("mac_m68k.io[%d]", i
+ 1);
424 memory_region_init_alias(&io
[i
], NULL
, name
, get_system_memory(),
426 memory_region_add_subregion(get_system_memory(),
427 IO_BASE
+ (i
+ 1) * IO_SLICE
, &io
[i
]);
432 glue
= qdev_new(TYPE_GLUE
);
433 object_property_set_link(OBJECT(glue
), "cpu", OBJECT(cpu
), &error_abort
);
434 sysbus_realize_and_unref(SYS_BUS_DEVICE(glue
), &error_fatal
);
437 via1_dev
= qdev_new(TYPE_MOS6522_Q800_VIA1
);
438 dinfo
= drive_get(IF_MTD
, 0, 0);
440 qdev_prop_set_drive(via1_dev
, "drive", blk_by_legacy_dinfo(dinfo
));
442 sysbus
= SYS_BUS_DEVICE(via1_dev
);
443 sysbus_realize_and_unref(sysbus
, &error_fatal
);
444 sysbus_mmio_map(sysbus
, 1, VIA_BASE
);
445 sysbus_connect_irq(sysbus
, 0, qdev_get_gpio_in(glue
, GLUE_IRQ_IN_VIA1
));
447 qdev_connect_gpio_out(via1_dev
, 0,
448 qdev_get_gpio_in_named(glue
, "auxmode", 0));
450 adb_bus
= qdev_get_child_bus(via1_dev
, "adb.0");
451 dev
= qdev_new(TYPE_ADB_KEYBOARD
);
452 qdev_realize_and_unref(dev
, adb_bus
, &error_fatal
);
453 dev
= qdev_new(TYPE_ADB_MOUSE
);
454 qdev_realize_and_unref(dev
, adb_bus
, &error_fatal
);
457 via2_dev
= qdev_new(TYPE_MOS6522_Q800_VIA2
);
458 sysbus
= SYS_BUS_DEVICE(via2_dev
);
459 sysbus_realize_and_unref(sysbus
, &error_fatal
);
460 sysbus_mmio_map(sysbus
, 1, VIA_BASE
+ VIA_SIZE
);
461 sysbus_connect_irq(sysbus
, 0, qdev_get_gpio_in(glue
, GLUE_IRQ_IN_VIA2
));
466 error_report("q800 can only have one ethernet interface");
470 qemu_check_nic_model(&nd_table
[0], "dp83932");
473 * MacSonic driver needs an Apple MAC address
476 * 00:80:19 Dayna Communications, Inc.
479 * (Q800 use the last one)
481 nd_table
[0].macaddr
.a
[0] = 0x08;
482 nd_table
[0].macaddr
.a
[1] = 0x00;
483 nd_table
[0].macaddr
.a
[2] = 0x07;
485 dev
= qdev_new("dp8393x");
486 qdev_set_nic_properties(dev
, &nd_table
[0]);
487 qdev_prop_set_uint8(dev
, "it_shift", 2);
488 qdev_prop_set_bit(dev
, "big_endian", true);
489 object_property_set_link(OBJECT(dev
), "dma_mr",
490 OBJECT(get_system_memory()), &error_abort
);
491 sysbus
= SYS_BUS_DEVICE(dev
);
492 sysbus_realize_and_unref(sysbus
, &error_fatal
);
493 sysbus_mmio_map(sysbus
, 0, SONIC_BASE
);
494 sysbus_connect_irq(sysbus
, 0, qdev_get_gpio_in(glue
, GLUE_IRQ_IN_SONIC
));
496 memory_region_init_rom(dp8393x_prom
, NULL
, "dp8393x-q800.prom",
497 SONIC_PROM_SIZE
, &error_fatal
);
498 memory_region_add_subregion(get_system_memory(), SONIC_PROM_BASE
,
501 /* Add MAC address with valid checksum to PROM */
502 prom
= memory_region_get_ram_ptr(dp8393x_prom
);
504 for (i
= 0; i
< 6; i
++) {
505 prom
[i
] = revbit8(nd_table
[0].macaddr
.a
[i
]);
508 prom
[7] = 0xff - checksum
;
512 dev
= qdev_new(TYPE_ESCC
);
513 qdev_prop_set_uint32(dev
, "disabled", 0);
514 qdev_prop_set_uint32(dev
, "frequency", MAC_CLOCK
);
515 qdev_prop_set_uint32(dev
, "it_shift", 1);
516 qdev_prop_set_bit(dev
, "bit_swap", true);
517 qdev_prop_set_chr(dev
, "chrA", serial_hd(0));
518 qdev_prop_set_chr(dev
, "chrB", serial_hd(1));
519 qdev_prop_set_uint32(dev
, "chnBtype", 0);
520 qdev_prop_set_uint32(dev
, "chnAtype", 0);
521 sysbus
= SYS_BUS_DEVICE(dev
);
522 sysbus_realize_and_unref(sysbus
, &error_fatal
);
524 /* Logically OR both its IRQs together */
525 escc_orgate
= DEVICE(object_new(TYPE_OR_IRQ
));
526 object_property_set_int(OBJECT(escc_orgate
), "num-lines", 2, &error_fatal
);
527 qdev_realize_and_unref(escc_orgate
, NULL
, &error_fatal
);
528 sysbus_connect_irq(sysbus
, 0, qdev_get_gpio_in(escc_orgate
, 0));
529 sysbus_connect_irq(sysbus
, 1, qdev_get_gpio_in(escc_orgate
, 1));
530 qdev_connect_gpio_out(escc_orgate
, 0,
531 qdev_get_gpio_in(glue
, GLUE_IRQ_IN_ESCC
));
532 sysbus_mmio_map(sysbus
, 0, SCC_BASE
);
536 dev
= qdev_new(TYPE_SYSBUS_ESP
);
537 sysbus_esp
= SYSBUS_ESP(dev
);
538 esp
= &sysbus_esp
->esp
;
539 esp
->dma_memory_read
= NULL
;
540 esp
->dma_memory_write
= NULL
;
541 esp
->dma_opaque
= NULL
;
542 sysbus_esp
->it_shift
= 4;
543 esp
->dma_enabled
= 1;
545 sysbus
= SYS_BUS_DEVICE(dev
);
546 sysbus_realize_and_unref(sysbus
, &error_fatal
);
547 /* SCSI and SCSI data IRQs are negative edge triggered */
548 sysbus_connect_irq(sysbus
, 0, qemu_irq_invert(qdev_get_gpio_in(via2_dev
,
549 VIA2_IRQ_SCSI_BIT
)));
550 sysbus_connect_irq(sysbus
, 1, qemu_irq_invert(qdev_get_gpio_in(via2_dev
,
551 VIA2_IRQ_SCSI_DATA_BIT
)));
552 sysbus_mmio_map(sysbus
, 0, ESP_BASE
);
553 sysbus_mmio_map(sysbus
, 1, ESP_PDMA
);
555 scsi_bus_legacy_handle_cmdline(&esp
->bus
);
557 /* SWIM floppy controller */
559 dev
= qdev_new(TYPE_SWIM
);
560 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
561 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, SWIM_BASE
);
565 dev
= qdev_new(TYPE_MAC_NUBUS_BRIDGE
);
566 qdev_prop_set_uint32(dev
, "slot-available-mask",
567 Q800_NUBUS_SLOTS_AVAILABLE
);
568 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
569 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0,
570 MAC_NUBUS_FIRST_SLOT
* NUBUS_SUPER_SLOT_SIZE
);
571 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 1, NUBUS_SLOT_BASE
+
572 MAC_NUBUS_FIRST_SLOT
* NUBUS_SLOT_SIZE
);
573 qdev_connect_gpio_out(dev
, 9,
574 qdev_get_gpio_in_named(via2_dev
, "nubus-irq",
575 VIA2_NUBUS_IRQ_INTVIDEO
));
576 for (i
= 1; i
< VIA2_NUBUS_IRQ_NB
; i
++) {
577 qdev_connect_gpio_out(dev
, 9 + i
,
578 qdev_get_gpio_in_named(via2_dev
, "nubus-irq",
579 VIA2_NUBUS_IRQ_9
+ i
));
583 * Since the framebuffer in slot 0x9 uses a separate IRQ, wire the unused
584 * IRQ via GLUE for use by SONIC Ethernet in classic mode
586 qdev_connect_gpio_out(glue
, GLUE_IRQ_NUBUS_9
,
587 qdev_get_gpio_in_named(via2_dev
, "nubus-irq",
590 nubus
= &NUBUS_BRIDGE(dev
)->bus
;
592 /* framebuffer in nubus slot #9 */
594 dev
= qdev_new(TYPE_NUBUS_MACFB
);
595 qdev_prop_set_uint32(dev
, "slot", 9);
596 qdev_prop_set_uint32(dev
, "width", graphic_width
);
597 qdev_prop_set_uint32(dev
, "height", graphic_height
);
598 qdev_prop_set_uint8(dev
, "depth", graphic_depth
);
599 if (graphic_width
== 1152 && graphic_height
== 870) {
600 qdev_prop_set_uint8(dev
, "display", MACFB_DISPLAY_APPLE_21_COLOR
);
602 qdev_prop_set_uint8(dev
, "display", MACFB_DISPLAY_VGA
);
604 qdev_realize_and_unref(dev
, BUS(nubus
), &error_fatal
);
606 macfb_mode
= (NUBUS_MACFB(dev
)->macfb
).mode
;
611 void *param_blob
, *param_ptr
, *param_rng_seed
;
613 if (kernel_cmdline
) {
614 param_blob
= g_malloc(strlen(kernel_cmdline
) + 1024);
616 param_blob
= g_malloc(1024);
619 kernel_size
= load_elf(kernel_filename
, NULL
, NULL
, NULL
,
620 &elf_entry
, NULL
, &high
, NULL
, 1,
622 if (kernel_size
< 0) {
623 error_report("could not load kernel '%s'", kernel_filename
);
626 stl_phys(cs
->as
, 4, elf_entry
); /* reset initial PC */
627 parameters_base
= (high
+ 1) & ~1;
628 param_ptr
= param_blob
;
630 BOOTINFO1(param_ptr
, BI_MACHTYPE
, MACH_MAC
);
631 BOOTINFO1(param_ptr
, BI_FPUTYPE
, FPU_68040
);
632 BOOTINFO1(param_ptr
, BI_MMUTYPE
, MMU_68040
);
633 BOOTINFO1(param_ptr
, BI_CPUTYPE
, CPU_68040
);
634 BOOTINFO1(param_ptr
, BI_MAC_CPUID
, CPUB_68040
);
635 BOOTINFO1(param_ptr
, BI_MAC_MODEL
, MAC_MODEL_Q800
);
637 BI_MAC_MEMSIZE
, ram_size
>> 20); /* in MB */
638 BOOTINFO2(param_ptr
, BI_MEMCHUNK
, 0, ram_size
);
639 BOOTINFO1(param_ptr
, BI_MAC_VADDR
,
640 VIDEO_BASE
+ macfb_mode
->offset
);
641 BOOTINFO1(param_ptr
, BI_MAC_VDEPTH
, graphic_depth
);
642 BOOTINFO1(param_ptr
, BI_MAC_VDIM
,
643 (graphic_height
<< 16) | graphic_width
);
644 BOOTINFO1(param_ptr
, BI_MAC_VROW
, macfb_mode
->stride
);
645 BOOTINFO1(param_ptr
, BI_MAC_SCCBASE
, SCC_BASE
);
647 rom
= g_malloc(sizeof(*rom
));
648 memory_region_init_ram_ptr(rom
, NULL
, "m68k_fake_mac.rom",
649 sizeof(fake_mac_rom
), fake_mac_rom
);
650 memory_region_set_readonly(rom
, true);
651 memory_region_add_subregion(get_system_memory(), MACROM_ADDR
, rom
);
653 if (kernel_cmdline
) {
654 BOOTINFOSTR(param_ptr
, BI_COMMAND_LINE
,
658 /* Pass seed to RNG. */
659 param_rng_seed
= param_ptr
;
660 qemu_guest_getrandom_nofail(rng_seed
, sizeof(rng_seed
));
661 BOOTINFODATA(param_ptr
, BI_RNG_SEED
,
662 rng_seed
, sizeof(rng_seed
));
665 if (initrd_filename
) {
666 initrd_size
= get_image_size(initrd_filename
);
667 if (initrd_size
< 0) {
668 error_report("could not load initial ram disk '%s'",
673 initrd_base
= (ram_size
- initrd_size
) & TARGET_PAGE_MASK
;
674 load_image_targphys(initrd_filename
, initrd_base
,
675 ram_size
- initrd_base
);
676 BOOTINFO2(param_ptr
, BI_RAMDISK
, initrd_base
,
682 BOOTINFO0(param_ptr
, BI_LAST
);
683 rom_add_blob_fixed_as("bootinfo", param_blob
, param_ptr
- param_blob
,
684 parameters_base
, cs
->as
);
685 qemu_register_reset_nosnapshotload(rerandomize_rng_seed
,
686 rom_ptr_for_as(cs
->as
, parameters_base
,
687 param_ptr
- param_blob
) +
688 (param_rng_seed
- param_blob
));
692 /* allocate and load BIOS */
693 rom
= g_malloc(sizeof(*rom
));
694 memory_region_init_rom(rom
, NULL
, "m68k_mac.rom", MACROM_SIZE
,
696 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
697 memory_region_add_subregion(get_system_memory(), MACROM_ADDR
, rom
);
699 /* Load MacROM binary */
701 bios_size
= load_image_targphys(filename
, MACROM_ADDR
, MACROM_SIZE
);
707 /* Remove qtest_enabled() check once firmware files are in the tree */
708 if (!qtest_enabled()) {
709 if (bios_size
<= 0 || bios_size
> MACROM_SIZE
) {
710 error_report("could not load MacROM '%s'", bios_name
);
714 ptr
= rom_ptr(MACROM_ADDR
, bios_size
);
716 stl_phys(cs
->as
, 0, ldl_p(ptr
)); /* reset initial SP */
718 MACROM_ADDR
+ ldl_p(ptr
+ 4)); /* reset initial PC */
723 static GlobalProperty hw_compat_q800
[] = {
724 { "scsi-hd", "quirk_mode_page_vendor_specific_apple", "on" },
725 { "scsi-hd", "vendor", " SEAGATE" },
726 { "scsi-hd", "product", " ST225N" },
727 { "scsi-hd", "ver", "1.0 " },
728 { "scsi-cd", "quirk_mode_page_apple_vendor", "on" },
729 { "scsi-cd", "quirk_mode_sense_rom_use_dbd", "on" },
730 { "scsi-cd", "quirk_mode_page_vendor_specific_apple", "on" },
731 { "scsi-cd", "quirk_mode_page_truncated", "on" },
732 { "scsi-cd", "vendor", "MATSHITA" },
733 { "scsi-cd", "product", "CD-ROM CR-8005" },
734 { "scsi-cd", "ver", "1.0k" },
736 static const size_t hw_compat_q800_len
= G_N_ELEMENTS(hw_compat_q800
);
738 static void q800_machine_class_init(ObjectClass
*oc
, void *data
)
740 MachineClass
*mc
= MACHINE_CLASS(oc
);
741 mc
->desc
= "Macintosh Quadra 800";
742 mc
->init
= q800_init
;
743 mc
->default_cpu_type
= M68K_CPU_TYPE_NAME("m68040");
745 mc
->block_default_type
= IF_SCSI
;
746 mc
->default_ram_id
= "m68k_mac.ram";
747 compat_props_add(mc
->compat_props
, hw_compat_q800
, hw_compat_q800_len
);
750 static const TypeInfo q800_machine_typeinfo
= {
751 .name
= MACHINE_TYPE_NAME("q800"),
752 .parent
= TYPE_MACHINE
,
753 .instance_size
= sizeof(Q800MachineState
),
754 .class_init
= q800_machine_class_init
,
757 static void q800_machine_register_types(void)
759 type_register_static(&q800_machine_typeinfo
);
760 type_register_static(&glue_info
);
763 type_init(q800_machine_register_types
)