hw/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "qemu-timer.h"
  26 #include "sysemu.h"
  27 #include "pc.h"
  28 #include "apic.h"
  29 #include "isa.h"
  30 #include "hpet_emul.h"
  31 #include "mc146818rtc.h"
  32
  33 //#define DEBUG_CMOS
  34
  35 #define RTC_REINJECT_ON_ACK_COUNT 20
  36
  37 #define RTC_SECONDS             0
  38 #define RTC_SECONDS_ALARM       1
  39 #define RTC_MINUTES             2
  40 #define RTC_MINUTES_ALARM       3
  41 #define RTC_HOURS               4
  42 #define RTC_HOURS_ALARM         5
  43 #define RTC_ALARM_DONT_CARE    0xC0
  44
  45 #define RTC_DAY_OF_WEEK         6
  46 #define RTC_DAY_OF_MONTH        7
  47 #define RTC_MONTH               8
  48 #define RTC_YEAR                9
  49
  50 #define RTC_REG_A               10
  51 #define RTC_REG_B               11
  52 #define RTC_REG_C               12
  53 #define RTC_REG_D               13
  54
  55 #define REG_A_UIP 0x80
  56
  57 #define REG_B_SET  0x80
  58 #define REG_B_PIE  0x40
  59 #define REG_B_AIE  0x20
  60 #define REG_B_UIE  0x10
  61 #define REG_B_SQWE 0x08
  62 #define REG_B_DM   0x04
  63
  64 #define REG_C_UF   0x10
  65 #define REG_C_IRQF 0x80
  66 #define REG_C_PF   0x40
  67 #define REG_C_AF   0x20
  68
  69 typedef struct RTCState {
  70     ISADevice dev;
  71     uint8_t cmos_data[128];
  72     uint8_t cmos_index;
  73     struct tm current_tm;
  74     int32_t base_year;
  75     qemu_irq irq;
  76     qemu_irq sqw_irq;
  77     int it_shift;
  78     /* periodic timer */
  79     QEMUTimer *periodic_timer;
  80     int64_t next_periodic_time;
  81     /* second update */
  82     int64_t next_second_time;
  83     uint16_t irq_reinject_on_ack_count;
  84     uint32_t irq_coalesced;
  85     uint32_t period;
  86     QEMUTimer *coalesced_timer;
  87     QEMUTimer *second_timer;
  88     QEMUTimer *second_timer2;
  89 } RTCState;
  90
  91 static void rtc_irq_raise(qemu_irq irq)
  92 {
  93     /* When HPET is operating in legacy mode, RTC interrupts are disabled
  94      * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
  95      * mode is established while interrupt is raised. We want it to
  96      * be lowered in any case
  97      */
  98 #if defined TARGET_I386
  99     if (!hpet_in_legacy_mode())
 100 #endif
 101         qemu_irq_raise(irq);
 102 }
 103
 104 static void rtc_set_time(RTCState *s);
 105 static void rtc_copy_date(RTCState *s);
 106
 107 #ifdef TARGET_I386
 108 static void rtc_coalesced_timer_update(RTCState *s)
 109 {
 110     if (s->irq_coalesced == 0) {
 111         qemu_del_timer(s->coalesced_timer);
 112     } else {
 113         /* divide each RTC interval to 2 - 8 smaller intervals */
 114         int c = MIN(s->irq_coalesced, 7) + 1;
 115         int64_t next_clock = qemu_get_clock(rtc_clock) +
 116             muldiv64(s->period / c, get_ticks_per_sec(), 32768);
 117         qemu_mod_timer(s->coalesced_timer, next_clock);
 118     }
 119 }
 120
 121 static void rtc_coalesced_timer(void *opaque)
 122 {
 123     RTCState *s = opaque;
 124
 125     if (s->irq_coalesced != 0) {
 126         apic_reset_irq_delivered();
 127         s->cmos_data[RTC_REG_C] |= 0xc0;
 128         rtc_irq_raise(s->irq);
 129         if (apic_get_irq_delivered()) {
 130             s->irq_coalesced--;
 131         }
 132     }
 133
 134     rtc_coalesced_timer_update(s);
 135 }
 136 #endif
 137
 138 static void rtc_timer_update(RTCState *s, int64_t current_time)
 139 {
 140     int period_code, period;
 141     int64_t cur_clock, next_irq_clock;
 142     int enable_pie;
 143
 144     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 145 #if defined TARGET_I386
 146     /* disable periodic timer if hpet is in legacy mode, since interrupts are
 147      * disabled anyway.
 148      */
 149     enable_pie = !hpet_in_legacy_mode();
 150 #else
 151     enable_pie = 1;
 152 #endif
 153     if (period_code != 0
 154         && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie)
 155             || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
 156         if (period_code <= 2)
 157             period_code += 7;
 158         /* period in 32 Khz cycles */
 159         period = 1 << (period_code - 1);
 160 #ifdef TARGET_I386
 161         if(period != s->period)
 162             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 163         s->period = period;
 164 #endif
 165         /* compute 32 khz clock */
 166         cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
 167         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 168         s->next_periodic_time =
 169             muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1;
 170         qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
 171     } else {
 172 #ifdef TARGET_I386
 173         s->irq_coalesced = 0;
 174 #endif
 175         qemu_del_timer(s->periodic_timer);
 176     }
 177 }
 178
 179 static void rtc_periodic_timer(void *opaque)
 180 {
 181     RTCState *s = opaque;
 182
 183     rtc_timer_update(s, s->next_periodic_time);
 184     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 185         s->cmos_data[RTC_REG_C] |= 0xc0;
 186 #ifdef TARGET_I386
 187         if(rtc_td_hack) {
 188             if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT)
 189                 s->irq_reinject_on_ack_count = 0;
 190             apic_reset_irq_delivered();
 191             rtc_irq_raise(s->irq);
 192             if (!apic_get_irq_delivered()) {
 193                 s->irq_coalesced++;
 194                 rtc_coalesced_timer_update(s);
 195             }
 196         } else
 197 #endif
 198         rtc_irq_raise(s->irq);
 199     }
 200     if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
 201         /* Not square wave at all but we don't want 2048Hz interrupts!
 202            Must be seen as a pulse.  */
 203         qemu_irq_raise(s->sqw_irq);
 204     }
 205 }
 206
 207 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
 208 {
 209     RTCState *s = opaque;
 210
 211     if ((addr & 1) == 0) {
 212         s->cmos_index = data & 0x7f;
 213     } else {
 214 #ifdef DEBUG_CMOS
 215         printf("cmos: write index=0x%02x val=0x%02x\n",
 216                s->cmos_index, data);
 217 #endif
 218         switch(s->cmos_index) {
 219         case RTC_SECONDS_ALARM:
 220         case RTC_MINUTES_ALARM:
 221         case RTC_HOURS_ALARM:
 222             /* XXX: not supported */
 223             s->cmos_data[s->cmos_index] = data;
 224             break;
 225         case RTC_SECONDS:
 226         case RTC_MINUTES:
 227         case RTC_HOURS:
 228         case RTC_DAY_OF_WEEK:
 229         case RTC_DAY_OF_MONTH:
 230         case RTC_MONTH:
 231         case RTC_YEAR:
 232             s->cmos_data[s->cmos_index] = data;
 233             /* if in set mode, do not update the time */
 234             if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 235                 rtc_set_time(s);
 236             }
 237             break;
 238         case RTC_REG_A:
 239             /* UIP bit is read only */
 240             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 241                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 242             rtc_timer_update(s, qemu_get_clock(rtc_clock));
 243             break;
 244         case RTC_REG_B:
 245             if (data & REG_B_SET) {
 246                 /* set mode: reset UIP mode */
 247                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 248                 data &= ~REG_B_UIE;
 249             } else {
 250                 /* if disabling set mode, update the time */
 251                 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
 252                     rtc_set_time(s);
 253                 }
 254             }
 255             s->cmos_data[RTC_REG_B] = data;
 256             rtc_timer_update(s, qemu_get_clock(rtc_clock));
 257             break;
 258         case RTC_REG_C:
 259         case RTC_REG_D:
 260             /* cannot write to them */
 261             break;
 262         default:
 263             s->cmos_data[s->cmos_index] = data;
 264             break;
 265         }
 266     }
 267 }
 268
 269 static inline int rtc_to_bcd(RTCState *s, int a)
 270 {
 271     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 272         return a;
 273     } else {
 274         return ((a / 10) << 4) | (a % 10);
 275     }
 276 }
 277
 278 static inline int rtc_from_bcd(RTCState *s, int a)
 279 {
 280     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 281         return a;
 282     } else {
 283         return ((a >> 4) * 10) + (a & 0x0f);
 284     }
 285 }
 286
 287 static void rtc_set_time(RTCState *s)
 288 {
 289     struct tm *tm = &s->current_tm;
 290
 291     tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]);
 292     tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]);
 293     tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 294     if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
 295         (s->cmos_data[RTC_HOURS] & 0x80)) {
 296         tm->tm_hour += 12;
 297     }
 298     tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 299     tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 300     tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 301     tm->tm_year = rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
 302
 303     rtc_change_mon_event(tm);
 304 }
 305
 306 static void rtc_copy_date(RTCState *s)
 307 {
 308     const struct tm *tm = &s->current_tm;
 309     int year;
 310
 311     s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec);
 312     s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min);
 313     if (s->cmos_data[RTC_REG_B] & 0x02) {
 314         /* 24 hour format */
 315         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour);
 316     } else {
 317         /* 12 hour format */
 318         s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour % 12);
 319         if (tm->tm_hour >= 12)
 320             s->cmos_data[RTC_HOURS] |= 0x80;
 321     }
 322     s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1);
 323     s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday);
 324     s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1);
 325     year = (tm->tm_year - s->base_year) % 100;
 326     if (year < 0)
 327         year += 100;
 328     s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year);
 329 }
 330
 331 /* month is between 0 and 11. */
 332 static int get_days_in_month(int month, int year)
 333 {
 334     static const int days_tab[12] = {
 335         31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
 336     };
 337     int d;
 338     if ((unsigned )month >= 12)
 339         return 31;
 340     d = days_tab[month];
 341     if (month == 1) {
 342         if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
 343             d++;
 344     }
 345     return d;
 346 }
 347
 348 /* update 'tm' to the next second */
 349 static void rtc_next_second(struct tm *tm)
 350 {
 351     int days_in_month;
 352
 353     tm->tm_sec++;
 354     if ((unsigned)tm->tm_sec >= 60) {
 355         tm->tm_sec = 0;
 356         tm->tm_min++;
 357         if ((unsigned)tm->tm_min >= 60) {
 358             tm->tm_min = 0;
 359             tm->tm_hour++;
 360             if ((unsigned)tm->tm_hour >= 24) {
 361                 tm->tm_hour = 0;
 362                 /* next day */
 363                 tm->tm_wday++;
 364                 if ((unsigned)tm->tm_wday >= 7)
 365                     tm->tm_wday = 0;
 366                 days_in_month = get_days_in_month(tm->tm_mon,
 367                                                   tm->tm_year + 1900);
 368                 tm->tm_mday++;
 369                 if (tm->tm_mday < 1) {
 370                     tm->tm_mday = 1;
 371                 } else if (tm->tm_mday > days_in_month) {
 372                     tm->tm_mday = 1;
 373                     tm->tm_mon++;
 374                     if (tm->tm_mon >= 12) {
 375                         tm->tm_mon = 0;
 376                         tm->tm_year++;
 377                     }
 378                 }
 379             }
 380         }
 381     }
 382 }
 383
 384
 385 static void rtc_update_second(void *opaque)
 386 {
 387     RTCState *s = opaque;
 388     int64_t delay;
 389
 390     /* if the oscillator is not in normal operation, we do not update */
 391     if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
 392         s->next_second_time += get_ticks_per_sec();
 393         qemu_mod_timer(s->second_timer, s->next_second_time);
 394     } else {
 395         rtc_next_second(&s->current_tm);
 396
 397         if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 398             /* update in progress bit */
 399             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 400         }
 401         /* should be 244 us = 8 / 32768 seconds, but currently the
 402            timers do not have the necessary resolution. */
 403         delay = (get_ticks_per_sec() * 1) / 100;
 404         if (delay < 1)
 405             delay = 1;
 406         qemu_mod_timer(s->second_timer2,
 407                        s->next_second_time + delay);
 408     }
 409 }
 410
 411 static void rtc_update_second2(void *opaque)
 412 {
 413     RTCState *s = opaque;
 414
 415     if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 416         rtc_copy_date(s);
 417     }
 418
 419     /* check alarm */
 420     if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 421         if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
 422              s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
 423             ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
 424              s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
 425             ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
 426              s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
 427
 428             s->cmos_data[RTC_REG_C] |= 0xa0;
 429             rtc_irq_raise(s->irq);
 430         }
 431     }
 432
 433     /* update ended interrupt */
 434     s->cmos_data[RTC_REG_C] |= REG_C_UF;
 435     if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
 436       s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 437       rtc_irq_raise(s->irq);
 438     }
 439
 440     /* clear update in progress bit */
 441     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 442
 443     s->next_second_time += get_ticks_per_sec();
 444     qemu_mod_timer(s->second_timer, s->next_second_time);
 445 }
 446
 447 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
 448 {
 449     RTCState *s = opaque;
 450     int ret;
 451     if ((addr & 1) == 0) {
 452         return 0xff;
 453     } else {
 454         switch(s->cmos_index) {
 455         case RTC_SECONDS:
 456         case RTC_MINUTES:
 457         case RTC_HOURS:
 458         case RTC_DAY_OF_WEEK:
 459         case RTC_DAY_OF_MONTH:
 460         case RTC_MONTH:
 461         case RTC_YEAR:
 462             ret = s->cmos_data[s->cmos_index];
 463             break;
 464         case RTC_REG_A:
 465             ret = s->cmos_data[s->cmos_index];
 466             break;
 467         case RTC_REG_C:
 468             ret = s->cmos_data[s->cmos_index];
 469             qemu_irq_lower(s->irq);
 470 #ifdef TARGET_I386
 471             if(s->irq_coalesced &&
 472                     s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) {
 473                 s->irq_reinject_on_ack_count++;
 474                 apic_reset_irq_delivered();
 475                 qemu_irq_raise(s->irq);
 476                 if (apic_get_irq_delivered())
 477                     s->irq_coalesced--;
 478                 break;
 479             }
 480 #endif
 481
 482             s->cmos_data[RTC_REG_C] = 0x00;
 483             break;
 484         default:
 485             ret = s->cmos_data[s->cmos_index];
 486             break;
 487         }
 488 #ifdef DEBUG_CMOS
 489         printf("cmos: read index=0x%02x val=0x%02x\n",
 490                s->cmos_index, ret);
 491 #endif
 492         return ret;
 493     }
 494 }
 495
 496 void rtc_set_memory(ISADevice *dev, int addr, int val)
 497 {
 498     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 499     if (addr >= 0 && addr <= 127)
 500         s->cmos_data[addr] = val;
 501 }
 502
 503 void rtc_set_date(ISADevice *dev, const struct tm *tm)
 504 {
 505     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 506     s->current_tm = *tm;
 507     rtc_copy_date(s);
 508 }
 509
 510 /* PC cmos mappings */
 511 #define REG_IBM_CENTURY_BYTE        0x32
 512 #define REG_IBM_PS2_CENTURY_BYTE    0x37
 513
 514 static void rtc_set_date_from_host(ISADevice *dev)
 515 {
 516     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 517     struct tm tm;
 518     int val;
 519
 520     /* set the CMOS date */
 521     qemu_get_timedate(&tm, 0);
 522     rtc_set_date(dev, &tm);
 523
 524     val = rtc_to_bcd(s, (tm.tm_year / 100) + 19);
 525     rtc_set_memory(dev, REG_IBM_CENTURY_BYTE, val);
 526     rtc_set_memory(dev, REG_IBM_PS2_CENTURY_BYTE, val);
 527 }
 528
 529 static int rtc_post_load(void *opaque, int version_id)
 530 {
 531 #ifdef TARGET_I386
 532     RTCState *s = opaque;
 533
 534     if (version_id >= 2) {
 535         if (rtc_td_hack) {
 536             rtc_coalesced_timer_update(s);
 537         }
 538     }
 539 #endif
 540     return 0;
 541 }
 542
 543 static const VMStateDescription vmstate_rtc = {
 544     .name = "mc146818rtc",
 545     .version_id = 2,
 546     .minimum_version_id = 1,
 547     .minimum_version_id_old = 1,
 548     .post_load = rtc_post_load,
 549     .fields      = (VMStateField []) {
 550         VMSTATE_BUFFER(cmos_data, RTCState),
 551         VMSTATE_UINT8(cmos_index, RTCState),
 552         VMSTATE_INT32(current_tm.tm_sec, RTCState),
 553         VMSTATE_INT32(current_tm.tm_min, RTCState),
 554         VMSTATE_INT32(current_tm.tm_hour, RTCState),
 555         VMSTATE_INT32(current_tm.tm_wday, RTCState),
 556         VMSTATE_INT32(current_tm.tm_mday, RTCState),
 557         VMSTATE_INT32(current_tm.tm_mon, RTCState),
 558         VMSTATE_INT32(current_tm.tm_year, RTCState),
 559         VMSTATE_TIMER(periodic_timer, RTCState),
 560         VMSTATE_INT64(next_periodic_time, RTCState),
 561         VMSTATE_INT64(next_second_time, RTCState),
 562         VMSTATE_TIMER(second_timer, RTCState),
 563         VMSTATE_TIMER(second_timer2, RTCState),
 564         VMSTATE_UINT32_V(irq_coalesced, RTCState, 2),
 565         VMSTATE_UINT32_V(period, RTCState, 2),
 566         VMSTATE_END_OF_LIST()
 567     }
 568 };
 569
 570 static void rtc_reset(void *opaque)
 571 {
 572     RTCState *s = opaque;
 573
 574     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 575     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 576
 577     qemu_irq_lower(s->irq);
 578
 579 #ifdef TARGET_I386
 580     if (rtc_td_hack)
 581             s->irq_coalesced = 0;
 582 #endif
 583 }
 584
 585 static int rtc_initfn(ISADevice *dev)
 586 {
 587     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 588     int base = 0x70;
 589     int isairq = 8;
 590
 591     isa_init_irq(dev, &s->irq, isairq);
 592
 593     s->cmos_data[RTC_REG_A] = 0x26;
 594     s->cmos_data[RTC_REG_B] = 0x02;
 595     s->cmos_data[RTC_REG_C] = 0x00;
 596     s->cmos_data[RTC_REG_D] = 0x80;
 597
 598     rtc_set_date_from_host(dev);
 599
 600     s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s);
 601 #ifdef TARGET_I386
 602     if (rtc_td_hack)
 603         s->coalesced_timer =
 604             qemu_new_timer(rtc_clock, rtc_coalesced_timer, s);
 605 #endif
 606     s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s);
 607     s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s);
 608
 609     s->next_second_time =
 610         qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
 611     qemu_mod_timer(s->second_timer2, s->next_second_time);
 612
 613     register_ioport_write(base, 2, 1, cmos_ioport_write, s);
 614     register_ioport_read(base, 2, 1, cmos_ioport_read, s);
 615
 616     qdev_set_legacy_instance_id(&dev->qdev, base, 2);
 617     qemu_register_reset(rtc_reset, s);
 618     return 0;
 619 }
 620
 621 ISADevice *rtc_init(int base_year)
 622 {
 623     ISADevice *dev;
 624
 625     dev = isa_create("mc146818rtc");
 626     qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
 627     qdev_init_nofail(&dev->qdev);
 628     return dev;
 629 }
 630
 631 static ISADeviceInfo mc146818rtc_info = {
 632     .qdev.name     = "mc146818rtc",
 633     .qdev.size     = sizeof(RTCState),
 634     .qdev.no_user  = 1,
 635     .qdev.vmsd     = &vmstate_rtc,
 636     .init          = rtc_initfn,
 637     .qdev.props    = (Property[]) {
 638         DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 639         DEFINE_PROP_END_OF_LIST(),
 640     }
 641 };
 642
 643 static void mc146818rtc_register(void)
 644 {
 645     isa_qdev_register(&mc146818rtc_info);
 646 }
 647 device_init(mc146818rtc_register)