hw/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 //#define DEBUG_CMOS
  27
  28 #define RTC_SECONDS             0
  29 #define RTC_SECONDS_ALARM       1
  30 #define RTC_MINUTES             2
  31 #define RTC_MINUTES_ALARM       3
  32 #define RTC_HOURS               4
  33 #define RTC_HOURS_ALARM         5
  34 #define RTC_ALARM_DONT_CARE    0xC0
  35
  36 #define RTC_DAY_OF_WEEK         6
  37 #define RTC_DAY_OF_MONTH        7
  38 #define RTC_MONTH               8
  39 #define RTC_YEAR                9
  40
  41 #define RTC_REG_A               10
  42 #define RTC_REG_B               11
  43 #define RTC_REG_C               12
  44 #define RTC_REG_D               13
  45
  46 #define REG_A_UIP 0x80
  47
  48 #define REG_B_SET 0x80
  49 #define REG_B_PIE 0x40
  50 #define REG_B_AIE 0x20
  51 #define REG_B_UIE 0x10
  52
  53 struct RTCState {
  54     uint8_t cmos_data[128];
  55     uint8_t cmos_index;
  56     int current_time; /* in seconds */
  57     int irq;
  58     uint8_t buf_data[10]; /* buffered data */
  59     /* periodic timer */
  60     QEMUTimer *periodic_timer;
  61     int64_t next_periodic_time;
  62     /* second update */
  63     int64_t next_second_time;
  64     QEMUTimer *second_timer;
  65     QEMUTimer *second_timer2;
  66 };
  67
  68 static void rtc_set_time(RTCState *s);
  69 static void rtc_set_date_buf(RTCState *s, const struct tm *tm);
  70 static void rtc_copy_date(RTCState *s);
  71
  72 static void rtc_timer_update(RTCState *s, int64_t current_time)
  73 {
  74     int period_code, period;
  75     int64_t cur_clock, next_irq_clock;
  76
  77     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
  78     if (period_code != 0 &&
  79         (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
  80         if (period_code <= 2)
  81             period_code += 7;
  82         /* period in 32 Khz cycles */
  83         period = 1 << (period_code - 1);
  84         /* compute 32 khz clock */
  85         cur_clock = muldiv64(current_time, 32768, ticks_per_sec);
  86         next_irq_clock = (cur_clock & ~(period - 1)) + period;
  87         s->next_periodic_time = muldiv64(next_irq_clock, ticks_per_sec, 32768) + 1;
  88         qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
  89     } else {
  90         qemu_del_timer(s->periodic_timer);
  91     }
  92 }
  93
  94 static void rtc_periodic_timer(void *opaque)
  95 {
  96     RTCState *s = opaque;
  97
  98     rtc_timer_update(s, s->next_periodic_time);
  99     s->cmos_data[RTC_REG_C] |= 0xc0;
 100     pic_set_irq(s->irq, 1);
 101 }
 102
 103 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
 104 {
 105     RTCState *s = opaque;
 106
 107     if ((addr & 1) == 0) {
 108         s->cmos_index = data & 0x7f;
 109     } else {
 110 #ifdef DEBUG_CMOS
 111         printf("cmos: write index=0x%02x val=0x%02x\n",
 112                s->cmos_index, data);
 113 #endif
 114         switch(s->cmos_index) {
 115         case RTC_SECONDS_ALARM:
 116         case RTC_MINUTES_ALARM:
 117         case RTC_HOURS_ALARM:
 118             /* XXX: not supported */
 119             s->cmos_data[s->cmos_index] = data;
 120             break;
 121         case RTC_SECONDS:
 122         case RTC_MINUTES:
 123         case RTC_HOURS:
 124         case RTC_DAY_OF_WEEK:
 125         case RTC_DAY_OF_MONTH:
 126         case RTC_MONTH:
 127         case RTC_YEAR:
 128             s->cmos_data[s->cmos_index] = data;
 129             /* if in set mode, do not update the time */
 130             if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 131                 rtc_set_time(s);
 132             }
 133             break;
 134         case RTC_REG_A:
 135             /* UIP bit is read only */
 136             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 137                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 138             rtc_timer_update(s, qemu_get_clock(vm_clock));
 139             break;
 140         case RTC_REG_B:
 141             if (data & REG_B_SET) {
 142                 /* set mode: reset UIP mode */
 143                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 144                 data &= ~REG_B_UIE;
 145             } else {
 146                 /* if disabling set mode, update the time */
 147                 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
 148                     rtc_set_time(s);
 149                 }
 150             }
 151             s->cmos_data[RTC_REG_B] = data;
 152             rtc_timer_update(s, qemu_get_clock(vm_clock));
 153             break;
 154         case RTC_REG_C:
 155         case RTC_REG_D:
 156             /* cannot write to them */
 157             break;
 158         default:
 159             s->cmos_data[s->cmos_index] = data;
 160             break;
 161         }
 162     }
 163 }
 164
 165 static inline int to_bcd(RTCState *s, int a)
 166 {
 167     if (s->cmos_data[RTC_REG_B] & 0x04) {
 168         return a;
 169     } else {
 170         return ((a / 10) << 4) | (a % 10);
 171     }
 172 }
 173
 174 static inline int from_bcd(RTCState *s, int a)
 175 {
 176     if (s->cmos_data[RTC_REG_B] & 0x04) {
 177         return a;
 178     } else {
 179         return ((a >> 4) * 10) + (a & 0x0f);
 180     }
 181 }
 182
 183 static void rtc_set_time(RTCState *s)
 184 {
 185     struct tm tm1, *tm = &tm1;
 186
 187     tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
 188     tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
 189     tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS]);
 190     tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]);
 191     tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 192     tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 193     tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + 100;
 194
 195     /* update internal state */
 196     s->buf_data[RTC_SECONDS] = s->cmos_data[RTC_SECONDS];
 197     s->buf_data[RTC_MINUTES] = s->cmos_data[RTC_MINUTES];
 198     s->buf_data[RTC_HOURS] = s->cmos_data[RTC_HOURS];
 199     s->buf_data[RTC_DAY_OF_WEEK] = s->cmos_data[RTC_DAY_OF_WEEK];
 200     s->buf_data[RTC_DAY_OF_MONTH] = s->cmos_data[RTC_DAY_OF_MONTH];
 201     s->buf_data[RTC_MONTH] = s->cmos_data[RTC_MONTH];
 202     s->buf_data[RTC_YEAR] = s->cmos_data[RTC_YEAR];
 203     s->current_time = mktime(tm);
 204 }
 205
 206 static void rtc_update_second(void *opaque)
 207 {
 208     RTCState *s = opaque;
 209
 210     /* if the oscillator is not in normal operation, we do not update */
 211     if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
 212         s->next_second_time += ticks_per_sec;
 213         qemu_mod_timer(s->second_timer, s->next_second_time);
 214     } else {
 215         s->current_time++;
 216
 217         if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 218             /* update in progress bit */
 219             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 220         }
 221         qemu_mod_timer(s->second_timer2,
 222                        s->next_second_time + (ticks_per_sec * 99) / 100);
 223     }
 224 }
 225
 226 static void rtc_update_second2(void *opaque)
 227 {
 228     RTCState *s = opaque;
 229     time_t ti;
 230
 231     ti = s->current_time;
 232     rtc_set_date_buf(s, gmtime(&ti));
 233
 234     if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 235         rtc_copy_date(s);
 236     }
 237
 238     /* check alarm */
 239     if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 240         if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
 241              s->cmos_data[RTC_SECONDS_ALARM] == s->buf_data[RTC_SECONDS]) &&
 242             ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
 243              s->cmos_data[RTC_MINUTES_ALARM] == s->buf_data[RTC_MINUTES]) &&
 244             ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
 245              s->cmos_data[RTC_HOURS_ALARM] == s->buf_data[RTC_HOURS])) {
 246
 247             s->cmos_data[RTC_REG_C] |= 0xa0;
 248             pic_set_irq(s->irq, 1);
 249         }
 250     }
 251
 252     /* update ended interrupt */
 253     if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
 254         s->cmos_data[RTC_REG_C] |= 0x90;
 255         pic_set_irq(s->irq, 1);
 256     }
 257
 258     /* clear update in progress bit */
 259     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 260
 261     s->next_second_time += ticks_per_sec;
 262     qemu_mod_timer(s->second_timer, s->next_second_time);
 263 }
 264
 265 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
 266 {
 267     RTCState *s = opaque;
 268     int ret;
 269     if ((addr & 1) == 0) {
 270         return 0xff;
 271     } else {
 272         switch(s->cmos_index) {
 273         case RTC_SECONDS:
 274         case RTC_MINUTES:
 275         case RTC_HOURS:
 276         case RTC_DAY_OF_WEEK:
 277         case RTC_DAY_OF_MONTH:
 278         case RTC_MONTH:
 279         case RTC_YEAR:
 280             ret = s->cmos_data[s->cmos_index];
 281             break;
 282         case RTC_REG_A:
 283             ret = s->cmos_data[s->cmos_index];
 284             break;
 285         case RTC_REG_C:
 286             ret = s->cmos_data[s->cmos_index];
 287             pic_set_irq(s->irq, 0);
 288             s->cmos_data[RTC_REG_C] = 0x00;
 289             break;
 290         default:
 291             ret = s->cmos_data[s->cmos_index];
 292             break;
 293         }
 294 #ifdef DEBUG_CMOS
 295         printf("cmos: read index=0x%02x val=0x%02x\n",
 296                s->cmos_index, ret);
 297 #endif
 298         return ret;
 299     }
 300 }
 301
 302 static void rtc_set_date_buf(RTCState *s, const struct tm *tm)
 303 {
 304     s->buf_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
 305     s->buf_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
 306     if (s->cmos_data[RTC_REG_B] & 0x02) {
 307         /* 24 hour format */
 308         s->buf_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
 309     } else {
 310         /* 12 hour format */
 311         s->buf_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
 312         if (tm->tm_hour >= 12)
 313             s->buf_data[RTC_HOURS] |= 0x80;
 314     }
 315     s->buf_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday);
 316     s->buf_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
 317     s->buf_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
 318     s->buf_data[RTC_YEAR] = to_bcd(s, tm->tm_year % 100);
 319 }
 320
 321 static void rtc_copy_date(RTCState *s)
 322 {
 323     s->cmos_data[RTC_SECONDS] = s->buf_data[RTC_SECONDS];
 324     s->cmos_data[RTC_MINUTES] = s->buf_data[RTC_MINUTES];
 325     s->cmos_data[RTC_HOURS] = s->buf_data[RTC_HOURS];
 326     s->cmos_data[RTC_DAY_OF_WEEK] = s->buf_data[RTC_DAY_OF_WEEK];
 327     s->cmos_data[RTC_DAY_OF_MONTH] = s->buf_data[RTC_DAY_OF_MONTH];
 328     s->cmos_data[RTC_MONTH] = s->buf_data[RTC_MONTH];
 329     s->cmos_data[RTC_YEAR] = s->buf_data[RTC_YEAR];
 330 }
 331
 332 void rtc_set_memory(RTCState *s, int addr, int val)
 333 {
 334     if (addr >= 0 && addr <= 127)
 335         s->cmos_data[addr] = val;
 336 }
 337
 338 void rtc_set_date(RTCState *s, const struct tm *tm)
 339 {
 340     s->current_time = mktime((struct tm *)tm);
 341     rtc_set_date_buf(s, tm);
 342     rtc_copy_date(s);
 343 }
 344
 345 static void rtc_save(QEMUFile *f, void *opaque)
 346 {
 347     RTCState *s = opaque;
 348
 349     qemu_put_buffer(f, s->cmos_data, 128);
 350     qemu_put_8s(f, &s->cmos_index);
 351     qemu_put_be32s(f, &s->current_time);
 352     qemu_put_buffer(f, s->buf_data, 10);
 353
 354     qemu_put_timer(f, s->periodic_timer);
 355     qemu_put_be64s(f, &s->next_periodic_time);
 356
 357     qemu_put_be64s(f, &s->next_second_time);
 358     qemu_put_timer(f, s->second_timer);
 359     qemu_put_timer(f, s->second_timer2);
 360 }
 361
 362 static int rtc_load(QEMUFile *f, void *opaque, int version_id)
 363 {
 364     RTCState *s = opaque;
 365
 366     if (version_id != 1)
 367         return -EINVAL;
 368
 369     qemu_get_buffer(f, s->cmos_data, 128);
 370     qemu_get_8s(f, &s->cmos_index);
 371     qemu_get_be32s(f, &s->current_time);
 372     qemu_get_buffer(f, s->buf_data, 10);
 373
 374     qemu_get_timer(f, s->periodic_timer);
 375     qemu_get_be64s(f, &s->next_periodic_time);
 376
 377     qemu_get_be64s(f, &s->next_second_time);
 378     qemu_get_timer(f, s->second_timer);
 379     qemu_get_timer(f, s->second_timer2);
 380     return 0;
 381 }
 382
 383 RTCState *rtc_init(int base, int irq)
 384 {
 385     RTCState *s;
 386
 387     s = qemu_mallocz(sizeof(RTCState));
 388     if (!s)
 389         return NULL;
 390
 391     s->irq = irq;
 392     s->cmos_data[RTC_REG_A] = 0x26;
 393     s->cmos_data[RTC_REG_B] = 0x02;
 394     s->cmos_data[RTC_REG_C] = 0x00;
 395     s->cmos_data[RTC_REG_D] = 0x80;
 396
 397     s->periodic_timer = qemu_new_timer(vm_clock,
 398                                        rtc_periodic_timer, s);
 399     s->second_timer = qemu_new_timer(vm_clock,
 400                                      rtc_update_second, s);
 401     s->second_timer2 = qemu_new_timer(vm_clock,
 402                                       rtc_update_second2, s);
 403
 404     s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
 405     qemu_mod_timer(s->second_timer2, s->next_second_time);
 406
 407     register_ioport_write(base, 2, 1, cmos_ioport_write, s);
 408     register_ioport_read(base, 2, 1, cmos_ioport_read, s);
 409
 410     register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
 411     return s;
 412 }
 413