hw/mc146818rtc.c

   1 /*
   2  * QEMU MC146818 RTC emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "qemu-timer.h"
  26 #include "sysemu.h"
  27 #include "pc.h"
  28 #include "isa.h"
  29 #include "hpet_emul.h"
  30
  31 //#define DEBUG_CMOS
  32
  33 #define RTC_SECONDS             0
  34 #define RTC_SECONDS_ALARM       1
  35 #define RTC_MINUTES             2
  36 #define RTC_MINUTES_ALARM       3
  37 #define RTC_HOURS               4
  38 #define RTC_HOURS_ALARM         5
  39 #define RTC_ALARM_DONT_CARE    0xC0
  40
  41 #define RTC_DAY_OF_WEEK         6
  42 #define RTC_DAY_OF_MONTH        7
  43 #define RTC_MONTH               8
  44 #define RTC_YEAR                9
  45
  46 #define RTC_REG_A               10
  47 #define RTC_REG_B               11
  48 #define RTC_REG_C               12
  49 #define RTC_REG_D               13
  50
  51 #define REG_A_UIP 0x80
  52
  53 #define REG_B_SET  0x80
  54 #define REG_B_PIE  0x40
  55 #define REG_B_AIE  0x20
  56 #define REG_B_UIE  0x10
  57 #define REG_B_SQWE 0x08
  58 #define REG_B_DM   0x04
  59
  60 #define REG_C_UF   0x10
  61 #define REG_C_IRQF 0x80
  62 #define REG_C_PF   0x40
  63 #define REG_C_AF   0x20
  64
  65 struct RTCState {
  66     ISADevice dev;
  67     uint8_t cmos_data[128];
  68     uint8_t cmos_index;
  69     struct tm current_tm;
  70     int32_t base_year;
  71     qemu_irq irq;
  72     qemu_irq sqw_irq;
  73     int it_shift;
  74     /* periodic timer */
  75     QEMUTimer *periodic_timer;
  76     int64_t next_periodic_time;
  77     /* second update */
  78     int64_t next_second_time;
  79 #ifdef TARGET_I386
  80     uint32_t irq_coalesced;
  81     uint32_t period;
  82     QEMUTimer *coalesced_timer;
  83 #endif
  84     QEMUTimer *second_timer;
  85     QEMUTimer *second_timer2;
  86 };
  87
  88 static void rtc_irq_raise(qemu_irq irq) {
  89     /* When HPET is operating in legacy mode, RTC interrupts are disabled
  90      * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
  91      * mode is established while interrupt is raised. We want it to
  92      * be lowered in any case
  93      */
  94 #if defined TARGET_I386
  95     if (!hpet_in_legacy_mode())
  96 #endif
  97         qemu_irq_raise(irq);
  98 }
  99
 100 static void rtc_set_time(RTCState *s);
 101 static void rtc_copy_date(RTCState *s);
 102
 103 #ifdef TARGET_I386
 104 static void rtc_coalesced_timer_update(RTCState *s)
 105 {
 106     if (s->irq_coalesced == 0) {
 107         qemu_del_timer(s->coalesced_timer);
 108     } else {
 109         /* divide each RTC interval to 2 - 8 smaller intervals */
 110         int c = MIN(s->irq_coalesced, 7) + 1;
 111         int64_t next_clock = qemu_get_clock(rtc_clock) +
 112             muldiv64(s->period / c, get_ticks_per_sec(), 32768);
 113         qemu_mod_timer(s->coalesced_timer, next_clock);
 114     }
 115 }
 116
 117 static void rtc_coalesced_timer(void *opaque)
 118 {
 119     RTCState *s = opaque;
 120
 121     if (s->irq_coalesced != 0) {
 122         apic_reset_irq_delivered();
 123         s->cmos_data[RTC_REG_C] |= 0xc0;
 124         rtc_irq_raise(s->irq);
 125         if (apic_get_irq_delivered()) {
 126             s->irq_coalesced--;
 127         }
 128     }
 129
 130     rtc_coalesced_timer_update(s);
 131 }
 132 #endif
 133
 134 static void rtc_timer_update(RTCState *s, int64_t current_time)
 135 {
 136     int period_code, period;
 137     int64_t cur_clock, next_irq_clock;
 138     int enable_pie;
 139
 140     period_code = s->cmos_data[RTC_REG_A] & 0x0f;
 141 #if defined TARGET_I386
 142     /* disable periodic timer if hpet is in legacy mode, since interrupts are
 143      * disabled anyway.
 144      */
 145     enable_pie = !hpet_in_legacy_mode();
 146 #else
 147     enable_pie = 1;
 148 #endif
 149     if (period_code != 0
 150         && (((s->cmos_data[RTC_REG_B] & REG_B_PIE) && enable_pie)
 151             || ((s->cmos_data[RTC_REG_B] & REG_B_SQWE) && s->sqw_irq))) {
 152         if (period_code <= 2)
 153             period_code += 7;
 154         /* period in 32 Khz cycles */
 155         period = 1 << (period_code - 1);
 156 #ifdef TARGET_I386
 157         if(period != s->period)
 158             s->irq_coalesced = (s->irq_coalesced * s->period) / period;
 159         s->period = period;
 160 #endif
 161         /* compute 32 khz clock */
 162         cur_clock = muldiv64(current_time, 32768, get_ticks_per_sec());
 163         next_irq_clock = (cur_clock & ~(period - 1)) + period;
 164         s->next_periodic_time =
 165             muldiv64(next_irq_clock, get_ticks_per_sec(), 32768) + 1;
 166         qemu_mod_timer(s->periodic_timer, s->next_periodic_time);
 167     } else {
 168 #ifdef TARGET_I386
 169         s->irq_coalesced = 0;
 170 #endif
 171         qemu_del_timer(s->periodic_timer);
 172     }
 173 }
 174
 175 static void rtc_periodic_timer(void *opaque)
 176 {
 177     RTCState *s = opaque;
 178
 179     rtc_timer_update(s, s->next_periodic_time);
 180     if (s->cmos_data[RTC_REG_B] & REG_B_PIE) {
 181         s->cmos_data[RTC_REG_C] |= 0xc0;
 182 #ifdef TARGET_I386
 183         if(rtc_td_hack) {
 184             apic_reset_irq_delivered();
 185             rtc_irq_raise(s->irq);
 186             if (!apic_get_irq_delivered()) {
 187                 s->irq_coalesced++;
 188                 rtc_coalesced_timer_update(s);
 189             }
 190         } else
 191 #endif
 192         rtc_irq_raise(s->irq);
 193     }
 194     if (s->cmos_data[RTC_REG_B] & REG_B_SQWE) {
 195         /* Not square wave at all but we don't want 2048Hz interrupts!
 196            Must be seen as a pulse.  */
 197         qemu_irq_raise(s->sqw_irq);
 198     }
 199 }
 200
 201 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
 202 {
 203     RTCState *s = opaque;
 204
 205     if ((addr & 1) == 0) {
 206         s->cmos_index = data & 0x7f;
 207     } else {
 208 #ifdef DEBUG_CMOS
 209         printf("cmos: write index=0x%02x val=0x%02x\n",
 210                s->cmos_index, data);
 211 #endif
 212         switch(s->cmos_index) {
 213         case RTC_SECONDS_ALARM:
 214         case RTC_MINUTES_ALARM:
 215         case RTC_HOURS_ALARM:
 216             /* XXX: not supported */
 217             s->cmos_data[s->cmos_index] = data;
 218             break;
 219         case RTC_SECONDS:
 220         case RTC_MINUTES:
 221         case RTC_HOURS:
 222         case RTC_DAY_OF_WEEK:
 223         case RTC_DAY_OF_MONTH:
 224         case RTC_MONTH:
 225         case RTC_YEAR:
 226             s->cmos_data[s->cmos_index] = data;
 227             /* if in set mode, do not update the time */
 228             if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 229                 rtc_set_time(s);
 230             }
 231             break;
 232         case RTC_REG_A:
 233             /* UIP bit is read only */
 234             s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) |
 235                 (s->cmos_data[RTC_REG_A] & REG_A_UIP);
 236             rtc_timer_update(s, qemu_get_clock(rtc_clock));
 237             break;
 238         case RTC_REG_B:
 239             if (data & REG_B_SET) {
 240                 /* set mode: reset UIP mode */
 241                 s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 242                 data &= ~REG_B_UIE;
 243             } else {
 244                 /* if disabling set mode, update the time */
 245                 if (s->cmos_data[RTC_REG_B] & REG_B_SET) {
 246                     rtc_set_time(s);
 247                 }
 248             }
 249             s->cmos_data[RTC_REG_B] = data;
 250             rtc_timer_update(s, qemu_get_clock(rtc_clock));
 251             break;
 252         case RTC_REG_C:
 253         case RTC_REG_D:
 254             /* cannot write to them */
 255             break;
 256         default:
 257             s->cmos_data[s->cmos_index] = data;
 258             break;
 259         }
 260     }
 261 }
 262
 263 static inline int to_bcd(RTCState *s, int a)
 264 {
 265     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 266         return a;
 267     } else {
 268         return ((a / 10) << 4) | (a % 10);
 269     }
 270 }
 271
 272 static inline int from_bcd(RTCState *s, int a)
 273 {
 274     if (s->cmos_data[RTC_REG_B] & REG_B_DM) {
 275         return a;
 276     } else {
 277         return ((a >> 4) * 10) + (a & 0x0f);
 278     }
 279 }
 280
 281 static void rtc_set_time(RTCState *s)
 282 {
 283     struct tm *tm = &s->current_tm;
 284
 285     tm->tm_sec = from_bcd(s, s->cmos_data[RTC_SECONDS]);
 286     tm->tm_min = from_bcd(s, s->cmos_data[RTC_MINUTES]);
 287     tm->tm_hour = from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f);
 288     if (!(s->cmos_data[RTC_REG_B] & 0x02) &&
 289         (s->cmos_data[RTC_HOURS] & 0x80)) {
 290         tm->tm_hour += 12;
 291     }
 292     tm->tm_wday = from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1;
 293     tm->tm_mday = from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]);
 294     tm->tm_mon = from_bcd(s, s->cmos_data[RTC_MONTH]) - 1;
 295     tm->tm_year = from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year - 1900;
 296 }
 297
 298 static void rtc_copy_date(RTCState *s)
 299 {
 300     const struct tm *tm = &s->current_tm;
 301     int year;
 302
 303     s->cmos_data[RTC_SECONDS] = to_bcd(s, tm->tm_sec);
 304     s->cmos_data[RTC_MINUTES] = to_bcd(s, tm->tm_min);
 305     if (s->cmos_data[RTC_REG_B] & 0x02) {
 306         /* 24 hour format */
 307         s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour);
 308     } else {
 309         /* 12 hour format */
 310         s->cmos_data[RTC_HOURS] = to_bcd(s, tm->tm_hour % 12);
 311         if (tm->tm_hour >= 12)
 312             s->cmos_data[RTC_HOURS] |= 0x80;
 313     }
 314     s->cmos_data[RTC_DAY_OF_WEEK] = to_bcd(s, tm->tm_wday + 1);
 315     s->cmos_data[RTC_DAY_OF_MONTH] = to_bcd(s, tm->tm_mday);
 316     s->cmos_data[RTC_MONTH] = to_bcd(s, tm->tm_mon + 1);
 317     year = (tm->tm_year - s->base_year) % 100;
 318     if (year < 0)
 319         year += 100;
 320     s->cmos_data[RTC_YEAR] = to_bcd(s, year);
 321 }
 322
 323 /* month is between 0 and 11. */
 324 static int get_days_in_month(int month, int year)
 325 {
 326     static const int days_tab[12] = {
 327         31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31
 328     };
 329     int d;
 330     if ((unsigned )month >= 12)
 331         return 31;
 332     d = days_tab[month];
 333     if (month == 1) {
 334         if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0))
 335             d++;
 336     }
 337     return d;
 338 }
 339
 340 /* update 'tm' to the next second */
 341 static void rtc_next_second(struct tm *tm)
 342 {
 343     int days_in_month;
 344
 345     tm->tm_sec++;
 346     if ((unsigned)tm->tm_sec >= 60) {
 347         tm->tm_sec = 0;
 348         tm->tm_min++;
 349         if ((unsigned)tm->tm_min >= 60) {
 350             tm->tm_min = 0;
 351             tm->tm_hour++;
 352             if ((unsigned)tm->tm_hour >= 24) {
 353                 tm->tm_hour = 0;
 354                 /* next day */
 355                 tm->tm_wday++;
 356                 if ((unsigned)tm->tm_wday >= 7)
 357                     tm->tm_wday = 0;
 358                 days_in_month = get_days_in_month(tm->tm_mon,
 359                                                   tm->tm_year + 1900);
 360                 tm->tm_mday++;
 361                 if (tm->tm_mday < 1) {
 362                     tm->tm_mday = 1;
 363                 } else if (tm->tm_mday > days_in_month) {
 364                     tm->tm_mday = 1;
 365                     tm->tm_mon++;
 366                     if (tm->tm_mon >= 12) {
 367                         tm->tm_mon = 0;
 368                         tm->tm_year++;
 369                     }
 370                 }
 371             }
 372         }
 373     }
 374 }
 375
 376
 377 static void rtc_update_second(void *opaque)
 378 {
 379     RTCState *s = opaque;
 380     int64_t delay;
 381
 382     /* if the oscillator is not in normal operation, we do not update */
 383     if ((s->cmos_data[RTC_REG_A] & 0x70) != 0x20) {
 384         s->next_second_time += get_ticks_per_sec();
 385         qemu_mod_timer(s->second_timer, s->next_second_time);
 386     } else {
 387         rtc_next_second(&s->current_tm);
 388
 389         if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 390             /* update in progress bit */
 391             s->cmos_data[RTC_REG_A] |= REG_A_UIP;
 392         }
 393         /* should be 244 us = 8 / 32768 seconds, but currently the
 394            timers do not have the necessary resolution. */
 395         delay = (get_ticks_per_sec() * 1) / 100;
 396         if (delay < 1)
 397             delay = 1;
 398         qemu_mod_timer(s->second_timer2,
 399                        s->next_second_time + delay);
 400     }
 401 }
 402
 403 static void rtc_update_second2(void *opaque)
 404 {
 405     RTCState *s = opaque;
 406
 407     if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) {
 408         rtc_copy_date(s);
 409     }
 410
 411     /* check alarm */
 412     if (s->cmos_data[RTC_REG_B] & REG_B_AIE) {
 413         if (((s->cmos_data[RTC_SECONDS_ALARM] & 0xc0) == 0xc0 ||
 414              s->cmos_data[RTC_SECONDS_ALARM] == s->current_tm.tm_sec) &&
 415             ((s->cmos_data[RTC_MINUTES_ALARM] & 0xc0) == 0xc0 ||
 416              s->cmos_data[RTC_MINUTES_ALARM] == s->current_tm.tm_mon) &&
 417             ((s->cmos_data[RTC_HOURS_ALARM] & 0xc0) == 0xc0 ||
 418              s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
 419
 420             s->cmos_data[RTC_REG_C] |= 0xa0;
 421             rtc_irq_raise(s->irq);
 422         }
 423     }
 424
 425     /* update ended interrupt */
 426     s->cmos_data[RTC_REG_C] |= REG_C_UF;
 427     if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
 428       s->cmos_data[RTC_REG_C] |= REG_C_IRQF;
 429       rtc_irq_raise(s->irq);
 430     }
 431
 432     /* clear update in progress bit */
 433     s->cmos_data[RTC_REG_A] &= ~REG_A_UIP;
 434
 435     s->next_second_time += get_ticks_per_sec();
 436     qemu_mod_timer(s->second_timer, s->next_second_time);
 437 }
 438
 439 static uint32_t cmos_ioport_read(void *opaque, uint32_t addr)
 440 {
 441     RTCState *s = opaque;
 442     int ret;
 443     if ((addr & 1) == 0) {
 444         return 0xff;
 445     } else {
 446         switch(s->cmos_index) {
 447         case RTC_SECONDS:
 448         case RTC_MINUTES:
 449         case RTC_HOURS:
 450         case RTC_DAY_OF_WEEK:
 451         case RTC_DAY_OF_MONTH:
 452         case RTC_MONTH:
 453         case RTC_YEAR:
 454             ret = s->cmos_data[s->cmos_index];
 455             break;
 456         case RTC_REG_A:
 457             ret = s->cmos_data[s->cmos_index];
 458             break;
 459         case RTC_REG_C:
 460             ret = s->cmos_data[s->cmos_index];
 461             qemu_irq_lower(s->irq);
 462             s->cmos_data[RTC_REG_C] = 0x00;
 463             break;
 464         default:
 465             ret = s->cmos_data[s->cmos_index];
 466             break;
 467         }
 468 #ifdef DEBUG_CMOS
 469         printf("cmos: read index=0x%02x val=0x%02x\n",
 470                s->cmos_index, ret);
 471 #endif
 472         return ret;
 473     }
 474 }
 475
 476 void rtc_set_memory(RTCState *s, int addr, int val)
 477 {
 478     if (addr >= 0 && addr <= 127)
 479         s->cmos_data[addr] = val;
 480 }
 481
 482 void rtc_set_date(RTCState *s, const struct tm *tm)
 483 {
 484     s->current_tm = *tm;
 485     rtc_copy_date(s);
 486 }
 487
 488 /* PC cmos mappings */
 489 #define REG_IBM_CENTURY_BYTE        0x32
 490 #define REG_IBM_PS2_CENTURY_BYTE    0x37
 491
 492 static void rtc_set_date_from_host(RTCState *s)
 493 {
 494     struct tm tm;
 495     int val;
 496
 497     /* set the CMOS date */
 498     qemu_get_timedate(&tm, 0);
 499     rtc_set_date(s, &tm);
 500
 501     val = to_bcd(s, (tm.tm_year / 100) + 19);
 502     rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
 503     rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
 504 }
 505
 506 static void rtc_save(QEMUFile *f, void *opaque)
 507 {
 508     RTCState *s = opaque;
 509
 510     qemu_put_buffer(f, s->cmos_data, 128);
 511     qemu_put_8s(f, &s->cmos_index);
 512
 513     qemu_put_be32(f, s->current_tm.tm_sec);
 514     qemu_put_be32(f, s->current_tm.tm_min);
 515     qemu_put_be32(f, s->current_tm.tm_hour);
 516     qemu_put_be32(f, s->current_tm.tm_wday);
 517     qemu_put_be32(f, s->current_tm.tm_mday);
 518     qemu_put_be32(f, s->current_tm.tm_mon);
 519     qemu_put_be32(f, s->current_tm.tm_year);
 520
 521     qemu_put_timer(f, s->periodic_timer);
 522     qemu_put_be64(f, s->next_periodic_time);
 523
 524     qemu_put_be64(f, s->next_second_time);
 525     qemu_put_timer(f, s->second_timer);
 526     qemu_put_timer(f, s->second_timer2);
 527 }
 528
 529 static int rtc_load(QEMUFile *f, void *opaque, int version_id)
 530 {
 531     RTCState *s = opaque;
 532
 533     if (version_id != 1)
 534         return -EINVAL;
 535
 536     qemu_get_buffer(f, s->cmos_data, 128);
 537     qemu_get_8s(f, &s->cmos_index);
 538
 539     s->current_tm.tm_sec=qemu_get_be32(f);
 540     s->current_tm.tm_min=qemu_get_be32(f);
 541     s->current_tm.tm_hour=qemu_get_be32(f);
 542     s->current_tm.tm_wday=qemu_get_be32(f);
 543     s->current_tm.tm_mday=qemu_get_be32(f);
 544     s->current_tm.tm_mon=qemu_get_be32(f);
 545     s->current_tm.tm_year=qemu_get_be32(f);
 546
 547     qemu_get_timer(f, s->periodic_timer);
 548     s->next_periodic_time=qemu_get_be64(f);
 549
 550     s->next_second_time=qemu_get_be64(f);
 551     qemu_get_timer(f, s->second_timer);
 552     qemu_get_timer(f, s->second_timer2);
 553     return 0;
 554 }
 555
 556 #ifdef TARGET_I386
 557 static void rtc_save_td(QEMUFile *f, void *opaque)
 558 {
 559     RTCState *s = opaque;
 560
 561     qemu_put_be32(f, s->irq_coalesced);
 562     qemu_put_be32(f, s->period);
 563 }
 564
 565 static int rtc_load_td(QEMUFile *f, void *opaque, int version_id)
 566 {
 567     RTCState *s = opaque;
 568
 569     if (version_id != 1)
 570         return -EINVAL;
 571
 572     s->irq_coalesced = qemu_get_be32(f);
 573     s->period = qemu_get_be32(f);
 574     rtc_coalesced_timer_update(s);
 575     return 0;
 576 }
 577 #endif
 578
 579 static void rtc_reset(void *opaque)
 580 {
 581     RTCState *s = opaque;
 582
 583     s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE);
 584     s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF);
 585
 586     qemu_irq_lower(s->irq);
 587
 588 #ifdef TARGET_I386
 589     if (rtc_td_hack)
 590             s->irq_coalesced = 0;
 591 #endif
 592 }
 593
 594 static int rtc_initfn(ISADevice *dev)
 595 {
 596     RTCState *s = DO_UPCAST(RTCState, dev, dev);
 597     int base = 0x70;
 598     int isairq = 8;
 599
 600     isa_init_irq(dev, &s->irq, isairq);
 601
 602     s->cmos_data[RTC_REG_A] = 0x26;
 603     s->cmos_data[RTC_REG_B] = 0x02;
 604     s->cmos_data[RTC_REG_C] = 0x00;
 605     s->cmos_data[RTC_REG_D] = 0x80;
 606
 607     rtc_set_date_from_host(s);
 608
 609     s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s);
 610 #ifdef TARGET_I386
 611     if (rtc_td_hack)
 612         s->coalesced_timer =
 613             qemu_new_timer(rtc_clock, rtc_coalesced_timer, s);
 614 #endif
 615     s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s);
 616     s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s);
 617
 618     s->next_second_time =
 619         qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
 620     qemu_mod_timer(s->second_timer2, s->next_second_time);
 621
 622     register_ioport_write(base, 2, 1, cmos_ioport_write, s);
 623     register_ioport_read(base, 2, 1, cmos_ioport_read, s);
 624
 625     register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
 626 #ifdef TARGET_I386
 627     if (rtc_td_hack)
 628         register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s);
 629 #endif
 630     qemu_register_reset(rtc_reset, s);
 631     return 0;
 632 }
 633
 634 RTCState *rtc_init(int base_year)
 635 {
 636     ISADevice *dev;
 637
 638     dev = isa_create("mc146818rtc");
 639     qdev_prop_set_int32(&dev->qdev, "base_year", base_year);
 640     qdev_init_nofail(&dev->qdev);
 641     return DO_UPCAST(RTCState, dev, dev);
 642 }
 643
 644 static ISADeviceInfo mc146818rtc_info = {
 645     .qdev.name     = "mc146818rtc",
 646     .qdev.size     = sizeof(RTCState),
 647     .qdev.no_user  = 1,
 648     .init          = rtc_initfn,
 649     .qdev.props    = (Property[]) {
 650         DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
 651         DEFINE_PROP_END_OF_LIST(),
 652     }
 653 };
 654
 655 static void mc146818rtc_register(void)
 656 {
 657     isa_qdev_register(&mc146818rtc_info);
 658 }
 659 device_init(mc146818rtc_register)
 660
 661 /* Memory mapped interface */
 662 static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
 663 {
 664     RTCState *s = opaque;
 665
 666     return cmos_ioport_read(s, addr >> s->it_shift) & 0xFF;
 667 }
 668
 669 static void cmos_mm_writeb (void *opaque,
 670                             target_phys_addr_t addr, uint32_t value)
 671 {
 672     RTCState *s = opaque;
 673
 674     cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
 675 }
 676
 677 static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
 678 {
 679     RTCState *s = opaque;
 680     uint32_t val;
 681
 682     val = cmos_ioport_read(s, addr >> s->it_shift) & 0xFFFF;
 683 #ifdef TARGET_WORDS_BIGENDIAN
 684     val = bswap16(val);
 685 #endif
 686     return val;
 687 }
 688
 689 static void cmos_mm_writew (void *opaque,
 690                             target_phys_addr_t addr, uint32_t value)
 691 {
 692     RTCState *s = opaque;
 693 #ifdef TARGET_WORDS_BIGENDIAN
 694     value = bswap16(value);
 695 #endif
 696     cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
 697 }
 698
 699 static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
 700 {
 701     RTCState *s = opaque;
 702     uint32_t val;
 703
 704     val = cmos_ioport_read(s, addr >> s->it_shift);
 705 #ifdef TARGET_WORDS_BIGENDIAN
 706     val = bswap32(val);
 707 #endif
 708     return val;
 709 }
 710
 711 static void cmos_mm_writel (void *opaque,
 712                             target_phys_addr_t addr, uint32_t value)
 713 {
 714     RTCState *s = opaque;
 715 #ifdef TARGET_WORDS_BIGENDIAN
 716     value = bswap32(value);
 717 #endif
 718     cmos_ioport_write(s, addr >> s->it_shift, value);
 719 }
 720
 721 static CPUReadMemoryFunc * const rtc_mm_read[] = {
 722     &cmos_mm_readb,
 723     &cmos_mm_readw,
 724     &cmos_mm_readl,
 725 };
 726
 727 static CPUWriteMemoryFunc * const rtc_mm_write[] = {
 728     &cmos_mm_writeb,
 729     &cmos_mm_writew,
 730     &cmos_mm_writel,
 731 };
 732
 733 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
 734                       int base_year)
 735 {
 736     RTCState *s;
 737     int io_memory;
 738
 739     s = qemu_mallocz(sizeof(RTCState));
 740
 741     s->irq = irq;
 742     s->cmos_data[RTC_REG_A] = 0x26;
 743     s->cmos_data[RTC_REG_B] = 0x02;
 744     s->cmos_data[RTC_REG_C] = 0x00;
 745     s->cmos_data[RTC_REG_D] = 0x80;
 746
 747     s->base_year = base_year;
 748     rtc_set_date_from_host(s);
 749
 750     s->periodic_timer = qemu_new_timer(rtc_clock, rtc_periodic_timer, s);
 751     s->second_timer = qemu_new_timer(rtc_clock, rtc_update_second, s);
 752     s->second_timer2 = qemu_new_timer(rtc_clock, rtc_update_second2, s);
 753
 754     s->next_second_time =
 755         qemu_get_clock(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
 756     qemu_mod_timer(s->second_timer2, s->next_second_time);
 757
 758     io_memory = cpu_register_io_memory(rtc_mm_read, rtc_mm_write, s);
 759     cpu_register_physical_memory(base, 2 << it_shift, io_memory);
 760
 761     register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
 762 #ifdef TARGET_I386
 763     if (rtc_td_hack)
 764         register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s);
 765 #endif
 766     qemu_register_reset(rtc_reset, s);
 767     return s;
 768 }