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[mirror_qemu.git] / hw / mips / gt64xxx_pci.c
1 /*
2 * QEMU GT64120 PCI host
3 *
4 * Copyright (c) 2006,2007 Aurelien Jarno
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "hw/hw.h"
26 #include "hw/mips/mips.h"
27 #include "hw/pci/pci.h"
28 #include "hw/pci/pci_host.h"
29 #include "hw/i386/pc.h"
30 #include "exec/address-spaces.h"
31
32 //#define DEBUG
33
34 #ifdef DEBUG
35 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
36 #else
37 #define DPRINTF(fmt, ...)
38 #endif
39
40 #define GT_REGS (0x1000 >> 2)
41
42 /* CPU Configuration */
43 #define GT_CPU (0x000 >> 2)
44 #define GT_MULTI (0x120 >> 2)
45
46 /* CPU Address Decode */
47 #define GT_SCS10LD (0x008 >> 2)
48 #define GT_SCS10HD (0x010 >> 2)
49 #define GT_SCS32LD (0x018 >> 2)
50 #define GT_SCS32HD (0x020 >> 2)
51 #define GT_CS20LD (0x028 >> 2)
52 #define GT_CS20HD (0x030 >> 2)
53 #define GT_CS3BOOTLD (0x038 >> 2)
54 #define GT_CS3BOOTHD (0x040 >> 2)
55 #define GT_PCI0IOLD (0x048 >> 2)
56 #define GT_PCI0IOHD (0x050 >> 2)
57 #define GT_PCI0M0LD (0x058 >> 2)
58 #define GT_PCI0M0HD (0x060 >> 2)
59 #define GT_PCI0M1LD (0x080 >> 2)
60 #define GT_PCI0M1HD (0x088 >> 2)
61 #define GT_PCI1IOLD (0x090 >> 2)
62 #define GT_PCI1IOHD (0x098 >> 2)
63 #define GT_PCI1M0LD (0x0a0 >> 2)
64 #define GT_PCI1M0HD (0x0a8 >> 2)
65 #define GT_PCI1M1LD (0x0b0 >> 2)
66 #define GT_PCI1M1HD (0x0b8 >> 2)
67 #define GT_ISD (0x068 >> 2)
68
69 #define GT_SCS10AR (0x0d0 >> 2)
70 #define GT_SCS32AR (0x0d8 >> 2)
71 #define GT_CS20R (0x0e0 >> 2)
72 #define GT_CS3BOOTR (0x0e8 >> 2)
73
74 #define GT_PCI0IOREMAP (0x0f0 >> 2)
75 #define GT_PCI0M0REMAP (0x0f8 >> 2)
76 #define GT_PCI0M1REMAP (0x100 >> 2)
77 #define GT_PCI1IOREMAP (0x108 >> 2)
78 #define GT_PCI1M0REMAP (0x110 >> 2)
79 #define GT_PCI1M1REMAP (0x118 >> 2)
80
81 /* CPU Error Report */
82 #define GT_CPUERR_ADDRLO (0x070 >> 2)
83 #define GT_CPUERR_ADDRHI (0x078 >> 2)
84 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
85 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
86 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
87
88 /* CPU Sync Barrier */
89 #define GT_PCI0SYNC (0x0c0 >> 2)
90 #define GT_PCI1SYNC (0x0c8 >> 2)
91
92 /* SDRAM and Device Address Decode */
93 #define GT_SCS0LD (0x400 >> 2)
94 #define GT_SCS0HD (0x404 >> 2)
95 #define GT_SCS1LD (0x408 >> 2)
96 #define GT_SCS1HD (0x40c >> 2)
97 #define GT_SCS2LD (0x410 >> 2)
98 #define GT_SCS2HD (0x414 >> 2)
99 #define GT_SCS3LD (0x418 >> 2)
100 #define GT_SCS3HD (0x41c >> 2)
101 #define GT_CS0LD (0x420 >> 2)
102 #define GT_CS0HD (0x424 >> 2)
103 #define GT_CS1LD (0x428 >> 2)
104 #define GT_CS1HD (0x42c >> 2)
105 #define GT_CS2LD (0x430 >> 2)
106 #define GT_CS2HD (0x434 >> 2)
107 #define GT_CS3LD (0x438 >> 2)
108 #define GT_CS3HD (0x43c >> 2)
109 #define GT_BOOTLD (0x440 >> 2)
110 #define GT_BOOTHD (0x444 >> 2)
111 #define GT_ADERR (0x470 >> 2)
112
113 /* SDRAM Configuration */
114 #define GT_SDRAM_CFG (0x448 >> 2)
115 #define GT_SDRAM_OPMODE (0x474 >> 2)
116 #define GT_SDRAM_BM (0x478 >> 2)
117 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
118
119 /* SDRAM Parameters */
120 #define GT_SDRAM_B0 (0x44c >> 2)
121 #define GT_SDRAM_B1 (0x450 >> 2)
122 #define GT_SDRAM_B2 (0x454 >> 2)
123 #define GT_SDRAM_B3 (0x458 >> 2)
124
125 /* Device Parameters */
126 #define GT_DEV_B0 (0x45c >> 2)
127 #define GT_DEV_B1 (0x460 >> 2)
128 #define GT_DEV_B2 (0x464 >> 2)
129 #define GT_DEV_B3 (0x468 >> 2)
130 #define GT_DEV_BOOT (0x46c >> 2)
131
132 /* ECC */
133 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
134 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
135 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
136 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
137 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
138
139 /* DMA Record */
140 #define GT_DMA0_CNT (0x800 >> 2)
141 #define GT_DMA1_CNT (0x804 >> 2)
142 #define GT_DMA2_CNT (0x808 >> 2)
143 #define GT_DMA3_CNT (0x80c >> 2)
144 #define GT_DMA0_SA (0x810 >> 2)
145 #define GT_DMA1_SA (0x814 >> 2)
146 #define GT_DMA2_SA (0x818 >> 2)
147 #define GT_DMA3_SA (0x81c >> 2)
148 #define GT_DMA0_DA (0x820 >> 2)
149 #define GT_DMA1_DA (0x824 >> 2)
150 #define GT_DMA2_DA (0x828 >> 2)
151 #define GT_DMA3_DA (0x82c >> 2)
152 #define GT_DMA0_NEXT (0x830 >> 2)
153 #define GT_DMA1_NEXT (0x834 >> 2)
154 #define GT_DMA2_NEXT (0x838 >> 2)
155 #define GT_DMA3_NEXT (0x83c >> 2)
156 #define GT_DMA0_CUR (0x870 >> 2)
157 #define GT_DMA1_CUR (0x874 >> 2)
158 #define GT_DMA2_CUR (0x878 >> 2)
159 #define GT_DMA3_CUR (0x87c >> 2)
160
161 /* DMA Channel Control */
162 #define GT_DMA0_CTRL (0x840 >> 2)
163 #define GT_DMA1_CTRL (0x844 >> 2)
164 #define GT_DMA2_CTRL (0x848 >> 2)
165 #define GT_DMA3_CTRL (0x84c >> 2)
166
167 /* DMA Arbiter */
168 #define GT_DMA_ARB (0x860 >> 2)
169
170 /* Timer/Counter */
171 #define GT_TC0 (0x850 >> 2)
172 #define GT_TC1 (0x854 >> 2)
173 #define GT_TC2 (0x858 >> 2)
174 #define GT_TC3 (0x85c >> 2)
175 #define GT_TC_CONTROL (0x864 >> 2)
176
177 /* PCI Internal */
178 #define GT_PCI0_CMD (0xc00 >> 2)
179 #define GT_PCI0_TOR (0xc04 >> 2)
180 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
181 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
182 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
183 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
184 #define GT_PCI1_IACK (0xc30 >> 2)
185 #define GT_PCI0_IACK (0xc34 >> 2)
186 #define GT_PCI0_BARE (0xc3c >> 2)
187 #define GT_PCI0_PREFMBR (0xc40 >> 2)
188 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
189 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
190 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
191 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
192 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
193 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
194 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
195 #define GT_PCI1_CMD (0xc80 >> 2)
196 #define GT_PCI1_TOR (0xc84 >> 2)
197 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
198 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
199 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
200 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
201 #define GT_PCI1_BARE (0xcbc >> 2)
202 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
203 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
204 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
205 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
206 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
207 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
208 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
209 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
210 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
211 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
212 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
213 #define GT_PCI0_CFGDATA (0xcfc >> 2)
214
215 /* Interrupts */
216 #define GT_INTRCAUSE (0xc18 >> 2)
217 #define GT_INTRMASK (0xc1c >> 2)
218 #define GT_PCI0_ICMASK (0xc24 >> 2)
219 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
220 #define GT_CPU_INTSEL (0xc70 >> 2)
221 #define GT_PCI0_INTSEL (0xc74 >> 2)
222 #define GT_HINTRCAUSE (0xc98 >> 2)
223 #define GT_HINTRMASK (0xc9c >> 2)
224 #define GT_PCI0_HICMASK (0xca4 >> 2)
225 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
226
227 #define PCI_MAPPING_ENTRY(regname) \
228 hwaddr regname ##_start; \
229 hwaddr regname ##_length; \
230 MemoryRegion regname ##_mem
231
232 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
233
234 #define GT64120_PCI_HOST_BRIDGE(obj) \
235 OBJECT_CHECK(GT64120State, (obj), TYPE_GT64120_PCI_HOST_BRIDGE)
236
237 typedef struct GT64120State {
238 PCIHostState parent_obj;
239
240 uint32_t regs[GT_REGS];
241 PCI_MAPPING_ENTRY(PCI0IO);
242 PCI_MAPPING_ENTRY(PCI0M0);
243 PCI_MAPPING_ENTRY(PCI0M1);
244 PCI_MAPPING_ENTRY(ISD);
245 MemoryRegion pci0_mem;
246 AddressSpace pci0_mem_as;
247 } GT64120State;
248
249 /* Adjust range to avoid touching space which isn't mappable via PCI */
250 /* XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
251 0x1fc00000 - 0x1fd00000 */
252 static void check_reserved_space (hwaddr *start,
253 hwaddr *length)
254 {
255 hwaddr begin = *start;
256 hwaddr end = *start + *length;
257
258 if (end >= 0x1e000000LL && end < 0x1f100000LL)
259 end = 0x1e000000LL;
260 if (begin >= 0x1e000000LL && begin < 0x1f100000LL)
261 begin = 0x1f100000LL;
262 if (end >= 0x1fc00000LL && end < 0x1fd00000LL)
263 end = 0x1fc00000LL;
264 if (begin >= 0x1fc00000LL && begin < 0x1fd00000LL)
265 begin = 0x1fd00000LL;
266 /* XXX: This is broken when a reserved range splits the requested range */
267 if (end >= 0x1f100000LL && begin < 0x1e000000LL)
268 end = 0x1e000000LL;
269 if (end >= 0x1fd00000LL && begin < 0x1fc00000LL)
270 end = 0x1fc00000LL;
271
272 *start = begin;
273 *length = end - begin;
274 }
275
276 static void gt64120_isd_mapping(GT64120State *s)
277 {
278 hwaddr start = s->regs[GT_ISD] << 21;
279 hwaddr length = 0x1000;
280
281 if (s->ISD_length) {
282 memory_region_del_subregion(get_system_memory(), &s->ISD_mem);
283 }
284 check_reserved_space(&start, &length);
285 length = 0x1000;
286 /* Map new address */
287 DPRINTF("ISD: "TARGET_FMT_plx"@"TARGET_FMT_plx
288 " -> "TARGET_FMT_plx"@"TARGET_FMT_plx"\n",
289 s->ISD_length, s->ISD_start, length, start);
290 s->ISD_start = start;
291 s->ISD_length = length;
292 memory_region_add_subregion(get_system_memory(), s->ISD_start, &s->ISD_mem);
293 }
294
295 static void gt64120_pci_mapping(GT64120State *s)
296 {
297 /* Update PCI0IO mapping */
298 if ((s->regs[GT_PCI0IOLD] & 0x7f) <= s->regs[GT_PCI0IOHD]) {
299 /* Unmap old IO address */
300 if (s->PCI0IO_length) {
301 memory_region_del_subregion(get_system_memory(), &s->PCI0IO_mem);
302 object_unparent(OBJECT(&s->PCI0IO_mem));
303 }
304 /* Map new IO address */
305 s->PCI0IO_start = s->regs[GT_PCI0IOLD] << 21;
306 s->PCI0IO_length = ((s->regs[GT_PCI0IOHD] + 1) -
307 (s->regs[GT_PCI0IOLD] & 0x7f)) << 21;
308 if (s->PCI0IO_length) {
309 memory_region_init_alias(&s->PCI0IO_mem, OBJECT(s), "pci0-io",
310 get_system_io(), 0, s->PCI0IO_length);
311 memory_region_add_subregion(get_system_memory(), s->PCI0IO_start,
312 &s->PCI0IO_mem);
313 }
314 }
315
316 /* Update PCI0M0 mapping */
317 if ((s->regs[GT_PCI0M0LD] & 0x7f) <= s->regs[GT_PCI0M0HD]) {
318 /* Unmap old MEM address */
319 if (s->PCI0M0_length) {
320 memory_region_del_subregion(get_system_memory(), &s->PCI0M0_mem);
321 object_unparent(OBJECT(&s->PCI0M0_mem));
322 }
323 /* Map new mem address */
324 s->PCI0M0_start = s->regs[GT_PCI0M0LD] << 21;
325 s->PCI0M0_length = ((s->regs[GT_PCI0M0HD] + 1) -
326 (s->regs[GT_PCI0M0LD] & 0x7f)) << 21;
327 if (s->PCI0M0_length) {
328 memory_region_init_alias(&s->PCI0M0_mem, OBJECT(s), "pci0-mem0",
329 &s->pci0_mem, s->PCI0M0_start,
330 s->PCI0M0_length);
331 memory_region_add_subregion(get_system_memory(), s->PCI0M0_start,
332 &s->PCI0M0_mem);
333 }
334 }
335
336 /* Update PCI0M1 mapping */
337 if ((s->regs[GT_PCI0M1LD] & 0x7f) <= s->regs[GT_PCI0M1HD]) {
338 /* Unmap old MEM address */
339 if (s->PCI0M1_length) {
340 memory_region_del_subregion(get_system_memory(), &s->PCI0M1_mem);
341 object_unparent(OBJECT(&s->PCI0M1_mem));
342 }
343 /* Map new mem address */
344 s->PCI0M1_start = s->regs[GT_PCI0M1LD] << 21;
345 s->PCI0M1_length = ((s->regs[GT_PCI0M1HD] + 1) -
346 (s->regs[GT_PCI0M1LD] & 0x7f)) << 21;
347 if (s->PCI0M1_length) {
348 memory_region_init_alias(&s->PCI0M1_mem, OBJECT(s), "pci0-mem1",
349 &s->pci0_mem, s->PCI0M1_start,
350 s->PCI0M1_length);
351 memory_region_add_subregion(get_system_memory(), s->PCI0M1_start,
352 &s->PCI0M1_mem);
353 }
354 }
355 }
356
357 static int gt64120_post_load(void *opaque, int version_id)
358 {
359 GT64120State *s = opaque;
360
361 gt64120_isd_mapping(s);
362 gt64120_pci_mapping(s);
363
364 return 0;
365 }
366
367 static const VMStateDescription vmstate_gt64120 = {
368 .name = "gt64120",
369 .version_id = 1,
370 .minimum_version_id = 1,
371 .post_load = gt64120_post_load,
372 .fields = (VMStateField[]) {
373 VMSTATE_UINT32_ARRAY(regs, GT64120State, GT_REGS),
374 VMSTATE_END_OF_LIST()
375 }
376 };
377
378 static void gt64120_writel (void *opaque, hwaddr addr,
379 uint64_t val, unsigned size)
380 {
381 GT64120State *s = opaque;
382 PCIHostState *phb = PCI_HOST_BRIDGE(s);
383 uint32_t saddr;
384
385 if (!(s->regs[GT_CPU] & 0x00001000))
386 val = bswap32(val);
387
388 saddr = (addr & 0xfff) >> 2;
389 switch (saddr) {
390
391 /* CPU Configuration */
392 case GT_CPU:
393 s->regs[GT_CPU] = val;
394 break;
395 case GT_MULTI:
396 /* Read-only register as only one GT64xxx is present on the CPU bus */
397 break;
398
399 /* CPU Address Decode */
400 case GT_PCI0IOLD:
401 s->regs[GT_PCI0IOLD] = val & 0x00007fff;
402 s->regs[GT_PCI0IOREMAP] = val & 0x000007ff;
403 gt64120_pci_mapping(s);
404 break;
405 case GT_PCI0M0LD:
406 s->regs[GT_PCI0M0LD] = val & 0x00007fff;
407 s->regs[GT_PCI0M0REMAP] = val & 0x000007ff;
408 gt64120_pci_mapping(s);
409 break;
410 case GT_PCI0M1LD:
411 s->regs[GT_PCI0M1LD] = val & 0x00007fff;
412 s->regs[GT_PCI0M1REMAP] = val & 0x000007ff;
413 gt64120_pci_mapping(s);
414 break;
415 case GT_PCI1IOLD:
416 s->regs[GT_PCI1IOLD] = val & 0x00007fff;
417 s->regs[GT_PCI1IOREMAP] = val & 0x000007ff;
418 break;
419 case GT_PCI1M0LD:
420 s->regs[GT_PCI1M0LD] = val & 0x00007fff;
421 s->regs[GT_PCI1M0REMAP] = val & 0x000007ff;
422 break;
423 case GT_PCI1M1LD:
424 s->regs[GT_PCI1M1LD] = val & 0x00007fff;
425 s->regs[GT_PCI1M1REMAP] = val & 0x000007ff;
426 break;
427 case GT_PCI0M0HD:
428 case GT_PCI0M1HD:
429 case GT_PCI0IOHD:
430 s->regs[saddr] = val & 0x0000007f;
431 gt64120_pci_mapping(s);
432 break;
433 case GT_PCI1IOHD:
434 case GT_PCI1M0HD:
435 case GT_PCI1M1HD:
436 s->regs[saddr] = val & 0x0000007f;
437 break;
438 case GT_ISD:
439 s->regs[saddr] = val & 0x00007fff;
440 gt64120_isd_mapping(s);
441 break;
442
443 case GT_PCI0IOREMAP:
444 case GT_PCI0M0REMAP:
445 case GT_PCI0M1REMAP:
446 case GT_PCI1IOREMAP:
447 case GT_PCI1M0REMAP:
448 case GT_PCI1M1REMAP:
449 s->regs[saddr] = val & 0x000007ff;
450 break;
451
452 /* CPU Error Report */
453 case GT_CPUERR_ADDRLO:
454 case GT_CPUERR_ADDRHI:
455 case GT_CPUERR_DATALO:
456 case GT_CPUERR_DATAHI:
457 case GT_CPUERR_PARITY:
458 /* Read-only registers, do nothing */
459 break;
460
461 /* CPU Sync Barrier */
462 case GT_PCI0SYNC:
463 case GT_PCI1SYNC:
464 /* Read-only registers, do nothing */
465 break;
466
467 /* SDRAM and Device Address Decode */
468 case GT_SCS0LD:
469 case GT_SCS0HD:
470 case GT_SCS1LD:
471 case GT_SCS1HD:
472 case GT_SCS2LD:
473 case GT_SCS2HD:
474 case GT_SCS3LD:
475 case GT_SCS3HD:
476 case GT_CS0LD:
477 case GT_CS0HD:
478 case GT_CS1LD:
479 case GT_CS1HD:
480 case GT_CS2LD:
481 case GT_CS2HD:
482 case GT_CS3LD:
483 case GT_CS3HD:
484 case GT_BOOTLD:
485 case GT_BOOTHD:
486 case GT_ADERR:
487 /* SDRAM Configuration */
488 case GT_SDRAM_CFG:
489 case GT_SDRAM_OPMODE:
490 case GT_SDRAM_BM:
491 case GT_SDRAM_ADDRDECODE:
492 /* Accept and ignore SDRAM interleave configuration */
493 s->regs[saddr] = val;
494 break;
495
496 /* Device Parameters */
497 case GT_DEV_B0:
498 case GT_DEV_B1:
499 case GT_DEV_B2:
500 case GT_DEV_B3:
501 case GT_DEV_BOOT:
502 /* Not implemented */
503 DPRINTF ("Unimplemented device register offset 0x%x\n", saddr << 2);
504 break;
505
506 /* ECC */
507 case GT_ECC_ERRDATALO:
508 case GT_ECC_ERRDATAHI:
509 case GT_ECC_MEM:
510 case GT_ECC_CALC:
511 case GT_ECC_ERRADDR:
512 /* Read-only registers, do nothing */
513 break;
514
515 /* DMA Record */
516 case GT_DMA0_CNT:
517 case GT_DMA1_CNT:
518 case GT_DMA2_CNT:
519 case GT_DMA3_CNT:
520 case GT_DMA0_SA:
521 case GT_DMA1_SA:
522 case GT_DMA2_SA:
523 case GT_DMA3_SA:
524 case GT_DMA0_DA:
525 case GT_DMA1_DA:
526 case GT_DMA2_DA:
527 case GT_DMA3_DA:
528 case GT_DMA0_NEXT:
529 case GT_DMA1_NEXT:
530 case GT_DMA2_NEXT:
531 case GT_DMA3_NEXT:
532 case GT_DMA0_CUR:
533 case GT_DMA1_CUR:
534 case GT_DMA2_CUR:
535 case GT_DMA3_CUR:
536 /* Not implemented */
537 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
538 break;
539
540 /* DMA Channel Control */
541 case GT_DMA0_CTRL:
542 case GT_DMA1_CTRL:
543 case GT_DMA2_CTRL:
544 case GT_DMA3_CTRL:
545 /* Not implemented */
546 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
547 break;
548
549 /* DMA Arbiter */
550 case GT_DMA_ARB:
551 /* Not implemented */
552 DPRINTF ("Unimplemented DMA register offset 0x%x\n", saddr << 2);
553 break;
554
555 /* Timer/Counter */
556 case GT_TC0:
557 case GT_TC1:
558 case GT_TC2:
559 case GT_TC3:
560 case GT_TC_CONTROL:
561 /* Not implemented */
562 DPRINTF ("Unimplemented timer register offset 0x%x\n", saddr << 2);
563 break;
564
565 /* PCI Internal */
566 case GT_PCI0_CMD:
567 case GT_PCI1_CMD:
568 s->regs[saddr] = val & 0x0401fc0f;
569 break;
570 case GT_PCI0_TOR:
571 case GT_PCI0_BS_SCS10:
572 case GT_PCI0_BS_SCS32:
573 case GT_PCI0_BS_CS20:
574 case GT_PCI0_BS_CS3BT:
575 case GT_PCI1_IACK:
576 case GT_PCI0_IACK:
577 case GT_PCI0_BARE:
578 case GT_PCI0_PREFMBR:
579 case GT_PCI0_SCS10_BAR:
580 case GT_PCI0_SCS32_BAR:
581 case GT_PCI0_CS20_BAR:
582 case GT_PCI0_CS3BT_BAR:
583 case GT_PCI0_SSCS10_BAR:
584 case GT_PCI0_SSCS32_BAR:
585 case GT_PCI0_SCS3BT_BAR:
586 case GT_PCI1_TOR:
587 case GT_PCI1_BS_SCS10:
588 case GT_PCI1_BS_SCS32:
589 case GT_PCI1_BS_CS20:
590 case GT_PCI1_BS_CS3BT:
591 case GT_PCI1_BARE:
592 case GT_PCI1_PREFMBR:
593 case GT_PCI1_SCS10_BAR:
594 case GT_PCI1_SCS32_BAR:
595 case GT_PCI1_CS20_BAR:
596 case GT_PCI1_CS3BT_BAR:
597 case GT_PCI1_SSCS10_BAR:
598 case GT_PCI1_SSCS32_BAR:
599 case GT_PCI1_SCS3BT_BAR:
600 case GT_PCI1_CFGADDR:
601 case GT_PCI1_CFGDATA:
602 /* not implemented */
603 break;
604 case GT_PCI0_CFGADDR:
605 phb->config_reg = val & 0x80fffffc;
606 break;
607 case GT_PCI0_CFGDATA:
608 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
609 val = bswap32(val);
610 }
611 if (phb->config_reg & (1u << 31)) {
612 pci_data_write(phb->bus, phb->config_reg, val, 4);
613 }
614 break;
615
616 /* Interrupts */
617 case GT_INTRCAUSE:
618 /* not really implemented */
619 s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
620 s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
621 DPRINTF("INTRCAUSE %" PRIx64 "\n", val);
622 break;
623 case GT_INTRMASK:
624 s->regs[saddr] = val & 0x3c3ffffe;
625 DPRINTF("INTRMASK %" PRIx64 "\n", val);
626 break;
627 case GT_PCI0_ICMASK:
628 s->regs[saddr] = val & 0x03fffffe;
629 DPRINTF("ICMASK %" PRIx64 "\n", val);
630 break;
631 case GT_PCI0_SERR0MASK:
632 s->regs[saddr] = val & 0x0000003f;
633 DPRINTF("SERR0MASK %" PRIx64 "\n", val);
634 break;
635
636 /* Reserved when only PCI_0 is configured. */
637 case GT_HINTRCAUSE:
638 case GT_CPU_INTSEL:
639 case GT_PCI0_INTSEL:
640 case GT_HINTRMASK:
641 case GT_PCI0_HICMASK:
642 case GT_PCI1_SERR1MASK:
643 /* not implemented */
644 break;
645
646 /* SDRAM Parameters */
647 case GT_SDRAM_B0:
648 case GT_SDRAM_B1:
649 case GT_SDRAM_B2:
650 case GT_SDRAM_B3:
651 /* We don't simulate electrical parameters of the SDRAM.
652 Accept, but ignore the values. */
653 s->regs[saddr] = val;
654 break;
655
656 default:
657 DPRINTF ("Bad register offset 0x%x\n", (int)addr);
658 break;
659 }
660 }
661
662 static uint64_t gt64120_readl (void *opaque,
663 hwaddr addr, unsigned size)
664 {
665 GT64120State *s = opaque;
666 PCIHostState *phb = PCI_HOST_BRIDGE(s);
667 uint32_t val;
668 uint32_t saddr;
669
670 saddr = (addr & 0xfff) >> 2;
671 switch (saddr) {
672
673 /* CPU Configuration */
674 case GT_MULTI:
675 /* Only one GT64xxx is present on the CPU bus, return
676 the initial value */
677 val = s->regs[saddr];
678 break;
679
680 /* CPU Error Report */
681 case GT_CPUERR_ADDRLO:
682 case GT_CPUERR_ADDRHI:
683 case GT_CPUERR_DATALO:
684 case GT_CPUERR_DATAHI:
685 case GT_CPUERR_PARITY:
686 /* Emulated memory has no error, always return the initial
687 values */
688 val = s->regs[saddr];
689 break;
690
691 /* CPU Sync Barrier */
692 case GT_PCI0SYNC:
693 case GT_PCI1SYNC:
694 /* Reading those register should empty all FIFO on the PCI
695 bus, which are not emulated. The return value should be
696 a random value that should be ignored. */
697 val = 0xc000ffee;
698 break;
699
700 /* ECC */
701 case GT_ECC_ERRDATALO:
702 case GT_ECC_ERRDATAHI:
703 case GT_ECC_MEM:
704 case GT_ECC_CALC:
705 case GT_ECC_ERRADDR:
706 /* Emulated memory has no error, always return the initial
707 values */
708 val = s->regs[saddr];
709 break;
710
711 case GT_CPU:
712 case GT_SCS10LD:
713 case GT_SCS10HD:
714 case GT_SCS32LD:
715 case GT_SCS32HD:
716 case GT_CS20LD:
717 case GT_CS20HD:
718 case GT_CS3BOOTLD:
719 case GT_CS3BOOTHD:
720 case GT_SCS10AR:
721 case GT_SCS32AR:
722 case GT_CS20R:
723 case GT_CS3BOOTR:
724 case GT_PCI0IOLD:
725 case GT_PCI0M0LD:
726 case GT_PCI0M1LD:
727 case GT_PCI1IOLD:
728 case GT_PCI1M0LD:
729 case GT_PCI1M1LD:
730 case GT_PCI0IOHD:
731 case GT_PCI0M0HD:
732 case GT_PCI0M1HD:
733 case GT_PCI1IOHD:
734 case GT_PCI1M0HD:
735 case GT_PCI1M1HD:
736 case GT_PCI0IOREMAP:
737 case GT_PCI0M0REMAP:
738 case GT_PCI0M1REMAP:
739 case GT_PCI1IOREMAP:
740 case GT_PCI1M0REMAP:
741 case GT_PCI1M1REMAP:
742 case GT_ISD:
743 val = s->regs[saddr];
744 break;
745 case GT_PCI0_IACK:
746 /* Read the IRQ number */
747 val = pic_read_irq(isa_pic);
748 break;
749
750 /* SDRAM and Device Address Decode */
751 case GT_SCS0LD:
752 case GT_SCS0HD:
753 case GT_SCS1LD:
754 case GT_SCS1HD:
755 case GT_SCS2LD:
756 case GT_SCS2HD:
757 case GT_SCS3LD:
758 case GT_SCS3HD:
759 case GT_CS0LD:
760 case GT_CS0HD:
761 case GT_CS1LD:
762 case GT_CS1HD:
763 case GT_CS2LD:
764 case GT_CS2HD:
765 case GT_CS3LD:
766 case GT_CS3HD:
767 case GT_BOOTLD:
768 case GT_BOOTHD:
769 case GT_ADERR:
770 val = s->regs[saddr];
771 break;
772
773 /* SDRAM Configuration */
774 case GT_SDRAM_CFG:
775 case GT_SDRAM_OPMODE:
776 case GT_SDRAM_BM:
777 case GT_SDRAM_ADDRDECODE:
778 val = s->regs[saddr];
779 break;
780
781 /* SDRAM Parameters */
782 case GT_SDRAM_B0:
783 case GT_SDRAM_B1:
784 case GT_SDRAM_B2:
785 case GT_SDRAM_B3:
786 /* We don't simulate electrical parameters of the SDRAM.
787 Just return the last written value. */
788 val = s->regs[saddr];
789 break;
790
791 /* Device Parameters */
792 case GT_DEV_B0:
793 case GT_DEV_B1:
794 case GT_DEV_B2:
795 case GT_DEV_B3:
796 case GT_DEV_BOOT:
797 val = s->regs[saddr];
798 break;
799
800 /* DMA Record */
801 case GT_DMA0_CNT:
802 case GT_DMA1_CNT:
803 case GT_DMA2_CNT:
804 case GT_DMA3_CNT:
805 case GT_DMA0_SA:
806 case GT_DMA1_SA:
807 case GT_DMA2_SA:
808 case GT_DMA3_SA:
809 case GT_DMA0_DA:
810 case GT_DMA1_DA:
811 case GT_DMA2_DA:
812 case GT_DMA3_DA:
813 case GT_DMA0_NEXT:
814 case GT_DMA1_NEXT:
815 case GT_DMA2_NEXT:
816 case GT_DMA3_NEXT:
817 case GT_DMA0_CUR:
818 case GT_DMA1_CUR:
819 case GT_DMA2_CUR:
820 case GT_DMA3_CUR:
821 val = s->regs[saddr];
822 break;
823
824 /* DMA Channel Control */
825 case GT_DMA0_CTRL:
826 case GT_DMA1_CTRL:
827 case GT_DMA2_CTRL:
828 case GT_DMA3_CTRL:
829 val = s->regs[saddr];
830 break;
831
832 /* DMA Arbiter */
833 case GT_DMA_ARB:
834 val = s->regs[saddr];
835 break;
836
837 /* Timer/Counter */
838 case GT_TC0:
839 case GT_TC1:
840 case GT_TC2:
841 case GT_TC3:
842 case GT_TC_CONTROL:
843 val = s->regs[saddr];
844 break;
845
846 /* PCI Internal */
847 case GT_PCI0_CFGADDR:
848 val = phb->config_reg;
849 break;
850 case GT_PCI0_CFGDATA:
851 if (!(phb->config_reg & (1 << 31))) {
852 val = 0xffffffff;
853 } else {
854 val = pci_data_read(phb->bus, phb->config_reg, 4);
855 }
856 if (!(s->regs[GT_PCI0_CMD] & 1) && (phb->config_reg & 0x00fff800)) {
857 val = bswap32(val);
858 }
859 break;
860
861 case GT_PCI0_CMD:
862 case GT_PCI0_TOR:
863 case GT_PCI0_BS_SCS10:
864 case GT_PCI0_BS_SCS32:
865 case GT_PCI0_BS_CS20:
866 case GT_PCI0_BS_CS3BT:
867 case GT_PCI1_IACK:
868 case GT_PCI0_BARE:
869 case GT_PCI0_PREFMBR:
870 case GT_PCI0_SCS10_BAR:
871 case GT_PCI0_SCS32_BAR:
872 case GT_PCI0_CS20_BAR:
873 case GT_PCI0_CS3BT_BAR:
874 case GT_PCI0_SSCS10_BAR:
875 case GT_PCI0_SSCS32_BAR:
876 case GT_PCI0_SCS3BT_BAR:
877 case GT_PCI1_CMD:
878 case GT_PCI1_TOR:
879 case GT_PCI1_BS_SCS10:
880 case GT_PCI1_BS_SCS32:
881 case GT_PCI1_BS_CS20:
882 case GT_PCI1_BS_CS3BT:
883 case GT_PCI1_BARE:
884 case GT_PCI1_PREFMBR:
885 case GT_PCI1_SCS10_BAR:
886 case GT_PCI1_SCS32_BAR:
887 case GT_PCI1_CS20_BAR:
888 case GT_PCI1_CS3BT_BAR:
889 case GT_PCI1_SSCS10_BAR:
890 case GT_PCI1_SSCS32_BAR:
891 case GT_PCI1_SCS3BT_BAR:
892 case GT_PCI1_CFGADDR:
893 case GT_PCI1_CFGDATA:
894 val = s->regs[saddr];
895 break;
896
897 /* Interrupts */
898 case GT_INTRCAUSE:
899 val = s->regs[saddr];
900 DPRINTF("INTRCAUSE %x\n", val);
901 break;
902 case GT_INTRMASK:
903 val = s->regs[saddr];
904 DPRINTF("INTRMASK %x\n", val);
905 break;
906 case GT_PCI0_ICMASK:
907 val = s->regs[saddr];
908 DPRINTF("ICMASK %x\n", val);
909 break;
910 case GT_PCI0_SERR0MASK:
911 val = s->regs[saddr];
912 DPRINTF("SERR0MASK %x\n", val);
913 break;
914
915 /* Reserved when only PCI_0 is configured. */
916 case GT_HINTRCAUSE:
917 case GT_CPU_INTSEL:
918 case GT_PCI0_INTSEL:
919 case GT_HINTRMASK:
920 case GT_PCI0_HICMASK:
921 case GT_PCI1_SERR1MASK:
922 val = s->regs[saddr];
923 break;
924
925 default:
926 val = s->regs[saddr];
927 DPRINTF ("Bad register offset 0x%x\n", (int)addr);
928 break;
929 }
930
931 if (!(s->regs[GT_CPU] & 0x00001000))
932 val = bswap32(val);
933
934 return val;
935 }
936
937 static const MemoryRegionOps isd_mem_ops = {
938 .read = gt64120_readl,
939 .write = gt64120_writel,
940 .endianness = DEVICE_NATIVE_ENDIAN,
941 };
942
943 static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
944 {
945 int slot;
946
947 slot = (pci_dev->devfn >> 3);
948
949 switch (slot) {
950 /* PIIX4 USB */
951 case 10:
952 return 3;
953 /* AMD 79C973 Ethernet */
954 case 11:
955 return 1;
956 /* Crystal 4281 Sound */
957 case 12:
958 return 2;
959 /* PCI slot 1 to 4 */
960 case 18 ... 21:
961 return ((slot - 18) + irq_num) & 0x03;
962 /* Unknown device, don't do any translation */
963 default:
964 return irq_num;
965 }
966 }
967
968 static int pci_irq_levels[4];
969
970 static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
971 {
972 int i, pic_irq, pic_level;
973 qemu_irq *pic = opaque;
974
975 pci_irq_levels[irq_num] = level;
976
977 /* now we change the pic irq level according to the piix irq mappings */
978 /* XXX: optimize */
979 pic_irq = piix4_dev->config[0x60 + irq_num];
980 if (pic_irq < 16) {
981 /* The pic level is the logical OR of all the PCI irqs mapped
982 to it */
983 pic_level = 0;
984 for (i = 0; i < 4; i++) {
985 if (pic_irq == piix4_dev->config[0x60 + i])
986 pic_level |= pci_irq_levels[i];
987 }
988 qemu_set_irq(pic[pic_irq], pic_level);
989 }
990 }
991
992
993 static void gt64120_reset(void *opaque)
994 {
995 GT64120State *s = opaque;
996
997 /* FIXME: Malta specific hw assumptions ahead */
998
999 /* CPU Configuration */
1000 #ifdef TARGET_WORDS_BIGENDIAN
1001 s->regs[GT_CPU] = 0x00000000;
1002 #else
1003 s->regs[GT_CPU] = 0x00001000;
1004 #endif
1005 s->regs[GT_MULTI] = 0x00000003;
1006
1007 /* CPU Address decode */
1008 s->regs[GT_SCS10LD] = 0x00000000;
1009 s->regs[GT_SCS10HD] = 0x00000007;
1010 s->regs[GT_SCS32LD] = 0x00000008;
1011 s->regs[GT_SCS32HD] = 0x0000000f;
1012 s->regs[GT_CS20LD] = 0x000000e0;
1013 s->regs[GT_CS20HD] = 0x00000070;
1014 s->regs[GT_CS3BOOTLD] = 0x000000f8;
1015 s->regs[GT_CS3BOOTHD] = 0x0000007f;
1016
1017 s->regs[GT_PCI0IOLD] = 0x00000080;
1018 s->regs[GT_PCI0IOHD] = 0x0000000f;
1019 s->regs[GT_PCI0M0LD] = 0x00000090;
1020 s->regs[GT_PCI0M0HD] = 0x0000001f;
1021 s->regs[GT_ISD] = 0x000000a0;
1022 s->regs[GT_PCI0M1LD] = 0x00000790;
1023 s->regs[GT_PCI0M1HD] = 0x0000001f;
1024 s->regs[GT_PCI1IOLD] = 0x00000100;
1025 s->regs[GT_PCI1IOHD] = 0x0000000f;
1026 s->regs[GT_PCI1M0LD] = 0x00000110;
1027 s->regs[GT_PCI1M0HD] = 0x0000001f;
1028 s->regs[GT_PCI1M1LD] = 0x00000120;
1029 s->regs[GT_PCI1M1HD] = 0x0000002f;
1030
1031 s->regs[GT_SCS10AR] = 0x00000000;
1032 s->regs[GT_SCS32AR] = 0x00000008;
1033 s->regs[GT_CS20R] = 0x000000e0;
1034 s->regs[GT_CS3BOOTR] = 0x000000f8;
1035
1036 s->regs[GT_PCI0IOREMAP] = 0x00000080;
1037 s->regs[GT_PCI0M0REMAP] = 0x00000090;
1038 s->regs[GT_PCI0M1REMAP] = 0x00000790;
1039 s->regs[GT_PCI1IOREMAP] = 0x00000100;
1040 s->regs[GT_PCI1M0REMAP] = 0x00000110;
1041 s->regs[GT_PCI1M1REMAP] = 0x00000120;
1042
1043 /* CPU Error Report */
1044 s->regs[GT_CPUERR_ADDRLO] = 0x00000000;
1045 s->regs[GT_CPUERR_ADDRHI] = 0x00000000;
1046 s->regs[GT_CPUERR_DATALO] = 0xffffffff;
1047 s->regs[GT_CPUERR_DATAHI] = 0xffffffff;
1048 s->regs[GT_CPUERR_PARITY] = 0x000000ff;
1049
1050 /* CPU Sync Barrier */
1051 s->regs[GT_PCI0SYNC] = 0x00000000;
1052 s->regs[GT_PCI1SYNC] = 0x00000000;
1053
1054 /* SDRAM and Device Address Decode */
1055 s->regs[GT_SCS0LD] = 0x00000000;
1056 s->regs[GT_SCS0HD] = 0x00000007;
1057 s->regs[GT_SCS1LD] = 0x00000008;
1058 s->regs[GT_SCS1HD] = 0x0000000f;
1059 s->regs[GT_SCS2LD] = 0x00000010;
1060 s->regs[GT_SCS2HD] = 0x00000017;
1061 s->regs[GT_SCS3LD] = 0x00000018;
1062 s->regs[GT_SCS3HD] = 0x0000001f;
1063 s->regs[GT_CS0LD] = 0x000000c0;
1064 s->regs[GT_CS0HD] = 0x000000c7;
1065 s->regs[GT_CS1LD] = 0x000000c8;
1066 s->regs[GT_CS1HD] = 0x000000cf;
1067 s->regs[GT_CS2LD] = 0x000000d0;
1068 s->regs[GT_CS2HD] = 0x000000df;
1069 s->regs[GT_CS3LD] = 0x000000f0;
1070 s->regs[GT_CS3HD] = 0x000000fb;
1071 s->regs[GT_BOOTLD] = 0x000000fc;
1072 s->regs[GT_BOOTHD] = 0x000000ff;
1073 s->regs[GT_ADERR] = 0xffffffff;
1074
1075 /* SDRAM Configuration */
1076 s->regs[GT_SDRAM_CFG] = 0x00000200;
1077 s->regs[GT_SDRAM_OPMODE] = 0x00000000;
1078 s->regs[GT_SDRAM_BM] = 0x00000007;
1079 s->regs[GT_SDRAM_ADDRDECODE] = 0x00000002;
1080
1081 /* SDRAM Parameters */
1082 s->regs[GT_SDRAM_B0] = 0x00000005;
1083 s->regs[GT_SDRAM_B1] = 0x00000005;
1084 s->regs[GT_SDRAM_B2] = 0x00000005;
1085 s->regs[GT_SDRAM_B3] = 0x00000005;
1086
1087 /* ECC */
1088 s->regs[GT_ECC_ERRDATALO] = 0x00000000;
1089 s->regs[GT_ECC_ERRDATAHI] = 0x00000000;
1090 s->regs[GT_ECC_MEM] = 0x00000000;
1091 s->regs[GT_ECC_CALC] = 0x00000000;
1092 s->regs[GT_ECC_ERRADDR] = 0x00000000;
1093
1094 /* Device Parameters */
1095 s->regs[GT_DEV_B0] = 0x386fffff;
1096 s->regs[GT_DEV_B1] = 0x386fffff;
1097 s->regs[GT_DEV_B2] = 0x386fffff;
1098 s->regs[GT_DEV_B3] = 0x386fffff;
1099 s->regs[GT_DEV_BOOT] = 0x146fffff;
1100
1101 /* DMA registers are all zeroed at reset */
1102
1103 /* Timer/Counter */
1104 s->regs[GT_TC0] = 0xffffffff;
1105 s->regs[GT_TC1] = 0x00ffffff;
1106 s->regs[GT_TC2] = 0x00ffffff;
1107 s->regs[GT_TC3] = 0x00ffffff;
1108 s->regs[GT_TC_CONTROL] = 0x00000000;
1109
1110 /* PCI Internal */
1111 #ifdef TARGET_WORDS_BIGENDIAN
1112 s->regs[GT_PCI0_CMD] = 0x00000000;
1113 #else
1114 s->regs[GT_PCI0_CMD] = 0x00010001;
1115 #endif
1116 s->regs[GT_PCI0_TOR] = 0x0000070f;
1117 s->regs[GT_PCI0_BS_SCS10] = 0x00fff000;
1118 s->regs[GT_PCI0_BS_SCS32] = 0x00fff000;
1119 s->regs[GT_PCI0_BS_CS20] = 0x01fff000;
1120 s->regs[GT_PCI0_BS_CS3BT] = 0x00fff000;
1121 s->regs[GT_PCI1_IACK] = 0x00000000;
1122 s->regs[GT_PCI0_IACK] = 0x00000000;
1123 s->regs[GT_PCI0_BARE] = 0x0000000f;
1124 s->regs[GT_PCI0_PREFMBR] = 0x00000040;
1125 s->regs[GT_PCI0_SCS10_BAR] = 0x00000000;
1126 s->regs[GT_PCI0_SCS32_BAR] = 0x01000000;
1127 s->regs[GT_PCI0_CS20_BAR] = 0x1c000000;
1128 s->regs[GT_PCI0_CS3BT_BAR] = 0x1f000000;
1129 s->regs[GT_PCI0_SSCS10_BAR] = 0x00000000;
1130 s->regs[GT_PCI0_SSCS32_BAR] = 0x01000000;
1131 s->regs[GT_PCI0_SCS3BT_BAR] = 0x1f000000;
1132 #ifdef TARGET_WORDS_BIGENDIAN
1133 s->regs[GT_PCI1_CMD] = 0x00000000;
1134 #else
1135 s->regs[GT_PCI1_CMD] = 0x00010001;
1136 #endif
1137 s->regs[GT_PCI1_TOR] = 0x0000070f;
1138 s->regs[GT_PCI1_BS_SCS10] = 0x00fff000;
1139 s->regs[GT_PCI1_BS_SCS32] = 0x00fff000;
1140 s->regs[GT_PCI1_BS_CS20] = 0x01fff000;
1141 s->regs[GT_PCI1_BS_CS3BT] = 0x00fff000;
1142 s->regs[GT_PCI1_BARE] = 0x0000000f;
1143 s->regs[GT_PCI1_PREFMBR] = 0x00000040;
1144 s->regs[GT_PCI1_SCS10_BAR] = 0x00000000;
1145 s->regs[GT_PCI1_SCS32_BAR] = 0x01000000;
1146 s->regs[GT_PCI1_CS20_BAR] = 0x1c000000;
1147 s->regs[GT_PCI1_CS3BT_BAR] = 0x1f000000;
1148 s->regs[GT_PCI1_SSCS10_BAR] = 0x00000000;
1149 s->regs[GT_PCI1_SSCS32_BAR] = 0x01000000;
1150 s->regs[GT_PCI1_SCS3BT_BAR] = 0x1f000000;
1151 s->regs[GT_PCI1_CFGADDR] = 0x00000000;
1152 s->regs[GT_PCI1_CFGDATA] = 0x00000000;
1153 s->regs[GT_PCI0_CFGADDR] = 0x00000000;
1154
1155 /* Interrupt registers are all zeroed at reset */
1156
1157 gt64120_isd_mapping(s);
1158 gt64120_pci_mapping(s);
1159 }
1160
1161 PCIBus *gt64120_register(qemu_irq *pic)
1162 {
1163 GT64120State *d;
1164 PCIHostState *phb;
1165 DeviceState *dev;
1166
1167 dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);
1168 qdev_init_nofail(dev);
1169 d = GT64120_PCI_HOST_BRIDGE(dev);
1170 phb = PCI_HOST_BRIDGE(dev);
1171 memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", UINT32_MAX);
1172 address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");
1173 phb->bus = pci_register_bus(dev, "pci",
1174 gt64120_pci_set_irq, gt64120_pci_map_irq,
1175 pic,
1176 &d->pci0_mem,
1177 get_system_io(),
1178 PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
1179 memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d, "isd-mem", 0x1000);
1180
1181 pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
1182 return phb->bus;
1183 }
1184
1185 static int gt64120_init(SysBusDevice *dev)
1186 {
1187 GT64120State *s;
1188
1189 s = GT64120_PCI_HOST_BRIDGE(dev);
1190
1191 qemu_register_reset(gt64120_reset, s);
1192 return 0;
1193 }
1194
1195 static int gt64120_pci_init(PCIDevice *d)
1196 {
1197 /* FIXME: Malta specific hw assumptions ahead */
1198 pci_set_word(d->config + PCI_COMMAND, 0);
1199 pci_set_word(d->config + PCI_STATUS,
1200 PCI_STATUS_FAST_BACK | PCI_STATUS_DEVSEL_MEDIUM);
1201 pci_config_set_prog_interface(d->config, 0);
1202 pci_set_long(d->config + PCI_BASE_ADDRESS_0, 0x00000008);
1203 pci_set_long(d->config + PCI_BASE_ADDRESS_1, 0x01000008);
1204 pci_set_long(d->config + PCI_BASE_ADDRESS_2, 0x1c000000);
1205 pci_set_long(d->config + PCI_BASE_ADDRESS_3, 0x1f000000);
1206 pci_set_long(d->config + PCI_BASE_ADDRESS_4, 0x14000000);
1207 pci_set_long(d->config + PCI_BASE_ADDRESS_5, 0x14000001);
1208 pci_set_byte(d->config + 0x3d, 0x01);
1209
1210 return 0;
1211 }
1212
1213 static void gt64120_pci_class_init(ObjectClass *klass, void *data)
1214 {
1215 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1216 DeviceClass *dc = DEVICE_CLASS(klass);
1217
1218 k->init = gt64120_pci_init;
1219 k->vendor_id = PCI_VENDOR_ID_MARVELL;
1220 k->device_id = PCI_DEVICE_ID_MARVELL_GT6412X;
1221 k->revision = 0x10;
1222 k->class_id = PCI_CLASS_BRIDGE_HOST;
1223 /*
1224 * PCI-facing part of the host bridge, not usable without the
1225 * host-facing part, which can't be device_add'ed, yet.
1226 */
1227 dc->cannot_instantiate_with_device_add_yet = true;
1228 }
1229
1230 static const TypeInfo gt64120_pci_info = {
1231 .name = "gt64120_pci",
1232 .parent = TYPE_PCI_DEVICE,
1233 .instance_size = sizeof(PCIDevice),
1234 .class_init = gt64120_pci_class_init,
1235 };
1236
1237 static void gt64120_class_init(ObjectClass *klass, void *data)
1238 {
1239 DeviceClass *dc = DEVICE_CLASS(klass);
1240 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
1241
1242 sdc->init = gt64120_init;
1243 dc->vmsd = &vmstate_gt64120;
1244 }
1245
1246 static const TypeInfo gt64120_info = {
1247 .name = TYPE_GT64120_PCI_HOST_BRIDGE,
1248 .parent = TYPE_PCI_HOST_BRIDGE,
1249 .instance_size = sizeof(GT64120State),
1250 .class_init = gt64120_class_init,
1251 };
1252
1253 static void gt64120_pci_register_types(void)
1254 {
1255 type_register_static(&gt64120_info);
1256 type_register_static(&gt64120_pci_info);
1257 }
1258
1259 type_init(gt64120_pci_register_types)
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