2 * QEMU GT64120 PCI host
4 * Copyright (c) 2006,2007 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
28 #include "hw/mips/mips.h"
29 #include "hw/pci/pci.h"
30 #include "hw/pci/pci_host.h"
31 #include "hw/southbridge/piix.h"
32 #include "migration/vmstate.h"
33 #include "hw/intc/i8259.h"
35 #include "exec/address-spaces.h"
38 #define GT_REGS (0x1000 >> 2)
40 /* CPU Configuration */
41 #define GT_CPU (0x000 >> 2)
42 #define GT_MULTI (0x120 >> 2)
44 /* CPU Address Decode */
45 #define GT_SCS10LD (0x008 >> 2)
46 #define GT_SCS10HD (0x010 >> 2)
47 #define GT_SCS32LD (0x018 >> 2)
48 #define GT_SCS32HD (0x020 >> 2)
49 #define GT_CS20LD (0x028 >> 2)
50 #define GT_CS20HD (0x030 >> 2)
51 #define GT_CS3BOOTLD (0x038 >> 2)
52 #define GT_CS3BOOTHD (0x040 >> 2)
53 #define GT_PCI0IOLD (0x048 >> 2)
54 #define GT_PCI0IOHD (0x050 >> 2)
55 #define GT_PCI0M0LD (0x058 >> 2)
56 #define GT_PCI0M0HD (0x060 >> 2)
57 #define GT_PCI0M1LD (0x080 >> 2)
58 #define GT_PCI0M1HD (0x088 >> 2)
59 #define GT_PCI1IOLD (0x090 >> 2)
60 #define GT_PCI1IOHD (0x098 >> 2)
61 #define GT_PCI1M0LD (0x0a0 >> 2)
62 #define GT_PCI1M0HD (0x0a8 >> 2)
63 #define GT_PCI1M1LD (0x0b0 >> 2)
64 #define GT_PCI1M1HD (0x0b8 >> 2)
65 #define GT_ISD (0x068 >> 2)
67 #define GT_SCS10AR (0x0d0 >> 2)
68 #define GT_SCS32AR (0x0d8 >> 2)
69 #define GT_CS20R (0x0e0 >> 2)
70 #define GT_CS3BOOTR (0x0e8 >> 2)
72 #define GT_PCI0IOREMAP (0x0f0 >> 2)
73 #define GT_PCI0M0REMAP (0x0f8 >> 2)
74 #define GT_PCI0M1REMAP (0x100 >> 2)
75 #define GT_PCI1IOREMAP (0x108 >> 2)
76 #define GT_PCI1M0REMAP (0x110 >> 2)
77 #define GT_PCI1M1REMAP (0x118 >> 2)
79 /* CPU Error Report */
80 #define GT_CPUERR_ADDRLO (0x070 >> 2)
81 #define GT_CPUERR_ADDRHI (0x078 >> 2)
82 #define GT_CPUERR_DATALO (0x128 >> 2) /* GT-64120A only */
83 #define GT_CPUERR_DATAHI (0x130 >> 2) /* GT-64120A only */
84 #define GT_CPUERR_PARITY (0x138 >> 2) /* GT-64120A only */
86 /* CPU Sync Barrier */
87 #define GT_PCI0SYNC (0x0c0 >> 2)
88 #define GT_PCI1SYNC (0x0c8 >> 2)
90 /* SDRAM and Device Address Decode */
91 #define GT_SCS0LD (0x400 >> 2)
92 #define GT_SCS0HD (0x404 >> 2)
93 #define GT_SCS1LD (0x408 >> 2)
94 #define GT_SCS1HD (0x40c >> 2)
95 #define GT_SCS2LD (0x410 >> 2)
96 #define GT_SCS2HD (0x414 >> 2)
97 #define GT_SCS3LD (0x418 >> 2)
98 #define GT_SCS3HD (0x41c >> 2)
99 #define GT_CS0LD (0x420 >> 2)
100 #define GT_CS0HD (0x424 >> 2)
101 #define GT_CS1LD (0x428 >> 2)
102 #define GT_CS1HD (0x42c >> 2)
103 #define GT_CS2LD (0x430 >> 2)
104 #define GT_CS2HD (0x434 >> 2)
105 #define GT_CS3LD (0x438 >> 2)
106 #define GT_CS3HD (0x43c >> 2)
107 #define GT_BOOTLD (0x440 >> 2)
108 #define GT_BOOTHD (0x444 >> 2)
109 #define GT_ADERR (0x470 >> 2)
111 /* SDRAM Configuration */
112 #define GT_SDRAM_CFG (0x448 >> 2)
113 #define GT_SDRAM_OPMODE (0x474 >> 2)
114 #define GT_SDRAM_BM (0x478 >> 2)
115 #define GT_SDRAM_ADDRDECODE (0x47c >> 2)
117 /* SDRAM Parameters */
118 #define GT_SDRAM_B0 (0x44c >> 2)
119 #define GT_SDRAM_B1 (0x450 >> 2)
120 #define GT_SDRAM_B2 (0x454 >> 2)
121 #define GT_SDRAM_B3 (0x458 >> 2)
123 /* Device Parameters */
124 #define GT_DEV_B0 (0x45c >> 2)
125 #define GT_DEV_B1 (0x460 >> 2)
126 #define GT_DEV_B2 (0x464 >> 2)
127 #define GT_DEV_B3 (0x468 >> 2)
128 #define GT_DEV_BOOT (0x46c >> 2)
131 #define GT_ECC_ERRDATALO (0x480 >> 2) /* GT-64120A only */
132 #define GT_ECC_ERRDATAHI (0x484 >> 2) /* GT-64120A only */
133 #define GT_ECC_MEM (0x488 >> 2) /* GT-64120A only */
134 #define GT_ECC_CALC (0x48c >> 2) /* GT-64120A only */
135 #define GT_ECC_ERRADDR (0x490 >> 2) /* GT-64120A only */
138 #define GT_DMA0_CNT (0x800 >> 2)
139 #define GT_DMA1_CNT (0x804 >> 2)
140 #define GT_DMA2_CNT (0x808 >> 2)
141 #define GT_DMA3_CNT (0x80c >> 2)
142 #define GT_DMA0_SA (0x810 >> 2)
143 #define GT_DMA1_SA (0x814 >> 2)
144 #define GT_DMA2_SA (0x818 >> 2)
145 #define GT_DMA3_SA (0x81c >> 2)
146 #define GT_DMA0_DA (0x820 >> 2)
147 #define GT_DMA1_DA (0x824 >> 2)
148 #define GT_DMA2_DA (0x828 >> 2)
149 #define GT_DMA3_DA (0x82c >> 2)
150 #define GT_DMA0_NEXT (0x830 >> 2)
151 #define GT_DMA1_NEXT (0x834 >> 2)
152 #define GT_DMA2_NEXT (0x838 >> 2)
153 #define GT_DMA3_NEXT (0x83c >> 2)
154 #define GT_DMA0_CUR (0x870 >> 2)
155 #define GT_DMA1_CUR (0x874 >> 2)
156 #define GT_DMA2_CUR (0x878 >> 2)
157 #define GT_DMA3_CUR (0x87c >> 2)
159 /* DMA Channel Control */
160 #define GT_DMA0_CTRL (0x840 >> 2)
161 #define GT_DMA1_CTRL (0x844 >> 2)
162 #define GT_DMA2_CTRL (0x848 >> 2)
163 #define GT_DMA3_CTRL (0x84c >> 2)
166 #define GT_DMA_ARB (0x860 >> 2)
169 #define GT_TC0 (0x850 >> 2)
170 #define GT_TC1 (0x854 >> 2)
171 #define GT_TC2 (0x858 >> 2)
172 #define GT_TC3 (0x85c >> 2)
173 #define GT_TC_CONTROL (0x864 >> 2)
176 #define GT_PCI0_CMD (0xc00 >> 2)
177 #define GT_PCI0_TOR (0xc04 >> 2)
178 #define GT_PCI0_BS_SCS10 (0xc08 >> 2)
179 #define GT_PCI0_BS_SCS32 (0xc0c >> 2)
180 #define GT_PCI0_BS_CS20 (0xc10 >> 2)
181 #define GT_PCI0_BS_CS3BT (0xc14 >> 2)
182 #define GT_PCI1_IACK (0xc30 >> 2)
183 #define GT_PCI0_IACK (0xc34 >> 2)
184 #define GT_PCI0_BARE (0xc3c >> 2)
185 #define GT_PCI0_PREFMBR (0xc40 >> 2)
186 #define GT_PCI0_SCS10_BAR (0xc48 >> 2)
187 #define GT_PCI0_SCS32_BAR (0xc4c >> 2)
188 #define GT_PCI0_CS20_BAR (0xc50 >> 2)
189 #define GT_PCI0_CS3BT_BAR (0xc54 >> 2)
190 #define GT_PCI0_SSCS10_BAR (0xc58 >> 2)
191 #define GT_PCI0_SSCS32_BAR (0xc5c >> 2)
192 #define GT_PCI0_SCS3BT_BAR (0xc64 >> 2)
193 #define GT_PCI1_CMD (0xc80 >> 2)
194 #define GT_PCI1_TOR (0xc84 >> 2)
195 #define GT_PCI1_BS_SCS10 (0xc88 >> 2)
196 #define GT_PCI1_BS_SCS32 (0xc8c >> 2)
197 #define GT_PCI1_BS_CS20 (0xc90 >> 2)
198 #define GT_PCI1_BS_CS3BT (0xc94 >> 2)
199 #define GT_PCI1_BARE (0xcbc >> 2)
200 #define GT_PCI1_PREFMBR (0xcc0 >> 2)
201 #define GT_PCI1_SCS10_BAR (0xcc8 >> 2)
202 #define GT_PCI1_SCS32_BAR (0xccc >> 2)
203 #define GT_PCI1_CS20_BAR (0xcd0 >> 2)
204 #define GT_PCI1_CS3BT_BAR (0xcd4 >> 2)
205 #define GT_PCI1_SSCS10_BAR (0xcd8 >> 2)
206 #define GT_PCI1_SSCS32_BAR (0xcdc >> 2)
207 #define GT_PCI1_SCS3BT_BAR (0xce4 >> 2)
208 #define GT_PCI1_CFGADDR (0xcf0 >> 2)
209 #define GT_PCI1_CFGDATA (0xcf4 >> 2)
210 #define GT_PCI0_CFGADDR (0xcf8 >> 2)
211 #define GT_PCI0_CFGDATA (0xcfc >> 2)
214 #define GT_INTRCAUSE (0xc18 >> 2)
215 #define GT_INTRMASK (0xc1c >> 2)
216 #define GT_PCI0_ICMASK (0xc24 >> 2)
217 #define GT_PCI0_SERR0MASK (0xc28 >> 2)
218 #define GT_CPU_INTSEL (0xc70 >> 2)
219 #define GT_PCI0_INTSEL (0xc74 >> 2)
220 #define GT_HINTRCAUSE (0xc98 >> 2)
221 #define GT_HINTRMASK (0xc9c >> 2)
222 #define GT_PCI0_HICMASK (0xca4 >> 2)
223 #define GT_PCI1_SERR1MASK (0xca8 >> 2)
225 #define PCI_MAPPING_ENTRY(regname) \
226 hwaddr regname ##_start; \
227 hwaddr regname ##_length; \
228 MemoryRegion regname ##_mem
230 #define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120"
232 #define GT64120_PCI_HOST_BRIDGE(obj) \
233 OBJECT_CHECK(GT64120State, (obj), TYPE_GT64120_PCI_HOST_BRIDGE)
235 typedef struct GT64120State
{
236 PCIHostState parent_obj
;
238 uint32_t regs
[GT_REGS
];
239 PCI_MAPPING_ENTRY(PCI0IO
);
240 PCI_MAPPING_ENTRY(PCI0M0
);
241 PCI_MAPPING_ENTRY(PCI0M1
);
242 PCI_MAPPING_ENTRY(ISD
);
243 MemoryRegion pci0_mem
;
244 AddressSpace pci0_mem_as
;
247 /* Adjust range to avoid touching space which isn't mappable via PCI */
249 * XXX: Hardcoded values for Malta: 0x1e000000 - 0x1f100000
250 * 0x1fc00000 - 0x1fd00000
252 static void check_reserved_space(hwaddr
*start
, hwaddr
*length
)
254 hwaddr begin
= *start
;
255 hwaddr end
= *start
+ *length
;
257 if (end
>= 0x1e000000LL
&& end
< 0x1f100000LL
) {
260 if (begin
>= 0x1e000000LL
&& begin
< 0x1f100000LL
) {
261 begin
= 0x1f100000LL
;
263 if (end
>= 0x1fc00000LL
&& end
< 0x1fd00000LL
) {
266 if (begin
>= 0x1fc00000LL
&& begin
< 0x1fd00000LL
) {
267 begin
= 0x1fd00000LL
;
269 /* XXX: This is broken when a reserved range splits the requested range */
270 if (end
>= 0x1f100000LL
&& begin
< 0x1e000000LL
) {
273 if (end
>= 0x1fd00000LL
&& begin
< 0x1fc00000LL
) {
278 *length
= end
- begin
;
281 static void gt64120_isd_mapping(GT64120State
*s
)
283 /* Bits 14:0 of ISD map to bits 35:21 of the start address. */
284 hwaddr start
= ((hwaddr
)s
->regs
[GT_ISD
] << 21) & 0xFFFE00000ull
;
285 hwaddr length
= 0x1000;
288 memory_region_del_subregion(get_system_memory(), &s
->ISD_mem
);
290 check_reserved_space(&start
, &length
);
292 /* Map new address */
293 trace_gt64120_isd_remap(s
->ISD_length
, s
->ISD_start
, length
, start
);
294 s
->ISD_start
= start
;
295 s
->ISD_length
= length
;
296 memory_region_add_subregion(get_system_memory(), s
->ISD_start
, &s
->ISD_mem
);
299 static void gt64120_pci_mapping(GT64120State
*s
)
301 /* Update PCI0IO mapping */
302 if ((s
->regs
[GT_PCI0IOLD
] & 0x7f) <= s
->regs
[GT_PCI0IOHD
]) {
303 /* Unmap old IO address */
304 if (s
->PCI0IO_length
) {
305 memory_region_del_subregion(get_system_memory(), &s
->PCI0IO_mem
);
306 object_unparent(OBJECT(&s
->PCI0IO_mem
));
308 /* Map new IO address */
309 s
->PCI0IO_start
= s
->regs
[GT_PCI0IOLD
] << 21;
310 s
->PCI0IO_length
= ((s
->regs
[GT_PCI0IOHD
] + 1) -
311 (s
->regs
[GT_PCI0IOLD
] & 0x7f)) << 21;
312 if (s
->PCI0IO_length
) {
313 memory_region_init_alias(&s
->PCI0IO_mem
, OBJECT(s
), "pci0-io",
314 get_system_io(), 0, s
->PCI0IO_length
);
315 memory_region_add_subregion(get_system_memory(), s
->PCI0IO_start
,
320 /* Update PCI0M0 mapping */
321 if ((s
->regs
[GT_PCI0M0LD
] & 0x7f) <= s
->regs
[GT_PCI0M0HD
]) {
322 /* Unmap old MEM address */
323 if (s
->PCI0M0_length
) {
324 memory_region_del_subregion(get_system_memory(), &s
->PCI0M0_mem
);
325 object_unparent(OBJECT(&s
->PCI0M0_mem
));
327 /* Map new mem address */
328 s
->PCI0M0_start
= s
->regs
[GT_PCI0M0LD
] << 21;
329 s
->PCI0M0_length
= ((s
->regs
[GT_PCI0M0HD
] + 1) -
330 (s
->regs
[GT_PCI0M0LD
] & 0x7f)) << 21;
331 if (s
->PCI0M0_length
) {
332 memory_region_init_alias(&s
->PCI0M0_mem
, OBJECT(s
), "pci0-mem0",
333 &s
->pci0_mem
, s
->PCI0M0_start
,
335 memory_region_add_subregion(get_system_memory(), s
->PCI0M0_start
,
340 /* Update PCI0M1 mapping */
341 if ((s
->regs
[GT_PCI0M1LD
] & 0x7f) <= s
->regs
[GT_PCI0M1HD
]) {
342 /* Unmap old MEM address */
343 if (s
->PCI0M1_length
) {
344 memory_region_del_subregion(get_system_memory(), &s
->PCI0M1_mem
);
345 object_unparent(OBJECT(&s
->PCI0M1_mem
));
347 /* Map new mem address */
348 s
->PCI0M1_start
= s
->regs
[GT_PCI0M1LD
] << 21;
349 s
->PCI0M1_length
= ((s
->regs
[GT_PCI0M1HD
] + 1) -
350 (s
->regs
[GT_PCI0M1LD
] & 0x7f)) << 21;
351 if (s
->PCI0M1_length
) {
352 memory_region_init_alias(&s
->PCI0M1_mem
, OBJECT(s
), "pci0-mem1",
353 &s
->pci0_mem
, s
->PCI0M1_start
,
355 memory_region_add_subregion(get_system_memory(), s
->PCI0M1_start
,
361 static int gt64120_post_load(void *opaque
, int version_id
)
363 GT64120State
*s
= opaque
;
365 gt64120_isd_mapping(s
);
366 gt64120_pci_mapping(s
);
371 static const VMStateDescription vmstate_gt64120
= {
374 .minimum_version_id
= 1,
375 .post_load
= gt64120_post_load
,
376 .fields
= (VMStateField
[]) {
377 VMSTATE_UINT32_ARRAY(regs
, GT64120State
, GT_REGS
),
378 VMSTATE_END_OF_LIST()
382 static void gt64120_writel(void *opaque
, hwaddr addr
,
383 uint64_t val
, unsigned size
)
385 GT64120State
*s
= opaque
;
386 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
389 if (!(s
->regs
[GT_CPU
] & 0x00001000)) {
393 saddr
= (addr
& 0xfff) >> 2;
396 /* CPU Configuration */
398 s
->regs
[GT_CPU
] = val
;
401 /* Read-only register as only one GT64xxx is present on the CPU bus */
404 /* CPU Address Decode */
406 s
->regs
[GT_PCI0IOLD
] = val
& 0x00007fff;
407 s
->regs
[GT_PCI0IOREMAP
] = val
& 0x000007ff;
408 gt64120_pci_mapping(s
);
411 s
->regs
[GT_PCI0M0LD
] = val
& 0x00007fff;
412 s
->regs
[GT_PCI0M0REMAP
] = val
& 0x000007ff;
413 gt64120_pci_mapping(s
);
416 s
->regs
[GT_PCI0M1LD
] = val
& 0x00007fff;
417 s
->regs
[GT_PCI0M1REMAP
] = val
& 0x000007ff;
418 gt64120_pci_mapping(s
);
421 s
->regs
[GT_PCI1IOLD
] = val
& 0x00007fff;
422 s
->regs
[GT_PCI1IOREMAP
] = val
& 0x000007ff;
425 s
->regs
[GT_PCI1M0LD
] = val
& 0x00007fff;
426 s
->regs
[GT_PCI1M0REMAP
] = val
& 0x000007ff;
429 s
->regs
[GT_PCI1M1LD
] = val
& 0x00007fff;
430 s
->regs
[GT_PCI1M1REMAP
] = val
& 0x000007ff;
435 s
->regs
[saddr
] = val
& 0x0000007f;
436 gt64120_pci_mapping(s
);
441 s
->regs
[saddr
] = val
& 0x0000007f;
444 s
->regs
[saddr
] = val
& 0x00007fff;
445 gt64120_isd_mapping(s
);
454 s
->regs
[saddr
] = val
& 0x000007ff;
457 /* CPU Error Report */
458 case GT_CPUERR_ADDRLO
:
459 case GT_CPUERR_ADDRHI
:
460 case GT_CPUERR_DATALO
:
461 case GT_CPUERR_DATAHI
:
462 case GT_CPUERR_PARITY
:
463 /* Read-only registers, do nothing */
464 qemu_log_mask(LOG_GUEST_ERROR
,
465 "gt64120: Read-only register write "
466 "reg:0x03%x size:%u value:0x%0*" PRIx64
"\n",
467 saddr
<< 2, size
, size
<< 1, val
);
470 /* CPU Sync Barrier */
473 /* Read-only registers, do nothing */
474 qemu_log_mask(LOG_GUEST_ERROR
,
475 "gt64120: Read-only register write "
476 "reg:0x03%x size:%u value:0x%0*" PRIx64
"\n",
477 saddr
<< 2, size
, size
<< 1, val
);
480 /* SDRAM and Device Address Decode */
500 /* SDRAM Configuration */
502 case GT_SDRAM_OPMODE
:
504 case GT_SDRAM_ADDRDECODE
:
505 /* Accept and ignore SDRAM interleave configuration */
506 s
->regs
[saddr
] = val
;
509 /* Device Parameters */
515 /* Not implemented */
516 qemu_log_mask(LOG_UNIMP
,
517 "gt64120: Unimplemented device register write "
518 "reg:0x03%x size:%u value:0x%0*" PRIx64
"\n",
519 saddr
<< 2, size
, size
<< 1, val
);
523 case GT_ECC_ERRDATALO
:
524 case GT_ECC_ERRDATAHI
:
528 /* Read-only registers, do nothing */
529 qemu_log_mask(LOG_GUEST_ERROR
,
530 "gt64120: Read-only register write "
531 "reg:0x03%x size:%u value:0x%0*" PRIx64
"\n",
532 saddr
<< 2, size
, size
<< 1, val
);
557 /* DMA Channel Control */
565 /* Not implemented */
566 qemu_log_mask(LOG_UNIMP
,
567 "gt64120: Unimplemented DMA register write "
568 "reg:0x03%x size:%u value:0x%0*" PRIx64
"\n",
569 saddr
<< 2, size
, size
<< 1, val
);
578 /* Not implemented */
579 qemu_log_mask(LOG_UNIMP
,
580 "gt64120: Unimplemented timer register write "
581 "reg:0x03%x size:%u value:0x%0*" PRIx64
"\n",
582 saddr
<< 2, size
, size
<< 1, val
);
588 s
->regs
[saddr
] = val
& 0x0401fc0f;
591 case GT_PCI0_BS_SCS10
:
592 case GT_PCI0_BS_SCS32
:
593 case GT_PCI0_BS_CS20
:
594 case GT_PCI0_BS_CS3BT
:
598 case GT_PCI0_PREFMBR
:
599 case GT_PCI0_SCS10_BAR
:
600 case GT_PCI0_SCS32_BAR
:
601 case GT_PCI0_CS20_BAR
:
602 case GT_PCI0_CS3BT_BAR
:
603 case GT_PCI0_SSCS10_BAR
:
604 case GT_PCI0_SSCS32_BAR
:
605 case GT_PCI0_SCS3BT_BAR
:
607 case GT_PCI1_BS_SCS10
:
608 case GT_PCI1_BS_SCS32
:
609 case GT_PCI1_BS_CS20
:
610 case GT_PCI1_BS_CS3BT
:
612 case GT_PCI1_PREFMBR
:
613 case GT_PCI1_SCS10_BAR
:
614 case GT_PCI1_SCS32_BAR
:
615 case GT_PCI1_CS20_BAR
:
616 case GT_PCI1_CS3BT_BAR
:
617 case GT_PCI1_SSCS10_BAR
:
618 case GT_PCI1_SSCS32_BAR
:
619 case GT_PCI1_SCS3BT_BAR
:
620 case GT_PCI1_CFGADDR
:
621 case GT_PCI1_CFGDATA
:
622 /* not implemented */
623 qemu_log_mask(LOG_UNIMP
,
624 "gt64120: Unimplemented timer register write "
625 "reg:0x03%x size:%u value:0x%0*" PRIx64
"\n",
626 saddr
<< 2, size
, size
<< 1, val
);
628 case GT_PCI0_CFGADDR
:
629 phb
->config_reg
= val
& 0x80fffffc;
631 case GT_PCI0_CFGDATA
:
632 if (!(s
->regs
[GT_PCI0_CMD
] & 1) && (phb
->config_reg
& 0x00fff800)) {
635 if (phb
->config_reg
& (1u << 31)) {
636 pci_data_write(phb
->bus
, phb
->config_reg
, val
, 4);
642 /* not really implemented */
643 s
->regs
[saddr
] = ~(~(s
->regs
[saddr
]) | ~(val
& 0xfffffffe));
644 s
->regs
[saddr
] |= !!(s
->regs
[saddr
] & 0xfffffffe);
645 trace_gt64120_write("INTRCAUSE", size
, val
);
648 s
->regs
[saddr
] = val
& 0x3c3ffffe;
649 trace_gt64120_write("INTRMASK", size
, val
);
652 s
->regs
[saddr
] = val
& 0x03fffffe;
653 trace_gt64120_write("ICMASK", size
, val
);
655 case GT_PCI0_SERR0MASK
:
656 s
->regs
[saddr
] = val
& 0x0000003f;
657 trace_gt64120_write("SERR0MASK", size
, val
);
660 /* Reserved when only PCI_0 is configured. */
665 case GT_PCI0_HICMASK
:
666 case GT_PCI1_SERR1MASK
:
667 /* not implemented */
670 /* SDRAM Parameters */
676 * We don't simulate electrical parameters of the SDRAM.
677 * Accept, but ignore the values.
679 s
->regs
[saddr
] = val
;
683 qemu_log_mask(LOG_GUEST_ERROR
,
684 "gt64120: Illegal register write "
685 "reg:0x03%x size:%u value:0x%0*" PRIx64
"\n",
686 saddr
<< 2, size
, size
<< 1, val
);
691 static uint64_t gt64120_readl(void *opaque
,
692 hwaddr addr
, unsigned size
)
694 GT64120State
*s
= opaque
;
695 PCIHostState
*phb
= PCI_HOST_BRIDGE(s
);
699 saddr
= (addr
& 0xfff) >> 2;
702 /* CPU Configuration */
705 * Only one GT64xxx is present on the CPU bus, return
708 val
= s
->regs
[saddr
];
711 /* CPU Error Report */
712 case GT_CPUERR_ADDRLO
:
713 case GT_CPUERR_ADDRHI
:
714 case GT_CPUERR_DATALO
:
715 case GT_CPUERR_DATAHI
:
716 case GT_CPUERR_PARITY
:
717 /* Emulated memory has no error, always return the initial values. */
718 val
= s
->regs
[saddr
];
721 /* CPU Sync Barrier */
725 * Reading those register should empty all FIFO on the PCI
726 * bus, which are not emulated. The return value should be
727 * a random value that should be ignored.
733 case GT_ECC_ERRDATALO
:
734 case GT_ECC_ERRDATAHI
:
738 /* Emulated memory has no error, always return the initial values. */
739 val
= s
->regs
[saddr
];
774 val
= s
->regs
[saddr
];
777 /* Read the IRQ number */
778 val
= pic_read_irq(isa_pic
);
781 /* SDRAM and Device Address Decode */
801 val
= s
->regs
[saddr
];
804 /* SDRAM Configuration */
806 case GT_SDRAM_OPMODE
:
808 case GT_SDRAM_ADDRDECODE
:
809 val
= s
->regs
[saddr
];
812 /* SDRAM Parameters */
818 * We don't simulate electrical parameters of the SDRAM.
819 * Just return the last written value.
821 val
= s
->regs
[saddr
];
824 /* Device Parameters */
830 val
= s
->regs
[saddr
];
854 val
= s
->regs
[saddr
];
857 /* DMA Channel Control */
862 val
= s
->regs
[saddr
];
867 val
= s
->regs
[saddr
];
876 val
= s
->regs
[saddr
];
880 case GT_PCI0_CFGADDR
:
881 val
= phb
->config_reg
;
883 case GT_PCI0_CFGDATA
:
884 if (!(phb
->config_reg
& (1 << 31))) {
887 val
= pci_data_read(phb
->bus
, phb
->config_reg
, 4);
889 if (!(s
->regs
[GT_PCI0_CMD
] & 1) && (phb
->config_reg
& 0x00fff800)) {
896 case GT_PCI0_BS_SCS10
:
897 case GT_PCI0_BS_SCS32
:
898 case GT_PCI0_BS_CS20
:
899 case GT_PCI0_BS_CS3BT
:
902 case GT_PCI0_PREFMBR
:
903 case GT_PCI0_SCS10_BAR
:
904 case GT_PCI0_SCS32_BAR
:
905 case GT_PCI0_CS20_BAR
:
906 case GT_PCI0_CS3BT_BAR
:
907 case GT_PCI0_SSCS10_BAR
:
908 case GT_PCI0_SSCS32_BAR
:
909 case GT_PCI0_SCS3BT_BAR
:
912 case GT_PCI1_BS_SCS10
:
913 case GT_PCI1_BS_SCS32
:
914 case GT_PCI1_BS_CS20
:
915 case GT_PCI1_BS_CS3BT
:
917 case GT_PCI1_PREFMBR
:
918 case GT_PCI1_SCS10_BAR
:
919 case GT_PCI1_SCS32_BAR
:
920 case GT_PCI1_CS20_BAR
:
921 case GT_PCI1_CS3BT_BAR
:
922 case GT_PCI1_SSCS10_BAR
:
923 case GT_PCI1_SSCS32_BAR
:
924 case GT_PCI1_SCS3BT_BAR
:
925 case GT_PCI1_CFGADDR
:
926 case GT_PCI1_CFGDATA
:
927 val
= s
->regs
[saddr
];
932 val
= s
->regs
[saddr
];
933 trace_gt64120_read("INTRCAUSE", size
, val
);
936 val
= s
->regs
[saddr
];
937 trace_gt64120_read("INTRMASK", size
, val
);
940 val
= s
->regs
[saddr
];
941 trace_gt64120_read("ICMASK", size
, val
);
943 case GT_PCI0_SERR0MASK
:
944 val
= s
->regs
[saddr
];
945 trace_gt64120_read("SERR0MASK", size
, val
);
948 /* Reserved when only PCI_0 is configured. */
953 case GT_PCI0_HICMASK
:
954 case GT_PCI1_SERR1MASK
:
955 val
= s
->regs
[saddr
];
959 val
= s
->regs
[saddr
];
960 qemu_log_mask(LOG_GUEST_ERROR
,
961 "gt64120: Illegal register read "
962 "reg:0x03%x size:%u value:0x%0*x\n",
963 saddr
<< 2, size
, size
<< 1, val
);
967 if (!(s
->regs
[GT_CPU
] & 0x00001000)) {
974 static const MemoryRegionOps isd_mem_ops
= {
975 .read
= gt64120_readl
,
976 .write
= gt64120_writel
,
977 .endianness
= DEVICE_NATIVE_ENDIAN
,
980 static int gt64120_pci_map_irq(PCIDevice
*pci_dev
, int irq_num
)
984 slot
= (pci_dev
->devfn
>> 3);
990 /* AMD 79C973 Ethernet */
993 /* Crystal 4281 Sound */
996 /* PCI slot 1 to 4 */
998 return ((slot
- 18) + irq_num
) & 0x03;
999 /* Unknown device, don't do any translation */
1005 static int pci_irq_levels
[4];
1007 static void gt64120_pci_set_irq(void *opaque
, int irq_num
, int level
)
1009 int i
, pic_irq
, pic_level
;
1010 qemu_irq
*pic
= opaque
;
1012 pci_irq_levels
[irq_num
] = level
;
1014 /* now we change the pic irq level according to the piix irq mappings */
1016 pic_irq
= piix4_dev
->config
[PIIX_PIRQCA
+ irq_num
];
1018 /* The pic level is the logical OR of all the PCI irqs mapped to it. */
1020 for (i
= 0; i
< 4; i
++) {
1021 if (pic_irq
== piix4_dev
->config
[PIIX_PIRQCA
+ i
]) {
1022 pic_level
|= pci_irq_levels
[i
];
1025 qemu_set_irq(pic
[pic_irq
], pic_level
);
1030 static void gt64120_reset(DeviceState
*dev
)
1032 GT64120State
*s
= GT64120_PCI_HOST_BRIDGE(dev
);
1034 /* FIXME: Malta specific hw assumptions ahead */
1036 /* CPU Configuration */
1037 #ifdef TARGET_WORDS_BIGENDIAN
1038 s
->regs
[GT_CPU
] = 0x00000000;
1040 s
->regs
[GT_CPU
] = 0x00001000;
1042 s
->regs
[GT_MULTI
] = 0x00000003;
1044 /* CPU Address decode */
1045 s
->regs
[GT_SCS10LD
] = 0x00000000;
1046 s
->regs
[GT_SCS10HD
] = 0x00000007;
1047 s
->regs
[GT_SCS32LD
] = 0x00000008;
1048 s
->regs
[GT_SCS32HD
] = 0x0000000f;
1049 s
->regs
[GT_CS20LD
] = 0x000000e0;
1050 s
->regs
[GT_CS20HD
] = 0x00000070;
1051 s
->regs
[GT_CS3BOOTLD
] = 0x000000f8;
1052 s
->regs
[GT_CS3BOOTHD
] = 0x0000007f;
1054 s
->regs
[GT_PCI0IOLD
] = 0x00000080;
1055 s
->regs
[GT_PCI0IOHD
] = 0x0000000f;
1056 s
->regs
[GT_PCI0M0LD
] = 0x00000090;
1057 s
->regs
[GT_PCI0M0HD
] = 0x0000001f;
1058 s
->regs
[GT_ISD
] = 0x000000a0;
1059 s
->regs
[GT_PCI0M1LD
] = 0x00000790;
1060 s
->regs
[GT_PCI0M1HD
] = 0x0000001f;
1061 s
->regs
[GT_PCI1IOLD
] = 0x00000100;
1062 s
->regs
[GT_PCI1IOHD
] = 0x0000000f;
1063 s
->regs
[GT_PCI1M0LD
] = 0x00000110;
1064 s
->regs
[GT_PCI1M0HD
] = 0x0000001f;
1065 s
->regs
[GT_PCI1M1LD
] = 0x00000120;
1066 s
->regs
[GT_PCI1M1HD
] = 0x0000002f;
1068 s
->regs
[GT_SCS10AR
] = 0x00000000;
1069 s
->regs
[GT_SCS32AR
] = 0x00000008;
1070 s
->regs
[GT_CS20R
] = 0x000000e0;
1071 s
->regs
[GT_CS3BOOTR
] = 0x000000f8;
1073 s
->regs
[GT_PCI0IOREMAP
] = 0x00000080;
1074 s
->regs
[GT_PCI0M0REMAP
] = 0x00000090;
1075 s
->regs
[GT_PCI0M1REMAP
] = 0x00000790;
1076 s
->regs
[GT_PCI1IOREMAP
] = 0x00000100;
1077 s
->regs
[GT_PCI1M0REMAP
] = 0x00000110;
1078 s
->regs
[GT_PCI1M1REMAP
] = 0x00000120;
1080 /* CPU Error Report */
1081 s
->regs
[GT_CPUERR_ADDRLO
] = 0x00000000;
1082 s
->regs
[GT_CPUERR_ADDRHI
] = 0x00000000;
1083 s
->regs
[GT_CPUERR_DATALO
] = 0xffffffff;
1084 s
->regs
[GT_CPUERR_DATAHI
] = 0xffffffff;
1085 s
->regs
[GT_CPUERR_PARITY
] = 0x000000ff;
1087 /* CPU Sync Barrier */
1088 s
->regs
[GT_PCI0SYNC
] = 0x00000000;
1089 s
->regs
[GT_PCI1SYNC
] = 0x00000000;
1091 /* SDRAM and Device Address Decode */
1092 s
->regs
[GT_SCS0LD
] = 0x00000000;
1093 s
->regs
[GT_SCS0HD
] = 0x00000007;
1094 s
->regs
[GT_SCS1LD
] = 0x00000008;
1095 s
->regs
[GT_SCS1HD
] = 0x0000000f;
1096 s
->regs
[GT_SCS2LD
] = 0x00000010;
1097 s
->regs
[GT_SCS2HD
] = 0x00000017;
1098 s
->regs
[GT_SCS3LD
] = 0x00000018;
1099 s
->regs
[GT_SCS3HD
] = 0x0000001f;
1100 s
->regs
[GT_CS0LD
] = 0x000000c0;
1101 s
->regs
[GT_CS0HD
] = 0x000000c7;
1102 s
->regs
[GT_CS1LD
] = 0x000000c8;
1103 s
->regs
[GT_CS1HD
] = 0x000000cf;
1104 s
->regs
[GT_CS2LD
] = 0x000000d0;
1105 s
->regs
[GT_CS2HD
] = 0x000000df;
1106 s
->regs
[GT_CS3LD
] = 0x000000f0;
1107 s
->regs
[GT_CS3HD
] = 0x000000fb;
1108 s
->regs
[GT_BOOTLD
] = 0x000000fc;
1109 s
->regs
[GT_BOOTHD
] = 0x000000ff;
1110 s
->regs
[GT_ADERR
] = 0xffffffff;
1112 /* SDRAM Configuration */
1113 s
->regs
[GT_SDRAM_CFG
] = 0x00000200;
1114 s
->regs
[GT_SDRAM_OPMODE
] = 0x00000000;
1115 s
->regs
[GT_SDRAM_BM
] = 0x00000007;
1116 s
->regs
[GT_SDRAM_ADDRDECODE
] = 0x00000002;
1118 /* SDRAM Parameters */
1119 s
->regs
[GT_SDRAM_B0
] = 0x00000005;
1120 s
->regs
[GT_SDRAM_B1
] = 0x00000005;
1121 s
->regs
[GT_SDRAM_B2
] = 0x00000005;
1122 s
->regs
[GT_SDRAM_B3
] = 0x00000005;
1125 s
->regs
[GT_ECC_ERRDATALO
] = 0x00000000;
1126 s
->regs
[GT_ECC_ERRDATAHI
] = 0x00000000;
1127 s
->regs
[GT_ECC_MEM
] = 0x00000000;
1128 s
->regs
[GT_ECC_CALC
] = 0x00000000;
1129 s
->regs
[GT_ECC_ERRADDR
] = 0x00000000;
1131 /* Device Parameters */
1132 s
->regs
[GT_DEV_B0
] = 0x386fffff;
1133 s
->regs
[GT_DEV_B1
] = 0x386fffff;
1134 s
->regs
[GT_DEV_B2
] = 0x386fffff;
1135 s
->regs
[GT_DEV_B3
] = 0x386fffff;
1136 s
->regs
[GT_DEV_BOOT
] = 0x146fffff;
1138 /* DMA registers are all zeroed at reset */
1141 s
->regs
[GT_TC0
] = 0xffffffff;
1142 s
->regs
[GT_TC1
] = 0x00ffffff;
1143 s
->regs
[GT_TC2
] = 0x00ffffff;
1144 s
->regs
[GT_TC3
] = 0x00ffffff;
1145 s
->regs
[GT_TC_CONTROL
] = 0x00000000;
1148 #ifdef TARGET_WORDS_BIGENDIAN
1149 s
->regs
[GT_PCI0_CMD
] = 0x00000000;
1151 s
->regs
[GT_PCI0_CMD
] = 0x00010001;
1153 s
->regs
[GT_PCI0_TOR
] = 0x0000070f;
1154 s
->regs
[GT_PCI0_BS_SCS10
] = 0x00fff000;
1155 s
->regs
[GT_PCI0_BS_SCS32
] = 0x00fff000;
1156 s
->regs
[GT_PCI0_BS_CS20
] = 0x01fff000;
1157 s
->regs
[GT_PCI0_BS_CS3BT
] = 0x00fff000;
1158 s
->regs
[GT_PCI1_IACK
] = 0x00000000;
1159 s
->regs
[GT_PCI0_IACK
] = 0x00000000;
1160 s
->regs
[GT_PCI0_BARE
] = 0x0000000f;
1161 s
->regs
[GT_PCI0_PREFMBR
] = 0x00000040;
1162 s
->regs
[GT_PCI0_SCS10_BAR
] = 0x00000000;
1163 s
->regs
[GT_PCI0_SCS32_BAR
] = 0x01000000;
1164 s
->regs
[GT_PCI0_CS20_BAR
] = 0x1c000000;
1165 s
->regs
[GT_PCI0_CS3BT_BAR
] = 0x1f000000;
1166 s
->regs
[GT_PCI0_SSCS10_BAR
] = 0x00000000;
1167 s
->regs
[GT_PCI0_SSCS32_BAR
] = 0x01000000;
1168 s
->regs
[GT_PCI0_SCS3BT_BAR
] = 0x1f000000;
1169 #ifdef TARGET_WORDS_BIGENDIAN
1170 s
->regs
[GT_PCI1_CMD
] = 0x00000000;
1172 s
->regs
[GT_PCI1_CMD
] = 0x00010001;
1174 s
->regs
[GT_PCI1_TOR
] = 0x0000070f;
1175 s
->regs
[GT_PCI1_BS_SCS10
] = 0x00fff000;
1176 s
->regs
[GT_PCI1_BS_SCS32
] = 0x00fff000;
1177 s
->regs
[GT_PCI1_BS_CS20
] = 0x01fff000;
1178 s
->regs
[GT_PCI1_BS_CS3BT
] = 0x00fff000;
1179 s
->regs
[GT_PCI1_BARE
] = 0x0000000f;
1180 s
->regs
[GT_PCI1_PREFMBR
] = 0x00000040;
1181 s
->regs
[GT_PCI1_SCS10_BAR
] = 0x00000000;
1182 s
->regs
[GT_PCI1_SCS32_BAR
] = 0x01000000;
1183 s
->regs
[GT_PCI1_CS20_BAR
] = 0x1c000000;
1184 s
->regs
[GT_PCI1_CS3BT_BAR
] = 0x1f000000;
1185 s
->regs
[GT_PCI1_SSCS10_BAR
] = 0x00000000;
1186 s
->regs
[GT_PCI1_SSCS32_BAR
] = 0x01000000;
1187 s
->regs
[GT_PCI1_SCS3BT_BAR
] = 0x1f000000;
1188 s
->regs
[GT_PCI1_CFGADDR
] = 0x00000000;
1189 s
->regs
[GT_PCI1_CFGDATA
] = 0x00000000;
1190 s
->regs
[GT_PCI0_CFGADDR
] = 0x00000000;
1192 /* Interrupt registers are all zeroed at reset */
1194 gt64120_isd_mapping(s
);
1195 gt64120_pci_mapping(s
);
1198 PCIBus
*gt64120_register(qemu_irq
*pic
)
1204 dev
= qdev_create(NULL
, TYPE_GT64120_PCI_HOST_BRIDGE
);
1205 d
= GT64120_PCI_HOST_BRIDGE(dev
);
1206 phb
= PCI_HOST_BRIDGE(dev
);
1207 memory_region_init(&d
->pci0_mem
, OBJECT(dev
), "pci0-mem", 4 * GiB
);
1208 address_space_init(&d
->pci0_mem_as
, &d
->pci0_mem
, "pci0-mem");
1209 phb
->bus
= pci_register_root_bus(dev
, "pci",
1210 gt64120_pci_set_irq
, gt64120_pci_map_irq
,
1214 PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS
);
1215 qdev_init_nofail(dev
);
1216 memory_region_init_io(&d
->ISD_mem
, OBJECT(dev
), &isd_mem_ops
, d
,
1219 pci_create_simple(phb
->bus
, PCI_DEVFN(0, 0), "gt64120_pci");
1223 static void gt64120_pci_realize(PCIDevice
*d
, Error
**errp
)
1225 /* FIXME: Malta specific hw assumptions ahead */
1226 pci_set_word(d
->config
+ PCI_COMMAND
, 0);
1227 pci_set_word(d
->config
+ PCI_STATUS
,
1228 PCI_STATUS_FAST_BACK
| PCI_STATUS_DEVSEL_MEDIUM
);
1229 pci_config_set_prog_interface(d
->config
, 0);
1230 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_0
, 0x00000008);
1231 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_1
, 0x01000008);
1232 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_2
, 0x1c000000);
1233 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_3
, 0x1f000000);
1234 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_4
, 0x14000000);
1235 pci_set_long(d
->config
+ PCI_BASE_ADDRESS_5
, 0x14000001);
1236 pci_set_byte(d
->config
+ 0x3d, 0x01);
1239 static void gt64120_pci_class_init(ObjectClass
*klass
, void *data
)
1241 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1242 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1244 k
->realize
= gt64120_pci_realize
;
1245 k
->vendor_id
= PCI_VENDOR_ID_MARVELL
;
1246 k
->device_id
= PCI_DEVICE_ID_MARVELL_GT6412X
;
1248 k
->class_id
= PCI_CLASS_BRIDGE_HOST
;
1250 * PCI-facing part of the host bridge, not usable without the
1251 * host-facing part, which can't be device_add'ed, yet.
1253 dc
->user_creatable
= false;
1256 static const TypeInfo gt64120_pci_info
= {
1257 .name
= "gt64120_pci",
1258 .parent
= TYPE_PCI_DEVICE
,
1259 .instance_size
= sizeof(PCIDevice
),
1260 .class_init
= gt64120_pci_class_init
,
1261 .interfaces
= (InterfaceInfo
[]) {
1262 { INTERFACE_CONVENTIONAL_PCI_DEVICE
},
1267 static void gt64120_class_init(ObjectClass
*klass
, void *data
)
1269 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1271 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
1272 dc
->reset
= gt64120_reset
;
1273 dc
->vmsd
= &vmstate_gt64120
;
1276 static const TypeInfo gt64120_info
= {
1277 .name
= TYPE_GT64120_PCI_HOST_BRIDGE
,
1278 .parent
= TYPE_PCI_HOST_BRIDGE
,
1279 .instance_size
= sizeof(GT64120State
),
1280 .class_init
= gt64120_class_init
,
1283 static void gt64120_pci_register_types(void)
1285 type_register_static(>64120_info
);
1286 type_register_static(>64120_pci_info
);
1289 type_init(gt64120_pci_register_types
)