2 * QEMU Malta board support
4 * Copyright (c) 2006 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu-common.h"
30 #include "hw/southbridge/piix.h"
31 #include "hw/isa/superio.h"
32 #include "hw/char/serial.h"
34 #include "hw/boards.h"
35 #include "hw/i2c/smbus_eeprom.h"
36 #include "hw/block/flash.h"
37 #include "hw/mips/mips.h"
38 #include "hw/mips/cpudevs.h"
39 #include "hw/pci/pci.h"
40 #include "sysemu/sysemu.h"
41 #include "sysemu/arch_init.h"
43 #include "hw/mips/bios.h"
46 #include "hw/loader.h"
48 #include "exec/address-spaces.h"
49 #include "qom/object.h"
50 #include "hw/sysbus.h" /* SysBusDevice */
51 #include "qemu/host-utils.h"
52 #include "sysemu/qtest.h"
53 #include "sysemu/reset.h"
54 #include "sysemu/runstate.h"
55 #include "qapi/error.h"
56 #include "qemu/error-report.h"
57 #include "hw/misc/empty_slot.h"
58 #include "sysemu/kvm.h"
59 #include "hw/semihosting/semihost.h"
60 #include "hw/mips/cps.h"
61 #include "hw/qdev-clock.h"
63 #define ENVP_ADDR 0x80002000l
64 #define ENVP_NB_ENTRIES 16
65 #define ENVP_ENTRY_SIZE 256
67 /* Hardware addresses */
68 #define FLASH_ADDRESS 0x1e000000ULL
69 #define FPGA_ADDRESS 0x1f000000ULL
70 #define RESET_ADDRESS 0x1fc00000ULL
72 #define FLASH_SIZE 0x400000
78 MemoryRegion iomem_lo
; /* 0 - 0x900 */
79 MemoryRegion iomem_hi
; /* 0xa00 - 0x100000 */
93 #define TYPE_MIPS_MALTA "mips-malta"
94 OBJECT_DECLARE_SIMPLE_TYPE(MaltaState
, MIPS_MALTA
)
97 SysBusDevice parent_obj
;
101 qemu_irq i8259
[ISA_NUM_IRQS
];
104 static struct _loaderparams
{
105 int ram_size
, ram_low_size
;
106 const char *kernel_filename
;
107 const char *kernel_cmdline
;
108 const char *initrd_filename
;
112 static void malta_fpga_update_display(void *opaque
)
116 MaltaFPGAState
*s
= opaque
;
118 for (i
= 7 ; i
>= 0 ; i
--) {
119 if (s
->leds
& (1 << i
)) {
127 qemu_chr_fe_printf(&s
->display
, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
129 qemu_chr_fe_printf(&s
->display
, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
134 * EEPROM 24C01 / 24C02 emulation.
136 * Emulation for serial EEPROMs:
137 * 24C01 - 1024 bit (128 x 8)
138 * 24C02 - 2048 bit (256 x 8)
140 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
144 # define logout(fmt, ...) \
145 fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
147 # define logout(fmt, ...) ((void)0)
150 struct _eeprom24c0x_t
{
159 uint8_t contents
[256];
162 typedef struct _eeprom24c0x_t eeprom24c0x_t
;
164 static eeprom24c0x_t spd_eeprom
= {
167 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
169 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
171 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
173 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
175 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
177 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
179 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
181 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
183 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
185 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
187 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
189 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
191 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
193 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
197 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
201 static void generate_eeprom_spd(uint8_t *eeprom
, ram_addr_t ram_size
)
203 enum { SDR
= 0x4, DDR2
= 0x8 } type
;
204 uint8_t *spd
= spd_eeprom
.contents
;
206 uint16_t density
= 0;
209 /* work in terms of MB */
212 while ((ram_size
>= 4) && (nbanks
<= 2)) {
213 int sz_log2
= MIN(31 - clz32(ram_size
), 14);
215 density
|= 1 << (sz_log2
- 2);
216 ram_size
-= 1 << sz_log2
;
219 /* split to 2 banks if possible */
220 if ((nbanks
== 1) && (density
> 1)) {
225 if (density
& 0xff00) {
226 density
= (density
& 0xe0) | ((density
>> 8) & 0x1f);
228 } else if (!(density
& 0x1f)) {
235 warn_report("SPD cannot represent final " RAM_ADDR_FMT
"MB"
236 " of SDRAM", ram_size
);
239 /* fill in SPD memory information */
246 for (i
= 0; i
< 63; i
++) {
251 memcpy(eeprom
, spd
, sizeof(spd_eeprom
.contents
));
254 static void generate_eeprom_serial(uint8_t *eeprom
)
257 uint8_t mac
[6] = { 0x00 };
258 uint8_t sn
[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
261 eeprom
[pos
++] = 0x01;
264 eeprom
[pos
++] = 0x02;
267 eeprom
[pos
++] = 0x01; /* MAC */
268 eeprom
[pos
++] = 0x06; /* length */
269 memcpy(&eeprom
[pos
], mac
, sizeof(mac
));
273 eeprom
[pos
++] = 0x02; /* serial */
274 eeprom
[pos
++] = 0x05; /* length */
275 memcpy(&eeprom
[pos
], sn
, sizeof(sn
));
280 for (i
= 0; i
< pos
; i
++) {
281 eeprom
[pos
] += eeprom
[i
];
285 static uint8_t eeprom24c0x_read(eeprom24c0x_t
*eeprom
)
287 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
288 eeprom
->tick
, eeprom
->scl
, eeprom
->sda
, eeprom
->data
);
292 static void eeprom24c0x_write(eeprom24c0x_t
*eeprom
, int scl
, int sda
)
294 if (eeprom
->scl
&& scl
&& (eeprom
->sda
!= sda
)) {
295 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
296 eeprom
->tick
, eeprom
->scl
, scl
, eeprom
->sda
, sda
,
297 sda
? "stop" : "start");
302 } else if (eeprom
->tick
== 0 && !eeprom
->ack
) {
303 /* Waiting for start. */
304 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
305 eeprom
->tick
, eeprom
->scl
, scl
, eeprom
->sda
, sda
);
306 } else if (!eeprom
->scl
&& scl
) {
307 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
308 eeprom
->tick
, eeprom
->scl
, scl
, eeprom
->sda
, sda
);
310 logout("\ti2c ack bit = 0\n");
313 } else if (eeprom
->sda
== sda
) {
314 uint8_t bit
= (sda
!= 0);
315 logout("\ti2c bit = %d\n", bit
);
316 if (eeprom
->tick
< 9) {
317 eeprom
->command
<<= 1;
318 eeprom
->command
+= bit
;
320 if (eeprom
->tick
== 9) {
321 logout("\tcommand 0x%04x, %s\n", eeprom
->command
,
322 bit
? "read" : "write");
325 } else if (eeprom
->tick
< 17) {
326 if (eeprom
->command
& 1) {
327 sda
= ((eeprom
->data
& 0x80) != 0);
329 eeprom
->address
<<= 1;
330 eeprom
->address
+= bit
;
333 if (eeprom
->tick
== 17) {
334 eeprom
->data
= eeprom
->contents
[eeprom
->address
];
335 logout("\taddress 0x%04x, data 0x%02x\n",
336 eeprom
->address
, eeprom
->data
);
340 } else if (eeprom
->tick
>= 17) {
344 logout("\tsda changed with raising scl\n");
347 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom
->tick
, eeprom
->scl
,
348 scl
, eeprom
->sda
, sda
);
354 static uint64_t malta_fpga_read(void *opaque
, hwaddr addr
,
357 MaltaFPGAState
*s
= opaque
;
361 saddr
= (addr
& 0xfffff);
365 /* SWITCH Register */
370 /* STATUS Register */
372 #ifdef TARGET_WORDS_BIGENDIAN
384 /* LEDBAR Register */
389 /* BRKRES Register */
394 /* UART Registers are handled directly by the serial device */
401 /* XXX: implement a real I2C controller */
405 /* IN = OUT until a real I2C control is implemented */
413 /* I2CINP Register */
415 val
= ((s
->i2cin
& ~1) | eeprom24c0x_read(&spd_eeprom
));
423 /* I2COUT Register */
428 /* I2CSEL Register */
434 qemu_log_mask(LOG_GUEST_ERROR
,
435 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX
"\n",
442 static void malta_fpga_write(void *opaque
, hwaddr addr
,
443 uint64_t val
, unsigned size
)
445 MaltaFPGAState
*s
= opaque
;
448 saddr
= (addr
& 0xfffff);
452 /* SWITCH Register */
460 /* LEDBAR Register */
462 s
->leds
= val
& 0xff;
463 malta_fpga_update_display(s
);
466 /* ASCIIWORD Register */
468 snprintf(s
->display_text
, 9, "%08X", (uint32_t)val
);
469 malta_fpga_update_display(s
);
472 /* ASCIIPOS0 to ASCIIPOS7 Registers */
481 s
->display_text
[(saddr
- 0x00418) >> 3] = (char) val
;
482 malta_fpga_update_display(s
);
485 /* SOFTRES Register */
488 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
492 /* BRKRES Register */
497 /* UART Registers are handled directly by the serial device */
501 s
->gpout
= val
& 0xff;
506 s
->i2coe
= val
& 0x03;
509 /* I2COUT Register */
511 eeprom24c0x_write(&spd_eeprom
, val
& 0x02, val
& 0x01);
515 /* I2CSEL Register */
517 s
->i2csel
= val
& 0x01;
521 qemu_log_mask(LOG_GUEST_ERROR
,
522 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX
"\n",
528 static const MemoryRegionOps malta_fpga_ops
= {
529 .read
= malta_fpga_read
,
530 .write
= malta_fpga_write
,
531 .endianness
= DEVICE_NATIVE_ENDIAN
,
534 static void malta_fpga_reset(void *opaque
)
536 MaltaFPGAState
*s
= opaque
;
546 s
->display_text
[8] = '\0';
547 snprintf(s
->display_text
, 9, " ");
550 static void malta_fgpa_display_event(void *opaque
, QEMUChrEvent event
)
552 MaltaFPGAState
*s
= opaque
;
554 if (event
== CHR_EVENT_OPENED
&& !s
->display_inited
) {
555 qemu_chr_fe_printf(&s
->display
, "\e[HMalta LEDBAR\r\n");
556 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
557 qemu_chr_fe_printf(&s
->display
, "+ +\r\n");
558 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
559 qemu_chr_fe_printf(&s
->display
, "\n");
560 qemu_chr_fe_printf(&s
->display
, "Malta ASCII\r\n");
561 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
562 qemu_chr_fe_printf(&s
->display
, "+ +\r\n");
563 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
564 s
->display_inited
= true;
568 static MaltaFPGAState
*malta_fpga_init(MemoryRegion
*address_space
,
569 hwaddr base
, qemu_irq uart_irq
, Chardev
*uart_chr
)
574 s
= g_new0(MaltaFPGAState
, 1);
576 memory_region_init_io(&s
->iomem
, NULL
, &malta_fpga_ops
, s
,
577 "malta-fpga", 0x100000);
578 memory_region_init_alias(&s
->iomem_lo
, NULL
, "malta-fpga",
579 &s
->iomem
, 0, 0x900);
580 memory_region_init_alias(&s
->iomem_hi
, NULL
, "malta-fpga",
581 &s
->iomem
, 0xa00, 0x100000 - 0xa00);
583 memory_region_add_subregion(address_space
, base
, &s
->iomem_lo
);
584 memory_region_add_subregion(address_space
, base
+ 0xa00, &s
->iomem_hi
);
586 chr
= qemu_chr_new("fpga", "vc:320x200", NULL
);
587 qemu_chr_fe_init(&s
->display
, chr
, NULL
);
588 qemu_chr_fe_set_handlers(&s
->display
, NULL
, NULL
,
589 malta_fgpa_display_event
, NULL
, s
, NULL
, true);
591 s
->uart
= serial_mm_init(address_space
, base
+ 0x900, 3, uart_irq
,
592 230400, uart_chr
, DEVICE_NATIVE_ENDIAN
);
595 qemu_register_reset(malta_fpga_reset
, s
);
600 /* Network support */
601 static void network_init(PCIBus
*pci_bus
)
605 for (i
= 0; i
< nb_nics
; i
++) {
606 NICInfo
*nd
= &nd_table
[i
];
607 const char *default_devaddr
= NULL
;
609 if (i
== 0 && (!nd
->model
|| strcmp(nd
->model
, "pcnet") == 0))
610 /* The malta board has a PCNet card using PCI SLOT 11 */
611 default_devaddr
= "0b";
613 pci_nic_init_nofail(nd
, pci_bus
, "pcnet", default_devaddr
);
617 static void write_bootloader_nanomips(uint8_t *base
, int64_t run_addr
,
618 int64_t kernel_entry
)
622 /* Small bootloader */
623 p
= (uint16_t *)base
;
625 #define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
626 #define NM_HI2(VAL) \
627 (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
628 #define NM_LO(VAL) ((VAL) & 0xfff)
630 stw_p(p
++, 0x2800); stw_p(p
++, 0x001c);
632 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
634 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
636 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
638 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
640 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
642 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
644 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
648 if (semihosting_get_argc()) {
649 /* Preserve a0 content as arguments have been passed */
650 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
653 stw_p(p
++, 0x0080); stw_p(p
++, 0x0002);
657 stw_p(p
++, 0xe3a0 | NM_HI1(ENVP_ADDR
- 64));
659 stw_p(p
++, NM_HI2(ENVP_ADDR
- 64));
660 /* lui sp,%hi(ENVP_ADDR - 64) */
662 stw_p(p
++, 0x83bd); stw_p(p
++, NM_LO(ENVP_ADDR
- 64));
663 /* ori sp,sp,%lo(ENVP_ADDR - 64) */
665 stw_p(p
++, 0xe0a0 | NM_HI1(ENVP_ADDR
));
667 stw_p(p
++, NM_HI2(ENVP_ADDR
));
668 /* lui a1,%hi(ENVP_ADDR) */
670 stw_p(p
++, 0x80a5); stw_p(p
++, NM_LO(ENVP_ADDR
));
671 /* ori a1,a1,%lo(ENVP_ADDR) */
673 stw_p(p
++, 0xe0c0 | NM_HI1(ENVP_ADDR
+ 8));
675 stw_p(p
++, NM_HI2(ENVP_ADDR
+ 8));
676 /* lui a2,%hi(ENVP_ADDR + 8) */
678 stw_p(p
++, 0x80c6); stw_p(p
++, NM_LO(ENVP_ADDR
+ 8));
679 /* ori a2,a2,%lo(ENVP_ADDR + 8) */
681 stw_p(p
++, 0xe0e0 | NM_HI1(loaderparams
.ram_low_size
));
683 stw_p(p
++, NM_HI2(loaderparams
.ram_low_size
));
684 /* lui a3,%hi(loaderparams.ram_low_size) */
686 stw_p(p
++, 0x80e7); stw_p(p
++, NM_LO(loaderparams
.ram_low_size
));
687 /* ori a3,a3,%lo(loaderparams.ram_low_size) */
690 * Load BAR registers as done by YAMON:
692 * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
693 * - set up PCI0 MEM0 at 0x10000000, size 0x8000000
694 * - set up PCI0 MEM1 at 0x18200000, size 0xbe00000
697 stw_p(p
++, 0xe040); stw_p(p
++, 0x0681);
698 /* lui t1, %hi(0xb4000000) */
700 #ifdef TARGET_WORDS_BIGENDIAN
702 stw_p(p
++, 0xe020); stw_p(p
++, 0x0be1);
703 /* lui t0, %hi(0xdf000000) */
705 /* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c) */
706 stw_p(p
++, 0x8422); stw_p(p
++, 0x9068);
707 /* sw t0, 0x68(t1) */
709 stw_p(p
++, 0xe040); stw_p(p
++, 0x077d);
710 /* lui t1, %hi(0xbbe00000) */
712 stw_p(p
++, 0xe020); stw_p(p
++, 0x0801);
713 /* lui t0, %hi(0xc0000000) */
715 /* 0x48 corresponds to GT_PCI0IOLD */
716 stw_p(p
++, 0x8422); stw_p(p
++, 0x9048);
717 /* sw t0, 0x48(t1) */
719 stw_p(p
++, 0xe020); stw_p(p
++, 0x0800);
720 /* lui t0, %hi(0x40000000) */
722 /* 0x50 corresponds to GT_PCI0IOHD */
723 stw_p(p
++, 0x8422); stw_p(p
++, 0x9050);
724 /* sw t0, 0x50(t1) */
726 stw_p(p
++, 0xe020); stw_p(p
++, 0x0001);
727 /* lui t0, %hi(0x80000000) */
729 /* 0x58 corresponds to GT_PCI0M0LD */
730 stw_p(p
++, 0x8422); stw_p(p
++, 0x9058);
731 /* sw t0, 0x58(t1) */
733 stw_p(p
++, 0xe020); stw_p(p
++, 0x07e0);
734 /* lui t0, %hi(0x3f000000) */
736 /* 0x60 corresponds to GT_PCI0M0HD */
737 stw_p(p
++, 0x8422); stw_p(p
++, 0x9060);
738 /* sw t0, 0x60(t1) */
740 stw_p(p
++, 0xe020); stw_p(p
++, 0x0821);
741 /* lui t0, %hi(0xc1000000) */
743 /* 0x80 corresponds to GT_PCI0M1LD */
744 stw_p(p
++, 0x8422); stw_p(p
++, 0x9080);
745 /* sw t0, 0x80(t1) */
747 stw_p(p
++, 0xe020); stw_p(p
++, 0x0bc0);
748 /* lui t0, %hi(0x5e000000) */
752 stw_p(p
++, 0x0020); stw_p(p
++, 0x00df);
753 /* addiu[32] t0, $0, 0xdf */
755 /* 0x68 corresponds to GT_ISD */
756 stw_p(p
++, 0x8422); stw_p(p
++, 0x9068);
757 /* sw t0, 0x68(t1) */
759 /* Use kseg2 remapped address 0x1be00000 */
760 stw_p(p
++, 0xe040); stw_p(p
++, 0x077d);
761 /* lui t1, %hi(0xbbe00000) */
763 stw_p(p
++, 0x0020); stw_p(p
++, 0x00c0);
764 /* addiu[32] t0, $0, 0xc0 */
766 /* 0x48 corresponds to GT_PCI0IOLD */
767 stw_p(p
++, 0x8422); stw_p(p
++, 0x9048);
768 /* sw t0, 0x48(t1) */
770 stw_p(p
++, 0x0020); stw_p(p
++, 0x0040);
771 /* addiu[32] t0, $0, 0x40 */
773 /* 0x50 corresponds to GT_PCI0IOHD */
774 stw_p(p
++, 0x8422); stw_p(p
++, 0x9050);
775 /* sw t0, 0x50(t1) */
777 stw_p(p
++, 0x0020); stw_p(p
++, 0x0080);
778 /* addiu[32] t0, $0, 0x80 */
780 /* 0x58 corresponds to GT_PCI0M0LD */
781 stw_p(p
++, 0x8422); stw_p(p
++, 0x9058);
782 /* sw t0, 0x58(t1) */
784 stw_p(p
++, 0x0020); stw_p(p
++, 0x003f);
785 /* addiu[32] t0, $0, 0x3f */
787 /* 0x60 corresponds to GT_PCI0M0HD */
788 stw_p(p
++, 0x8422); stw_p(p
++, 0x9060);
789 /* sw t0, 0x60(t1) */
791 stw_p(p
++, 0x0020); stw_p(p
++, 0x00c1);
792 /* addiu[32] t0, $0, 0xc1 */
794 /* 0x80 corresponds to GT_PCI0M1LD */
795 stw_p(p
++, 0x8422); stw_p(p
++, 0x9080);
796 /* sw t0, 0x80(t1) */
798 stw_p(p
++, 0x0020); stw_p(p
++, 0x005e);
799 /* addiu[32] t0, $0, 0x5e */
803 /* 0x88 corresponds to GT_PCI0M1HD */
804 stw_p(p
++, 0x8422); stw_p(p
++, 0x9088);
805 /* sw t0, 0x88(t1) */
807 stw_p(p
++, 0xe320 | NM_HI1(kernel_entry
));
809 stw_p(p
++, NM_HI2(kernel_entry
));
810 /* lui t9,%hi(kernel_entry) */
812 stw_p(p
++, 0x8339); stw_p(p
++, NM_LO(kernel_entry
));
813 /* ori t9,t9,%lo(kernel_entry) */
815 stw_p(p
++, 0x4bf9); stw_p(p
++, 0x0000);
820 * ROM and pseudo bootloader
822 * The following code implements a very very simple bootloader. It first
823 * loads the registers a0 to a3 to the values expected by the OS, and
824 * then jump at the kernel address.
826 * The bootloader should pass the locations of the kernel arguments and
827 * environment variables tables. Those tables contain the 32-bit address
828 * of NULL terminated strings. The environment variables table should be
829 * terminated by a NULL address.
831 * For a simpler implementation, the number of kernel arguments is fixed
832 * to two (the name of the kernel and the command line), and the two
833 * tables are actually the same one.
835 * The registers a0 to a3 should contain the following values:
836 * a0 - number of kernel arguments
837 * a1 - 32-bit address of the kernel arguments table
838 * a2 - 32-bit address of the environment variables table
839 * a3 - RAM size in bytes
841 static void write_bootloader(uint8_t *base
, int64_t run_addr
,
842 int64_t kernel_entry
)
846 /* Small bootloader */
847 p
= (uint32_t *)base
;
849 stl_p(p
++, 0x08000000 | /* j 0x1fc00580 */
850 ((run_addr
+ 0x580) & 0x0fffffff) >> 2);
851 stl_p(p
++, 0x00000000); /* nop */
853 /* YAMON service vector */
854 stl_p(base
+ 0x500, run_addr
+ 0x0580); /* start: */
855 stl_p(base
+ 0x504, run_addr
+ 0x083c); /* print_count: */
856 stl_p(base
+ 0x520, run_addr
+ 0x0580); /* start: */
857 stl_p(base
+ 0x52c, run_addr
+ 0x0800); /* flush_cache: */
858 stl_p(base
+ 0x534, run_addr
+ 0x0808); /* print: */
859 stl_p(base
+ 0x538, run_addr
+ 0x0800); /* reg_cpu_isr: */
860 stl_p(base
+ 0x53c, run_addr
+ 0x0800); /* unred_cpu_isr: */
861 stl_p(base
+ 0x540, run_addr
+ 0x0800); /* reg_ic_isr: */
862 stl_p(base
+ 0x544, run_addr
+ 0x0800); /* unred_ic_isr: */
863 stl_p(base
+ 0x548, run_addr
+ 0x0800); /* reg_esr: */
864 stl_p(base
+ 0x54c, run_addr
+ 0x0800); /* unreg_esr: */
865 stl_p(base
+ 0x550, run_addr
+ 0x0800); /* getchar: */
866 stl_p(base
+ 0x554, run_addr
+ 0x0800); /* syscon_read: */
869 /* Second part of the bootloader */
870 p
= (uint32_t *) (base
+ 0x580);
872 if (semihosting_get_argc()) {
873 /* Preserve a0 content as arguments have been passed */
874 stl_p(p
++, 0x00000000); /* nop */
876 stl_p(p
++, 0x24040002); /* addiu a0, zero, 2 */
879 /* lui sp, high(ENVP_ADDR) */
880 stl_p(p
++, 0x3c1d0000 | (((ENVP_ADDR
- 64) >> 16) & 0xffff));
881 /* ori sp, sp, low(ENVP_ADDR) */
882 stl_p(p
++, 0x37bd0000 | ((ENVP_ADDR
- 64) & 0xffff));
883 /* lui a1, high(ENVP_ADDR) */
884 stl_p(p
++, 0x3c050000 | ((ENVP_ADDR
>> 16) & 0xffff));
885 /* ori a1, a1, low(ENVP_ADDR) */
886 stl_p(p
++, 0x34a50000 | (ENVP_ADDR
& 0xffff));
887 /* lui a2, high(ENVP_ADDR + 8) */
888 stl_p(p
++, 0x3c060000 | (((ENVP_ADDR
+ 8) >> 16) & 0xffff));
889 /* ori a2, a2, low(ENVP_ADDR + 8) */
890 stl_p(p
++, 0x34c60000 | ((ENVP_ADDR
+ 8) & 0xffff));
891 /* lui a3, high(ram_low_size) */
892 stl_p(p
++, 0x3c070000 | (loaderparams
.ram_low_size
>> 16));
893 /* ori a3, a3, low(ram_low_size) */
894 stl_p(p
++, 0x34e70000 | (loaderparams
.ram_low_size
& 0xffff));
896 /* Load BAR registers as done by YAMON */
897 stl_p(p
++, 0x3c09b400); /* lui t1, 0xb400 */
899 #ifdef TARGET_WORDS_BIGENDIAN
900 stl_p(p
++, 0x3c08df00); /* lui t0, 0xdf00 */
902 stl_p(p
++, 0x340800df); /* ori t0, r0, 0x00df */
904 stl_p(p
++, 0xad280068); /* sw t0, 0x0068(t1) */
906 stl_p(p
++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
908 #ifdef TARGET_WORDS_BIGENDIAN
909 stl_p(p
++, 0x3c08c000); /* lui t0, 0xc000 */
911 stl_p(p
++, 0x340800c0); /* ori t0, r0, 0x00c0 */
913 stl_p(p
++, 0xad280048); /* sw t0, 0x0048(t1) */
914 #ifdef TARGET_WORDS_BIGENDIAN
915 stl_p(p
++, 0x3c084000); /* lui t0, 0x4000 */
917 stl_p(p
++, 0x34080040); /* ori t0, r0, 0x0040 */
919 stl_p(p
++, 0xad280050); /* sw t0, 0x0050(t1) */
921 #ifdef TARGET_WORDS_BIGENDIAN
922 stl_p(p
++, 0x3c088000); /* lui t0, 0x8000 */
924 stl_p(p
++, 0x34080080); /* ori t0, r0, 0x0080 */
926 stl_p(p
++, 0xad280058); /* sw t0, 0x0058(t1) */
927 #ifdef TARGET_WORDS_BIGENDIAN
928 stl_p(p
++, 0x3c083f00); /* lui t0, 0x3f00 */
930 stl_p(p
++, 0x3408003f); /* ori t0, r0, 0x003f */
932 stl_p(p
++, 0xad280060); /* sw t0, 0x0060(t1) */
934 #ifdef TARGET_WORDS_BIGENDIAN
935 stl_p(p
++, 0x3c08c100); /* lui t0, 0xc100 */
937 stl_p(p
++, 0x340800c1); /* ori t0, r0, 0x00c1 */
939 stl_p(p
++, 0xad280080); /* sw t0, 0x0080(t1) */
940 #ifdef TARGET_WORDS_BIGENDIAN
941 stl_p(p
++, 0x3c085e00); /* lui t0, 0x5e00 */
943 stl_p(p
++, 0x3408005e); /* ori t0, r0, 0x005e */
945 stl_p(p
++, 0xad280088); /* sw t0, 0x0088(t1) */
947 /* Jump to kernel code */
948 stl_p(p
++, 0x3c1f0000 |
949 ((kernel_entry
>> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
950 stl_p(p
++, 0x37ff0000 |
951 (kernel_entry
& 0xffff)); /* ori ra, ra, low(kernel_entry) */
952 stl_p(p
++, 0x03e00009); /* jalr ra */
953 stl_p(p
++, 0x00000000); /* nop */
955 /* YAMON subroutines */
956 p
= (uint32_t *) (base
+ 0x800);
957 stl_p(p
++, 0x03e00009); /* jalr ra */
958 stl_p(p
++, 0x24020000); /* li v0,0 */
959 /* 808 YAMON print */
960 stl_p(p
++, 0x03e06821); /* move t5,ra */
961 stl_p(p
++, 0x00805821); /* move t3,a0 */
962 stl_p(p
++, 0x00a05021); /* move t2,a1 */
963 stl_p(p
++, 0x91440000); /* lbu a0,0(t2) */
964 stl_p(p
++, 0x254a0001); /* addiu t2,t2,1 */
965 stl_p(p
++, 0x10800005); /* beqz a0,834 */
966 stl_p(p
++, 0x00000000); /* nop */
967 stl_p(p
++, 0x0ff0021c); /* jal 870 */
968 stl_p(p
++, 0x00000000); /* nop */
969 stl_p(p
++, 0x1000fff9); /* b 814 */
970 stl_p(p
++, 0x00000000); /* nop */
971 stl_p(p
++, 0x01a00009); /* jalr t5 */
972 stl_p(p
++, 0x01602021); /* move a0,t3 */
973 /* 0x83c YAMON print_count */
974 stl_p(p
++, 0x03e06821); /* move t5,ra */
975 stl_p(p
++, 0x00805821); /* move t3,a0 */
976 stl_p(p
++, 0x00a05021); /* move t2,a1 */
977 stl_p(p
++, 0x00c06021); /* move t4,a2 */
978 stl_p(p
++, 0x91440000); /* lbu a0,0(t2) */
979 stl_p(p
++, 0x0ff0021c); /* jal 870 */
980 stl_p(p
++, 0x00000000); /* nop */
981 stl_p(p
++, 0x254a0001); /* addiu t2,t2,1 */
982 stl_p(p
++, 0x258cffff); /* addiu t4,t4,-1 */
983 stl_p(p
++, 0x1580fffa); /* bnez t4,84c */
984 stl_p(p
++, 0x00000000); /* nop */
985 stl_p(p
++, 0x01a00009); /* jalr t5 */
986 stl_p(p
++, 0x01602021); /* move a0,t3 */
988 stl_p(p
++, 0x3c08b800); /* lui t0,0xb400 */
989 stl_p(p
++, 0x350803f8); /* ori t0,t0,0x3f8 */
990 stl_p(p
++, 0x91090005); /* lbu t1,5(t0) */
991 stl_p(p
++, 0x00000000); /* nop */
992 stl_p(p
++, 0x31290040); /* andi t1,t1,0x40 */
993 stl_p(p
++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
994 stl_p(p
++, 0x00000000); /* nop */
995 stl_p(p
++, 0x03e00009); /* jalr ra */
996 stl_p(p
++, 0xa1040000); /* sb a0,0(t0) */
1000 static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf
, int index
,
1001 const char *string
, ...)
1006 if (index
>= ENVP_NB_ENTRIES
) {
1010 if (string
== NULL
) {
1011 prom_buf
[index
] = 0;
1015 table_addr
= sizeof(int32_t) * ENVP_NB_ENTRIES
+ index
* ENVP_ENTRY_SIZE
;
1016 prom_buf
[index
] = tswap32(ENVP_ADDR
+ table_addr
);
1018 va_start(ap
, string
);
1019 vsnprintf((char *)prom_buf
+ table_addr
, ENVP_ENTRY_SIZE
, string
, ap
);
1024 static int64_t load_kernel(void)
1026 int64_t kernel_entry
, kernel_high
, initrd_size
;
1028 ram_addr_t initrd_offset
;
1033 uint64_t (*xlate_to_kseg0
) (void *opaque
, uint64_t addr
);
1035 #ifdef TARGET_WORDS_BIGENDIAN
1041 kernel_size
= load_elf(loaderparams
.kernel_filename
, NULL
,
1042 cpu_mips_kseg0_to_phys
, NULL
,
1043 (uint64_t *)&kernel_entry
, NULL
,
1044 (uint64_t *)&kernel_high
, NULL
, big_endian
, EM_MIPS
,
1046 if (kernel_size
< 0) {
1047 error_report("could not load kernel '%s': %s",
1048 loaderparams
.kernel_filename
,
1049 load_elf_strerror(kernel_size
));
1053 /* Check where the kernel has been linked */
1054 if (kernel_entry
& 0x80000000ll
) {
1055 if (kvm_enabled()) {
1056 error_report("KVM guest kernels must be linked in useg. "
1057 "Did you forget to enable CONFIG_KVM_GUEST?");
1061 xlate_to_kseg0
= cpu_mips_phys_to_kseg0
;
1063 /* if kernel entry is in useg it is probably a KVM T&E kernel */
1064 mips_um_ksegs_enable();
1066 xlate_to_kseg0
= cpu_mips_kvm_um_phys_to_kseg0
;
1072 if (loaderparams
.initrd_filename
) {
1073 initrd_size
= get_image_size(loaderparams
.initrd_filename
);
1074 if (initrd_size
> 0) {
1076 * The kernel allocates the bootmap memory in the low memory after
1077 * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
1080 initrd_offset
= ROUND_UP(loaderparams
.ram_low_size
1081 - (initrd_size
+ 128 * KiB
),
1083 if (kernel_high
>= initrd_offset
) {
1084 error_report("memory too small for initial ram disk '%s'",
1085 loaderparams
.initrd_filename
);
1088 initrd_size
= load_image_targphys(loaderparams
.initrd_filename
,
1090 ram_size
- initrd_offset
);
1092 if (initrd_size
== (target_ulong
) -1) {
1093 error_report("could not load initial ram disk '%s'",
1094 loaderparams
.initrd_filename
);
1099 /* Setup prom parameters. */
1100 prom_size
= ENVP_NB_ENTRIES
* (sizeof(int32_t) + ENVP_ENTRY_SIZE
);
1101 prom_buf
= g_malloc(prom_size
);
1103 prom_set(prom_buf
, prom_index
++, "%s", loaderparams
.kernel_filename
);
1104 if (initrd_size
> 0) {
1105 prom_set(prom_buf
, prom_index
++,
1106 "rd_start=0x%" PRIx64
" rd_size=%" PRId64
" %s",
1107 xlate_to_kseg0(NULL
, initrd_offset
),
1108 initrd_size
, loaderparams
.kernel_cmdline
);
1110 prom_set(prom_buf
, prom_index
++, "%s", loaderparams
.kernel_cmdline
);
1113 prom_set(prom_buf
, prom_index
++, "memsize");
1114 prom_set(prom_buf
, prom_index
++, "%u", loaderparams
.ram_low_size
);
1116 prom_set(prom_buf
, prom_index
++, "ememsize");
1117 prom_set(prom_buf
, prom_index
++, "%u", loaderparams
.ram_size
);
1119 prom_set(prom_buf
, prom_index
++, "modetty0");
1120 prom_set(prom_buf
, prom_index
++, "38400n8r");
1121 prom_set(prom_buf
, prom_index
++, NULL
);
1123 rom_add_blob_fixed("prom", prom_buf
, prom_size
,
1124 cpu_mips_kseg0_to_phys(NULL
, ENVP_ADDR
));
1127 return kernel_entry
;
1130 static void malta_mips_config(MIPSCPU
*cpu
)
1132 MachineState
*ms
= MACHINE(qdev_get_machine());
1133 unsigned int smp_cpus
= ms
->smp
.cpus
;
1134 CPUMIPSState
*env
= &cpu
->env
;
1135 CPUState
*cs
= CPU(cpu
);
1137 env
->mvp
->CP0_MVPConf0
|= ((smp_cpus
- 1) << CP0MVPC0_PVPE
) |
1138 ((smp_cpus
* cs
->nr_threads
- 1) << CP0MVPC0_PTC
);
1141 static void main_cpu_reset(void *opaque
)
1143 MIPSCPU
*cpu
= opaque
;
1144 CPUMIPSState
*env
= &cpu
->env
;
1146 cpu_reset(CPU(cpu
));
1149 * The bootloader does not need to be rewritten as it is located in a
1150 * read only location. The kernel location and the arguments table
1151 * location does not change.
1153 if (loaderparams
.kernel_filename
) {
1154 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
1157 malta_mips_config(cpu
);
1159 if (kvm_enabled()) {
1160 /* Start running from the bootloader we wrote to end of RAM */
1161 env
->active_tc
.PC
= 0x40000000 + loaderparams
.ram_low_size
;
1165 static void create_cpu_without_cps(MachineState
*ms
, MaltaState
*s
,
1166 qemu_irq
*cbus_irq
, qemu_irq
*i8259_irq
)
1172 for (i
= 0; i
< ms
->smp
.cpus
; i
++) {
1173 cpu
= mips_cpu_create_with_clock(ms
->cpu_type
, s
->cpuclk
);
1175 /* Init internal devices */
1176 cpu_mips_irq_init_cpu(cpu
);
1177 cpu_mips_clock_init(cpu
);
1178 qemu_register_reset(main_cpu_reset
, cpu
);
1181 cpu
= MIPS_CPU(first_cpu
);
1183 *i8259_irq
= env
->irq
[2];
1184 *cbus_irq
= env
->irq
[4];
1187 static void create_cps(MachineState
*ms
, MaltaState
*s
,
1188 qemu_irq
*cbus_irq
, qemu_irq
*i8259_irq
)
1190 object_initialize_child(OBJECT(s
), "cps", &s
->cps
, TYPE_MIPS_CPS
);
1191 object_property_set_str(OBJECT(&s
->cps
), "cpu-type", ms
->cpu_type
,
1193 object_property_set_int(OBJECT(&s
->cps
), "num-vp", ms
->smp
.cpus
,
1195 qdev_connect_clock_in(DEVICE(&s
->cps
), "clk-in", s
->cpuclk
);
1196 sysbus_realize(SYS_BUS_DEVICE(&s
->cps
), &error_fatal
);
1198 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s
->cps
), 0, 0, 1);
1200 *i8259_irq
= get_cps_irq(&s
->cps
, 3);
1204 static void mips_create_cpu(MachineState
*ms
, MaltaState
*s
,
1205 qemu_irq
*cbus_irq
, qemu_irq
*i8259_irq
)
1207 if ((ms
->smp
.cpus
> 1) && cpu_supports_cps_smp(ms
->cpu_type
)) {
1208 create_cps(ms
, s
, cbus_irq
, i8259_irq
);
1210 create_cpu_without_cps(ms
, s
, cbus_irq
, i8259_irq
);
1215 void mips_malta_init(MachineState
*machine
)
1217 ram_addr_t ram_size
= machine
->ram_size
;
1218 ram_addr_t ram_low_size
;
1219 const char *kernel_filename
= machine
->kernel_filename
;
1220 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1221 const char *initrd_filename
= machine
->initrd_filename
;
1224 MemoryRegion
*system_memory
= get_system_memory();
1225 MemoryRegion
*ram_low_preio
= g_new(MemoryRegion
, 1);
1226 MemoryRegion
*ram_low_postio
;
1227 MemoryRegion
*bios
, *bios_copy
= g_new(MemoryRegion
, 1);
1228 const size_t smbus_eeprom_size
= 8 * 256;
1229 uint8_t *smbus_eeprom_buf
= g_malloc0(smbus_eeprom_size
);
1230 int64_t kernel_entry
, bootloader_run_addr
;
1233 qemu_irq cbus_irq
, i8259_irq
;
1241 s
= MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA
));
1242 sysbus_realize_and_unref(SYS_BUS_DEVICE(s
), &error_fatal
);
1245 mips_create_cpu(machine
, s
, &cbus_irq
, &i8259_irq
);
1248 if (ram_size
> 2 * GiB
) {
1249 error_report("Too much memory for this machine: %" PRId64
"MB,"
1250 " maximum 2048MB", ram_size
/ MiB
);
1254 /* register RAM at high address where it is undisturbed by IO */
1255 memory_region_add_subregion(system_memory
, 0x80000000, machine
->ram
);
1257 /* alias for pre IO hole access */
1258 memory_region_init_alias(ram_low_preio
, NULL
, "mips_malta_low_preio.ram",
1259 machine
->ram
, 0, MIN(ram_size
, 256 * MiB
));
1260 memory_region_add_subregion(system_memory
, 0, ram_low_preio
);
1262 /* alias for post IO hole access, if there is enough RAM */
1263 if (ram_size
> 512 * MiB
) {
1264 ram_low_postio
= g_new(MemoryRegion
, 1);
1265 memory_region_init_alias(ram_low_postio
, NULL
,
1266 "mips_malta_low_postio.ram",
1267 machine
->ram
, 512 * MiB
,
1268 ram_size
- 512 * MiB
);
1269 memory_region_add_subregion(system_memory
, 512 * MiB
,
1273 #ifdef TARGET_WORDS_BIGENDIAN
1281 /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
1282 malta_fpga_init(system_memory
, FPGA_ADDRESS
, cbus_irq
, serial_hd(2));
1284 /* Load firmware in flash / BIOS. */
1285 dinfo
= drive_get(IF_PFLASH
, 0, fl_idx
);
1286 fl
= pflash_cfi01_register(FLASH_ADDRESS
, "mips_malta.bios",
1288 dinfo
? blk_by_legacy_dinfo(dinfo
) : NULL
,
1290 4, 0x0000, 0x0000, 0x0000, 0x0000, be
);
1291 bios
= pflash_cfi01_get_memory(fl
);
1293 if (kernel_filename
) {
1294 ram_low_size
= MIN(ram_size
, 256 * MiB
);
1295 /* For KVM we reserve 1MB of RAM for running bootloader */
1296 if (kvm_enabled()) {
1297 ram_low_size
-= 0x100000;
1298 bootloader_run_addr
= 0x40000000 + ram_low_size
;
1300 bootloader_run_addr
= 0xbfc00000;
1303 /* Write a small bootloader to the flash location. */
1304 loaderparams
.ram_size
= ram_size
;
1305 loaderparams
.ram_low_size
= ram_low_size
;
1306 loaderparams
.kernel_filename
= kernel_filename
;
1307 loaderparams
.kernel_cmdline
= kernel_cmdline
;
1308 loaderparams
.initrd_filename
= initrd_filename
;
1309 kernel_entry
= load_kernel();
1311 if (!cpu_supports_isa(machine
->cpu_type
, ISA_NANOMIPS32
)) {
1312 write_bootloader(memory_region_get_ram_ptr(bios
),
1313 bootloader_run_addr
, kernel_entry
);
1315 write_bootloader_nanomips(memory_region_get_ram_ptr(bios
),
1316 bootloader_run_addr
, kernel_entry
);
1318 if (kvm_enabled()) {
1319 /* Write the bootloader code @ the end of RAM, 1MB reserved */
1320 write_bootloader(memory_region_get_ram_ptr(ram_low_preio
) +
1322 bootloader_run_addr
, kernel_entry
);
1325 target_long bios_size
= FLASH_SIZE
;
1326 /* The flash region isn't executable from a KVM guest */
1327 if (kvm_enabled()) {
1328 error_report("KVM enabled but no -kernel argument was specified. "
1329 "Booting from flash is not supported with KVM.");
1332 /* Load firmware from flash. */
1334 /* Load a BIOS image. */
1335 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
,
1336 bios_name
?: BIOS_FILENAME
);
1338 bios_size
= load_image_targphys(filename
, FLASH_ADDRESS
,
1344 if ((bios_size
< 0 || bios_size
> BIOS_SIZE
) &&
1345 bios_name
&& !qtest_enabled()) {
1346 error_report("Could not load MIPS bios '%s'", bios_name
);
1351 * In little endian mode the 32bit words in the bios are swapped,
1352 * a neat trick which allows bi-endian firmware.
1354 #ifndef TARGET_WORDS_BIGENDIAN
1356 uint32_t *end
, *addr
;
1357 const size_t swapsize
= MIN(bios_size
, 0x3e0000);
1358 addr
= rom_ptr(FLASH_ADDRESS
, swapsize
);
1360 addr
= memory_region_get_ram_ptr(bios
);
1362 end
= (void *)addr
+ swapsize
;
1363 while (addr
< end
) {
1372 * Map the BIOS at a 2nd physical location, as on the real board.
1373 * Copy it so that we can patch in the MIPS revision, which cannot be
1374 * handled by an overlapping region as the resulting ROM code subpage
1375 * regions are not executable.
1377 memory_region_init_ram(bios_copy
, NULL
, "bios.1fc", BIOS_SIZE
,
1379 if (!rom_copy(memory_region_get_ram_ptr(bios_copy
),
1380 FLASH_ADDRESS
, BIOS_SIZE
)) {
1381 memcpy(memory_region_get_ram_ptr(bios_copy
),
1382 memory_region_get_ram_ptr(bios
), BIOS_SIZE
);
1384 memory_region_set_readonly(bios_copy
, true);
1385 memory_region_add_subregion(system_memory
, RESET_ADDRESS
, bios_copy
);
1387 /* Board ID = 0x420 (Malta Board with CoreLV) */
1388 stl_p(memory_region_get_ram_ptr(bios_copy
) + 0x10, 0x00000420);
1391 pci_bus
= gt64120_register(s
->i8259
);
1393 * The whole address space decoded by the GT-64120A doesn't generate
1394 * exception when accessing invalid memory. Create an empty slot to
1395 * emulate this feature.
1397 empty_slot_init("GT64120", 0, 0x20000000);
1400 dev
= piix4_create(pci_bus
, &isa_bus
, &smbus
);
1402 /* Interrupt controller */
1403 qdev_connect_gpio_out_named(dev
, "intr", 0, i8259_irq
);
1404 for (int i
= 0; i
< ISA_NUM_IRQS
; i
++) {
1405 s
->i8259
[i
] = qdev_get_gpio_in_named(dev
, "isa", i
);
1408 /* generate SPD EEPROM data */
1409 generate_eeprom_spd(&smbus_eeprom_buf
[0 * 256], ram_size
);
1410 generate_eeprom_serial(&smbus_eeprom_buf
[6 * 256]);
1411 smbus_eeprom_init(smbus
, 8, smbus_eeprom_buf
, smbus_eeprom_size
);
1412 g_free(smbus_eeprom_buf
);
1414 /* Super I/O: SMS FDC37M817 */
1415 isa_create_simple(isa_bus
, TYPE_FDC37M81X_SUPERIO
);
1418 network_init(pci_bus
);
1420 /* Optional PCI video card */
1421 pci_vga_init(pci_bus
);
1424 static void mips_malta_instance_init(Object
*obj
)
1426 MaltaState
*s
= MIPS_MALTA(obj
);
1428 s
->cpuclk
= qdev_init_clock_out(DEVICE(obj
), "cpu-refclk");
1429 clock_set_hz(s
->cpuclk
, 320000000); /* 320 MHz */
1432 static const TypeInfo mips_malta_device
= {
1433 .name
= TYPE_MIPS_MALTA
,
1434 .parent
= TYPE_SYS_BUS_DEVICE
,
1435 .instance_size
= sizeof(MaltaState
),
1436 .instance_init
= mips_malta_instance_init
,
1439 static void mips_malta_machine_init(MachineClass
*mc
)
1441 mc
->desc
= "MIPS Malta Core LV";
1442 mc
->init
= mips_malta_init
;
1443 mc
->block_default_type
= IF_IDE
;
1445 mc
->is_default
= true;
1446 #ifdef TARGET_MIPS64
1447 mc
->default_cpu_type
= MIPS_CPU_TYPE_NAME("20Kc");
1449 mc
->default_cpu_type
= MIPS_CPU_TYPE_NAME("24Kf");
1451 mc
->default_ram_id
= "mips_malta.ram";
1454 DEFINE_MACHINE("malta", mips_malta_machine_init
)
1456 static void mips_malta_register_types(void)
1458 type_register_static(&mips_malta_device
);
1461 type_init(mips_malta_register_types
)