2 * QEMU Malta board support
4 * Copyright (c) 2006 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu-common.h"
29 #include "hw/southbridge/piix.h"
30 #include "hw/isa/superio.h"
31 #include "hw/char/serial.h"
33 #include "hw/boards.h"
34 #include "hw/i2c/smbus_eeprom.h"
35 #include "hw/block/flash.h"
36 #include "hw/mips/mips.h"
37 #include "hw/mips/cpudevs.h"
38 #include "hw/pci/pci.h"
39 #include "sysemu/sysemu.h"
40 #include "sysemu/arch_init.h"
42 #include "hw/mips/bios.h"
45 #include "hw/loader.h"
47 #include "exec/address-spaces.h"
48 #include "qom/object.h"
49 #include "hw/sysbus.h" /* SysBusDevice */
50 #include "qemu/host-utils.h"
51 #include "sysemu/qtest.h"
52 #include "sysemu/reset.h"
53 #include "sysemu/runstate.h"
54 #include "qapi/error.h"
55 #include "qemu/error-report.h"
56 #include "hw/misc/empty_slot.h"
57 #include "sysemu/kvm.h"
58 #include "hw/semihosting/semihost.h"
59 #include "hw/mips/cps.h"
61 #define ENVP_ADDR 0x80002000l
62 #define ENVP_NB_ENTRIES 16
63 #define ENVP_ENTRY_SIZE 256
65 /* Hardware addresses */
66 #define FLASH_ADDRESS 0x1e000000ULL
67 #define FPGA_ADDRESS 0x1f000000ULL
68 #define RESET_ADDRESS 0x1fc00000ULL
70 #define FLASH_SIZE 0x400000
76 MemoryRegion iomem_lo
; /* 0 - 0x900 */
77 MemoryRegion iomem_hi
; /* 0xa00 - 0x100000 */
91 #define TYPE_MIPS_MALTA "mips-malta"
92 typedef struct MaltaState MaltaState
;
93 DECLARE_INSTANCE_CHECKER(MaltaState
, MIPS_MALTA
,
97 SysBusDevice parent_obj
;
100 qemu_irq i8259
[ISA_NUM_IRQS
];
103 static struct _loaderparams
{
104 int ram_size
, ram_low_size
;
105 const char *kernel_filename
;
106 const char *kernel_cmdline
;
107 const char *initrd_filename
;
111 static void malta_fpga_update_display(void *opaque
)
115 MaltaFPGAState
*s
= opaque
;
117 for (i
= 7 ; i
>= 0 ; i
--) {
118 if (s
->leds
& (1 << i
)) {
126 qemu_chr_fe_printf(&s
->display
, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
128 qemu_chr_fe_printf(&s
->display
, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
133 * EEPROM 24C01 / 24C02 emulation.
135 * Emulation for serial EEPROMs:
136 * 24C01 - 1024 bit (128 x 8)
137 * 24C02 - 2048 bit (256 x 8)
139 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
143 # define logout(fmt, ...) \
144 fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
146 # define logout(fmt, ...) ((void)0)
149 struct _eeprom24c0x_t
{
158 uint8_t contents
[256];
161 typedef struct _eeprom24c0x_t eeprom24c0x_t
;
163 static eeprom24c0x_t spd_eeprom
= {
166 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
168 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
170 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
172 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
174 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
176 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
178 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
180 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
182 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
184 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
186 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
188 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
190 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
192 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
196 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
200 static void generate_eeprom_spd(uint8_t *eeprom
, ram_addr_t ram_size
)
202 enum { SDR
= 0x4, DDR2
= 0x8 } type
;
203 uint8_t *spd
= spd_eeprom
.contents
;
205 uint16_t density
= 0;
208 /* work in terms of MB */
211 while ((ram_size
>= 4) && (nbanks
<= 2)) {
212 int sz_log2
= MIN(31 - clz32(ram_size
), 14);
214 density
|= 1 << (sz_log2
- 2);
215 ram_size
-= 1 << sz_log2
;
218 /* split to 2 banks if possible */
219 if ((nbanks
== 1) && (density
> 1)) {
224 if (density
& 0xff00) {
225 density
= (density
& 0xe0) | ((density
>> 8) & 0x1f);
227 } else if (!(density
& 0x1f)) {
234 warn_report("SPD cannot represent final " RAM_ADDR_FMT
"MB"
235 " of SDRAM", ram_size
);
238 /* fill in SPD memory information */
245 for (i
= 0; i
< 63; i
++) {
250 memcpy(eeprom
, spd
, sizeof(spd_eeprom
.contents
));
253 static void generate_eeprom_serial(uint8_t *eeprom
)
256 uint8_t mac
[6] = { 0x00 };
257 uint8_t sn
[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
260 eeprom
[pos
++] = 0x01;
263 eeprom
[pos
++] = 0x02;
266 eeprom
[pos
++] = 0x01; /* MAC */
267 eeprom
[pos
++] = 0x06; /* length */
268 memcpy(&eeprom
[pos
], mac
, sizeof(mac
));
272 eeprom
[pos
++] = 0x02; /* serial */
273 eeprom
[pos
++] = 0x05; /* length */
274 memcpy(&eeprom
[pos
], sn
, sizeof(sn
));
279 for (i
= 0; i
< pos
; i
++) {
280 eeprom
[pos
] += eeprom
[i
];
284 static uint8_t eeprom24c0x_read(eeprom24c0x_t
*eeprom
)
286 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
287 eeprom
->tick
, eeprom
->scl
, eeprom
->sda
, eeprom
->data
);
291 static void eeprom24c0x_write(eeprom24c0x_t
*eeprom
, int scl
, int sda
)
293 if (eeprom
->scl
&& scl
&& (eeprom
->sda
!= sda
)) {
294 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
295 eeprom
->tick
, eeprom
->scl
, scl
, eeprom
->sda
, sda
,
296 sda
? "stop" : "start");
301 } else if (eeprom
->tick
== 0 && !eeprom
->ack
) {
302 /* Waiting for start. */
303 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
304 eeprom
->tick
, eeprom
->scl
, scl
, eeprom
->sda
, sda
);
305 } else if (!eeprom
->scl
&& scl
) {
306 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
307 eeprom
->tick
, eeprom
->scl
, scl
, eeprom
->sda
, sda
);
309 logout("\ti2c ack bit = 0\n");
312 } else if (eeprom
->sda
== sda
) {
313 uint8_t bit
= (sda
!= 0);
314 logout("\ti2c bit = %d\n", bit
);
315 if (eeprom
->tick
< 9) {
316 eeprom
->command
<<= 1;
317 eeprom
->command
+= bit
;
319 if (eeprom
->tick
== 9) {
320 logout("\tcommand 0x%04x, %s\n", eeprom
->command
,
321 bit
? "read" : "write");
324 } else if (eeprom
->tick
< 17) {
325 if (eeprom
->command
& 1) {
326 sda
= ((eeprom
->data
& 0x80) != 0);
328 eeprom
->address
<<= 1;
329 eeprom
->address
+= bit
;
332 if (eeprom
->tick
== 17) {
333 eeprom
->data
= eeprom
->contents
[eeprom
->address
];
334 logout("\taddress 0x%04x, data 0x%02x\n",
335 eeprom
->address
, eeprom
->data
);
339 } else if (eeprom
->tick
>= 17) {
343 logout("\tsda changed with raising scl\n");
346 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom
->tick
, eeprom
->scl
,
347 scl
, eeprom
->sda
, sda
);
353 static uint64_t malta_fpga_read(void *opaque
, hwaddr addr
,
356 MaltaFPGAState
*s
= opaque
;
360 saddr
= (addr
& 0xfffff);
364 /* SWITCH Register */
369 /* STATUS Register */
371 #ifdef TARGET_WORDS_BIGENDIAN
383 /* LEDBAR Register */
388 /* BRKRES Register */
393 /* UART Registers are handled directly by the serial device */
400 /* XXX: implement a real I2C controller */
404 /* IN = OUT until a real I2C control is implemented */
412 /* I2CINP Register */
414 val
= ((s
->i2cin
& ~1) | eeprom24c0x_read(&spd_eeprom
));
422 /* I2COUT Register */
427 /* I2CSEL Register */
433 qemu_log_mask(LOG_GUEST_ERROR
,
434 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX
"\n",
441 static void malta_fpga_write(void *opaque
, hwaddr addr
,
442 uint64_t val
, unsigned size
)
444 MaltaFPGAState
*s
= opaque
;
447 saddr
= (addr
& 0xfffff);
451 /* SWITCH Register */
459 /* LEDBAR Register */
461 s
->leds
= val
& 0xff;
462 malta_fpga_update_display(s
);
465 /* ASCIIWORD Register */
467 snprintf(s
->display_text
, 9, "%08X", (uint32_t)val
);
468 malta_fpga_update_display(s
);
471 /* ASCIIPOS0 to ASCIIPOS7 Registers */
480 s
->display_text
[(saddr
- 0x00418) >> 3] = (char) val
;
481 malta_fpga_update_display(s
);
484 /* SOFTRES Register */
487 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
491 /* BRKRES Register */
496 /* UART Registers are handled directly by the serial device */
500 s
->gpout
= val
& 0xff;
505 s
->i2coe
= val
& 0x03;
508 /* I2COUT Register */
510 eeprom24c0x_write(&spd_eeprom
, val
& 0x02, val
& 0x01);
514 /* I2CSEL Register */
516 s
->i2csel
= val
& 0x01;
520 qemu_log_mask(LOG_GUEST_ERROR
,
521 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX
"\n",
527 static const MemoryRegionOps malta_fpga_ops
= {
528 .read
= malta_fpga_read
,
529 .write
= malta_fpga_write
,
530 .endianness
= DEVICE_NATIVE_ENDIAN
,
533 static void malta_fpga_reset(void *opaque
)
535 MaltaFPGAState
*s
= opaque
;
545 s
->display_text
[8] = '\0';
546 snprintf(s
->display_text
, 9, " ");
549 static void malta_fgpa_display_event(void *opaque
, QEMUChrEvent event
)
551 MaltaFPGAState
*s
= opaque
;
553 if (event
== CHR_EVENT_OPENED
&& !s
->display_inited
) {
554 qemu_chr_fe_printf(&s
->display
, "\e[HMalta LEDBAR\r\n");
555 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
556 qemu_chr_fe_printf(&s
->display
, "+ +\r\n");
557 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
558 qemu_chr_fe_printf(&s
->display
, "\n");
559 qemu_chr_fe_printf(&s
->display
, "Malta ASCII\r\n");
560 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
561 qemu_chr_fe_printf(&s
->display
, "+ +\r\n");
562 qemu_chr_fe_printf(&s
->display
, "+--------+\r\n");
563 s
->display_inited
= true;
567 static MaltaFPGAState
*malta_fpga_init(MemoryRegion
*address_space
,
568 hwaddr base
, qemu_irq uart_irq
, Chardev
*uart_chr
)
573 s
= g_new0(MaltaFPGAState
, 1);
575 memory_region_init_io(&s
->iomem
, NULL
, &malta_fpga_ops
, s
,
576 "malta-fpga", 0x100000);
577 memory_region_init_alias(&s
->iomem_lo
, NULL
, "malta-fpga",
578 &s
->iomem
, 0, 0x900);
579 memory_region_init_alias(&s
->iomem_hi
, NULL
, "malta-fpga",
580 &s
->iomem
, 0xa00, 0x10000 - 0xa00);
582 memory_region_add_subregion(address_space
, base
, &s
->iomem_lo
);
583 memory_region_add_subregion(address_space
, base
+ 0xa00, &s
->iomem_hi
);
585 chr
= qemu_chr_new("fpga", "vc:320x200", NULL
);
586 qemu_chr_fe_init(&s
->display
, chr
, NULL
);
587 qemu_chr_fe_set_handlers(&s
->display
, NULL
, NULL
,
588 malta_fgpa_display_event
, NULL
, s
, NULL
, true);
590 s
->uart
= serial_mm_init(address_space
, base
+ 0x900, 3, uart_irq
,
591 230400, uart_chr
, DEVICE_NATIVE_ENDIAN
);
594 qemu_register_reset(malta_fpga_reset
, s
);
599 /* Network support */
600 static void network_init(PCIBus
*pci_bus
)
604 for (i
= 0; i
< nb_nics
; i
++) {
605 NICInfo
*nd
= &nd_table
[i
];
606 const char *default_devaddr
= NULL
;
608 if (i
== 0 && (!nd
->model
|| strcmp(nd
->model
, "pcnet") == 0))
609 /* The malta board has a PCNet card using PCI SLOT 11 */
610 default_devaddr
= "0b";
612 pci_nic_init_nofail(nd
, pci_bus
, "pcnet", default_devaddr
);
616 static void write_bootloader_nanomips(uint8_t *base
, int64_t run_addr
,
617 int64_t kernel_entry
)
621 /* Small bootloader */
622 p
= (uint16_t *)base
;
624 #define NM_HI1(VAL) (((VAL) >> 16) & 0x1f)
625 #define NM_HI2(VAL) \
626 (((VAL) & 0xf000) | (((VAL) >> 19) & 0xffc) | (((VAL) >> 31) & 0x1))
627 #define NM_LO(VAL) ((VAL) & 0xfff)
629 stw_p(p
++, 0x2800); stw_p(p
++, 0x001c);
631 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
633 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
635 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
637 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
639 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
641 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
643 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
647 if (semihosting_get_argc()) {
648 /* Preserve a0 content as arguments have been passed */
649 stw_p(p
++, 0x8000); stw_p(p
++, 0xc000);
652 stw_p(p
++, 0x0080); stw_p(p
++, 0x0002);
656 stw_p(p
++, 0xe3a0 | NM_HI1(ENVP_ADDR
- 64));
658 stw_p(p
++, NM_HI2(ENVP_ADDR
- 64));
659 /* lui sp,%hi(ENVP_ADDR - 64) */
661 stw_p(p
++, 0x83bd); stw_p(p
++, NM_LO(ENVP_ADDR
- 64));
662 /* ori sp,sp,%lo(ENVP_ADDR - 64) */
664 stw_p(p
++, 0xe0a0 | NM_HI1(ENVP_ADDR
));
666 stw_p(p
++, NM_HI2(ENVP_ADDR
));
667 /* lui a1,%hi(ENVP_ADDR) */
669 stw_p(p
++, 0x80a5); stw_p(p
++, NM_LO(ENVP_ADDR
));
670 /* ori a1,a1,%lo(ENVP_ADDR) */
672 stw_p(p
++, 0xe0c0 | NM_HI1(ENVP_ADDR
+ 8));
674 stw_p(p
++, NM_HI2(ENVP_ADDR
+ 8));
675 /* lui a2,%hi(ENVP_ADDR + 8) */
677 stw_p(p
++, 0x80c6); stw_p(p
++, NM_LO(ENVP_ADDR
+ 8));
678 /* ori a2,a2,%lo(ENVP_ADDR + 8) */
680 stw_p(p
++, 0xe0e0 | NM_HI1(loaderparams
.ram_low_size
));
682 stw_p(p
++, NM_HI2(loaderparams
.ram_low_size
));
683 /* lui a3,%hi(loaderparams.ram_low_size) */
685 stw_p(p
++, 0x80e7); stw_p(p
++, NM_LO(loaderparams
.ram_low_size
));
686 /* ori a3,a3,%lo(loaderparams.ram_low_size) */
689 * Load BAR registers as done by YAMON:
691 * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
692 * - set up PCI0 MEM0 at 0x10000000, size 0x8000000
693 * - set up PCI0 MEM1 at 0x18200000, size 0xbe00000
696 stw_p(p
++, 0xe040); stw_p(p
++, 0x0681);
697 /* lui t1, %hi(0xb4000000) */
699 #ifdef TARGET_WORDS_BIGENDIAN
701 stw_p(p
++, 0xe020); stw_p(p
++, 0x0be1);
702 /* lui t0, %hi(0xdf000000) */
704 /* 0x68 corresponds to GT_ISD (from hw/mips/gt64xxx_pci.c) */
705 stw_p(p
++, 0x8422); stw_p(p
++, 0x9068);
706 /* sw t0, 0x68(t1) */
708 stw_p(p
++, 0xe040); stw_p(p
++, 0x077d);
709 /* lui t1, %hi(0xbbe00000) */
711 stw_p(p
++, 0xe020); stw_p(p
++, 0x0801);
712 /* lui t0, %hi(0xc0000000) */
714 /* 0x48 corresponds to GT_PCI0IOLD */
715 stw_p(p
++, 0x8422); stw_p(p
++, 0x9048);
716 /* sw t0, 0x48(t1) */
718 stw_p(p
++, 0xe020); stw_p(p
++, 0x0800);
719 /* lui t0, %hi(0x40000000) */
721 /* 0x50 corresponds to GT_PCI0IOHD */
722 stw_p(p
++, 0x8422); stw_p(p
++, 0x9050);
723 /* sw t0, 0x50(t1) */
725 stw_p(p
++, 0xe020); stw_p(p
++, 0x0001);
726 /* lui t0, %hi(0x80000000) */
728 /* 0x58 corresponds to GT_PCI0M0LD */
729 stw_p(p
++, 0x8422); stw_p(p
++, 0x9058);
730 /* sw t0, 0x58(t1) */
732 stw_p(p
++, 0xe020); stw_p(p
++, 0x07e0);
733 /* lui t0, %hi(0x3f000000) */
735 /* 0x60 corresponds to GT_PCI0M0HD */
736 stw_p(p
++, 0x8422); stw_p(p
++, 0x9060);
737 /* sw t0, 0x60(t1) */
739 stw_p(p
++, 0xe020); stw_p(p
++, 0x0821);
740 /* lui t0, %hi(0xc1000000) */
742 /* 0x80 corresponds to GT_PCI0M1LD */
743 stw_p(p
++, 0x8422); stw_p(p
++, 0x9080);
744 /* sw t0, 0x80(t1) */
746 stw_p(p
++, 0xe020); stw_p(p
++, 0x0bc0);
747 /* lui t0, %hi(0x5e000000) */
751 stw_p(p
++, 0x0020); stw_p(p
++, 0x00df);
752 /* addiu[32] t0, $0, 0xdf */
754 /* 0x68 corresponds to GT_ISD */
755 stw_p(p
++, 0x8422); stw_p(p
++, 0x9068);
756 /* sw t0, 0x68(t1) */
758 /* Use kseg2 remapped address 0x1be00000 */
759 stw_p(p
++, 0xe040); stw_p(p
++, 0x077d);
760 /* lui t1, %hi(0xbbe00000) */
762 stw_p(p
++, 0x0020); stw_p(p
++, 0x00c0);
763 /* addiu[32] t0, $0, 0xc0 */
765 /* 0x48 corresponds to GT_PCI0IOLD */
766 stw_p(p
++, 0x8422); stw_p(p
++, 0x9048);
767 /* sw t0, 0x48(t1) */
769 stw_p(p
++, 0x0020); stw_p(p
++, 0x0040);
770 /* addiu[32] t0, $0, 0x40 */
772 /* 0x50 corresponds to GT_PCI0IOHD */
773 stw_p(p
++, 0x8422); stw_p(p
++, 0x9050);
774 /* sw t0, 0x50(t1) */
776 stw_p(p
++, 0x0020); stw_p(p
++, 0x0080);
777 /* addiu[32] t0, $0, 0x80 */
779 /* 0x58 corresponds to GT_PCI0M0LD */
780 stw_p(p
++, 0x8422); stw_p(p
++, 0x9058);
781 /* sw t0, 0x58(t1) */
783 stw_p(p
++, 0x0020); stw_p(p
++, 0x003f);
784 /* addiu[32] t0, $0, 0x3f */
786 /* 0x60 corresponds to GT_PCI0M0HD */
787 stw_p(p
++, 0x8422); stw_p(p
++, 0x9060);
788 /* sw t0, 0x60(t1) */
790 stw_p(p
++, 0x0020); stw_p(p
++, 0x00c1);
791 /* addiu[32] t0, $0, 0xc1 */
793 /* 0x80 corresponds to GT_PCI0M1LD */
794 stw_p(p
++, 0x8422); stw_p(p
++, 0x9080);
795 /* sw t0, 0x80(t1) */
797 stw_p(p
++, 0x0020); stw_p(p
++, 0x005e);
798 /* addiu[32] t0, $0, 0x5e */
802 /* 0x88 corresponds to GT_PCI0M1HD */
803 stw_p(p
++, 0x8422); stw_p(p
++, 0x9088);
804 /* sw t0, 0x88(t1) */
806 stw_p(p
++, 0xe320 | NM_HI1(kernel_entry
));
808 stw_p(p
++, NM_HI2(kernel_entry
));
809 /* lui t9,%hi(kernel_entry) */
811 stw_p(p
++, 0x8339); stw_p(p
++, NM_LO(kernel_entry
));
812 /* ori t9,t9,%lo(kernel_entry) */
814 stw_p(p
++, 0x4bf9); stw_p(p
++, 0x0000);
819 * ROM and pseudo bootloader
821 * The following code implements a very very simple bootloader. It first
822 * loads the registers a0 to a3 to the values expected by the OS, and
823 * then jump at the kernel address.
825 * The bootloader should pass the locations of the kernel arguments and
826 * environment variables tables. Those tables contain the 32-bit address
827 * of NULL terminated strings. The environment variables table should be
828 * terminated by a NULL address.
830 * For a simpler implementation, the number of kernel arguments is fixed
831 * to two (the name of the kernel and the command line), and the two
832 * tables are actually the same one.
834 * The registers a0 to a3 should contain the following values:
835 * a0 - number of kernel arguments
836 * a1 - 32-bit address of the kernel arguments table
837 * a2 - 32-bit address of the environment variables table
838 * a3 - RAM size in bytes
840 static void write_bootloader(uint8_t *base
, int64_t run_addr
,
841 int64_t kernel_entry
)
845 /* Small bootloader */
846 p
= (uint32_t *)base
;
848 stl_p(p
++, 0x08000000 | /* j 0x1fc00580 */
849 ((run_addr
+ 0x580) & 0x0fffffff) >> 2);
850 stl_p(p
++, 0x00000000); /* nop */
852 /* YAMON service vector */
853 stl_p(base
+ 0x500, run_addr
+ 0x0580); /* start: */
854 stl_p(base
+ 0x504, run_addr
+ 0x083c); /* print_count: */
855 stl_p(base
+ 0x520, run_addr
+ 0x0580); /* start: */
856 stl_p(base
+ 0x52c, run_addr
+ 0x0800); /* flush_cache: */
857 stl_p(base
+ 0x534, run_addr
+ 0x0808); /* print: */
858 stl_p(base
+ 0x538, run_addr
+ 0x0800); /* reg_cpu_isr: */
859 stl_p(base
+ 0x53c, run_addr
+ 0x0800); /* unred_cpu_isr: */
860 stl_p(base
+ 0x540, run_addr
+ 0x0800); /* reg_ic_isr: */
861 stl_p(base
+ 0x544, run_addr
+ 0x0800); /* unred_ic_isr: */
862 stl_p(base
+ 0x548, run_addr
+ 0x0800); /* reg_esr: */
863 stl_p(base
+ 0x54c, run_addr
+ 0x0800); /* unreg_esr: */
864 stl_p(base
+ 0x550, run_addr
+ 0x0800); /* getchar: */
865 stl_p(base
+ 0x554, run_addr
+ 0x0800); /* syscon_read: */
868 /* Second part of the bootloader */
869 p
= (uint32_t *) (base
+ 0x580);
871 if (semihosting_get_argc()) {
872 /* Preserve a0 content as arguments have been passed */
873 stl_p(p
++, 0x00000000); /* nop */
875 stl_p(p
++, 0x24040002); /* addiu a0, zero, 2 */
878 /* lui sp, high(ENVP_ADDR) */
879 stl_p(p
++, 0x3c1d0000 | (((ENVP_ADDR
- 64) >> 16) & 0xffff));
880 /* ori sp, sp, low(ENVP_ADDR) */
881 stl_p(p
++, 0x37bd0000 | ((ENVP_ADDR
- 64) & 0xffff));
882 /* lui a1, high(ENVP_ADDR) */
883 stl_p(p
++, 0x3c050000 | ((ENVP_ADDR
>> 16) & 0xffff));
884 /* ori a1, a1, low(ENVP_ADDR) */
885 stl_p(p
++, 0x34a50000 | (ENVP_ADDR
& 0xffff));
886 /* lui a2, high(ENVP_ADDR + 8) */
887 stl_p(p
++, 0x3c060000 | (((ENVP_ADDR
+ 8) >> 16) & 0xffff));
888 /* ori a2, a2, low(ENVP_ADDR + 8) */
889 stl_p(p
++, 0x34c60000 | ((ENVP_ADDR
+ 8) & 0xffff));
890 /* lui a3, high(ram_low_size) */
891 stl_p(p
++, 0x3c070000 | (loaderparams
.ram_low_size
>> 16));
892 /* ori a3, a3, low(ram_low_size) */
893 stl_p(p
++, 0x34e70000 | (loaderparams
.ram_low_size
& 0xffff));
895 /* Load BAR registers as done by YAMON */
896 stl_p(p
++, 0x3c09b400); /* lui t1, 0xb400 */
898 #ifdef TARGET_WORDS_BIGENDIAN
899 stl_p(p
++, 0x3c08df00); /* lui t0, 0xdf00 */
901 stl_p(p
++, 0x340800df); /* ori t0, r0, 0x00df */
903 stl_p(p
++, 0xad280068); /* sw t0, 0x0068(t1) */
905 stl_p(p
++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
907 #ifdef TARGET_WORDS_BIGENDIAN
908 stl_p(p
++, 0x3c08c000); /* lui t0, 0xc000 */
910 stl_p(p
++, 0x340800c0); /* ori t0, r0, 0x00c0 */
912 stl_p(p
++, 0xad280048); /* sw t0, 0x0048(t1) */
913 #ifdef TARGET_WORDS_BIGENDIAN
914 stl_p(p
++, 0x3c084000); /* lui t0, 0x4000 */
916 stl_p(p
++, 0x34080040); /* ori t0, r0, 0x0040 */
918 stl_p(p
++, 0xad280050); /* sw t0, 0x0050(t1) */
920 #ifdef TARGET_WORDS_BIGENDIAN
921 stl_p(p
++, 0x3c088000); /* lui t0, 0x8000 */
923 stl_p(p
++, 0x34080080); /* ori t0, r0, 0x0080 */
925 stl_p(p
++, 0xad280058); /* sw t0, 0x0058(t1) */
926 #ifdef TARGET_WORDS_BIGENDIAN
927 stl_p(p
++, 0x3c083f00); /* lui t0, 0x3f00 */
929 stl_p(p
++, 0x3408003f); /* ori t0, r0, 0x003f */
931 stl_p(p
++, 0xad280060); /* sw t0, 0x0060(t1) */
933 #ifdef TARGET_WORDS_BIGENDIAN
934 stl_p(p
++, 0x3c08c100); /* lui t0, 0xc100 */
936 stl_p(p
++, 0x340800c1); /* ori t0, r0, 0x00c1 */
938 stl_p(p
++, 0xad280080); /* sw t0, 0x0080(t1) */
939 #ifdef TARGET_WORDS_BIGENDIAN
940 stl_p(p
++, 0x3c085e00); /* lui t0, 0x5e00 */
942 stl_p(p
++, 0x3408005e); /* ori t0, r0, 0x005e */
944 stl_p(p
++, 0xad280088); /* sw t0, 0x0088(t1) */
946 /* Jump to kernel code */
947 stl_p(p
++, 0x3c1f0000 |
948 ((kernel_entry
>> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
949 stl_p(p
++, 0x37ff0000 |
950 (kernel_entry
& 0xffff)); /* ori ra, ra, low(kernel_entry) */
951 stl_p(p
++, 0x03e00009); /* jalr ra */
952 stl_p(p
++, 0x00000000); /* nop */
954 /* YAMON subroutines */
955 p
= (uint32_t *) (base
+ 0x800);
956 stl_p(p
++, 0x03e00009); /* jalr ra */
957 stl_p(p
++, 0x24020000); /* li v0,0 */
958 /* 808 YAMON print */
959 stl_p(p
++, 0x03e06821); /* move t5,ra */
960 stl_p(p
++, 0x00805821); /* move t3,a0 */
961 stl_p(p
++, 0x00a05021); /* move t2,a1 */
962 stl_p(p
++, 0x91440000); /* lbu a0,0(t2) */
963 stl_p(p
++, 0x254a0001); /* addiu t2,t2,1 */
964 stl_p(p
++, 0x10800005); /* beqz a0,834 */
965 stl_p(p
++, 0x00000000); /* nop */
966 stl_p(p
++, 0x0ff0021c); /* jal 870 */
967 stl_p(p
++, 0x00000000); /* nop */
968 stl_p(p
++, 0x1000fff9); /* b 814 */
969 stl_p(p
++, 0x00000000); /* nop */
970 stl_p(p
++, 0x01a00009); /* jalr t5 */
971 stl_p(p
++, 0x01602021); /* move a0,t3 */
972 /* 0x83c YAMON print_count */
973 stl_p(p
++, 0x03e06821); /* move t5,ra */
974 stl_p(p
++, 0x00805821); /* move t3,a0 */
975 stl_p(p
++, 0x00a05021); /* move t2,a1 */
976 stl_p(p
++, 0x00c06021); /* move t4,a2 */
977 stl_p(p
++, 0x91440000); /* lbu a0,0(t2) */
978 stl_p(p
++, 0x0ff0021c); /* jal 870 */
979 stl_p(p
++, 0x00000000); /* nop */
980 stl_p(p
++, 0x254a0001); /* addiu t2,t2,1 */
981 stl_p(p
++, 0x258cffff); /* addiu t4,t4,-1 */
982 stl_p(p
++, 0x1580fffa); /* bnez t4,84c */
983 stl_p(p
++, 0x00000000); /* nop */
984 stl_p(p
++, 0x01a00009); /* jalr t5 */
985 stl_p(p
++, 0x01602021); /* move a0,t3 */
987 stl_p(p
++, 0x3c08b800); /* lui t0,0xb400 */
988 stl_p(p
++, 0x350803f8); /* ori t0,t0,0x3f8 */
989 stl_p(p
++, 0x91090005); /* lbu t1,5(t0) */
990 stl_p(p
++, 0x00000000); /* nop */
991 stl_p(p
++, 0x31290040); /* andi t1,t1,0x40 */
992 stl_p(p
++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
993 stl_p(p
++, 0x00000000); /* nop */
994 stl_p(p
++, 0x03e00009); /* jalr ra */
995 stl_p(p
++, 0xa1040000); /* sb a0,0(t0) */
999 static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf
, int index
,
1000 const char *string
, ...)
1005 if (index
>= ENVP_NB_ENTRIES
) {
1009 if (string
== NULL
) {
1010 prom_buf
[index
] = 0;
1014 table_addr
= sizeof(int32_t) * ENVP_NB_ENTRIES
+ index
* ENVP_ENTRY_SIZE
;
1015 prom_buf
[index
] = tswap32(ENVP_ADDR
+ table_addr
);
1017 va_start(ap
, string
);
1018 vsnprintf((char *)prom_buf
+ table_addr
, ENVP_ENTRY_SIZE
, string
, ap
);
1023 static int64_t load_kernel(void)
1025 int64_t kernel_entry
, kernel_high
, initrd_size
;
1027 ram_addr_t initrd_offset
;
1032 uint64_t (*xlate_to_kseg0
) (void *opaque
, uint64_t addr
);
1034 #ifdef TARGET_WORDS_BIGENDIAN
1040 kernel_size
= load_elf(loaderparams
.kernel_filename
, NULL
,
1041 cpu_mips_kseg0_to_phys
, NULL
,
1042 (uint64_t *)&kernel_entry
, NULL
,
1043 (uint64_t *)&kernel_high
, NULL
, big_endian
, EM_MIPS
,
1045 if (kernel_size
< 0) {
1046 error_report("could not load kernel '%s': %s",
1047 loaderparams
.kernel_filename
,
1048 load_elf_strerror(kernel_size
));
1052 /* Check where the kernel has been linked */
1053 if (kernel_entry
& 0x80000000ll
) {
1054 if (kvm_enabled()) {
1055 error_report("KVM guest kernels must be linked in useg. "
1056 "Did you forget to enable CONFIG_KVM_GUEST?");
1060 xlate_to_kseg0
= cpu_mips_phys_to_kseg0
;
1062 /* if kernel entry is in useg it is probably a KVM T&E kernel */
1063 mips_um_ksegs_enable();
1065 xlate_to_kseg0
= cpu_mips_kvm_um_phys_to_kseg0
;
1071 if (loaderparams
.initrd_filename
) {
1072 initrd_size
= get_image_size(loaderparams
.initrd_filename
);
1073 if (initrd_size
> 0) {
1075 * The kernel allocates the bootmap memory in the low memory after
1076 * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
1079 initrd_offset
= (loaderparams
.ram_low_size
- initrd_size
1081 - ~INITRD_PAGE_MASK
) & INITRD_PAGE_MASK
;
1082 if (kernel_high
>= initrd_offset
) {
1083 error_report("memory too small for initial ram disk '%s'",
1084 loaderparams
.initrd_filename
);
1087 initrd_size
= load_image_targphys(loaderparams
.initrd_filename
,
1089 ram_size
- initrd_offset
);
1091 if (initrd_size
== (target_ulong
) -1) {
1092 error_report("could not load initial ram disk '%s'",
1093 loaderparams
.initrd_filename
);
1098 /* Setup prom parameters. */
1099 prom_size
= ENVP_NB_ENTRIES
* (sizeof(int32_t) + ENVP_ENTRY_SIZE
);
1100 prom_buf
= g_malloc(prom_size
);
1102 prom_set(prom_buf
, prom_index
++, "%s", loaderparams
.kernel_filename
);
1103 if (initrd_size
> 0) {
1104 prom_set(prom_buf
, prom_index
++,
1105 "rd_start=0x%" PRIx64
" rd_size=%" PRId64
" %s",
1106 xlate_to_kseg0(NULL
, initrd_offset
),
1107 initrd_size
, loaderparams
.kernel_cmdline
);
1109 prom_set(prom_buf
, prom_index
++, "%s", loaderparams
.kernel_cmdline
);
1112 prom_set(prom_buf
, prom_index
++, "memsize");
1113 prom_set(prom_buf
, prom_index
++, "%u", loaderparams
.ram_low_size
);
1115 prom_set(prom_buf
, prom_index
++, "ememsize");
1116 prom_set(prom_buf
, prom_index
++, "%u", loaderparams
.ram_size
);
1118 prom_set(prom_buf
, prom_index
++, "modetty0");
1119 prom_set(prom_buf
, prom_index
++, "38400n8r");
1120 prom_set(prom_buf
, prom_index
++, NULL
);
1122 rom_add_blob_fixed("prom", prom_buf
, prom_size
,
1123 cpu_mips_kseg0_to_phys(NULL
, ENVP_ADDR
));
1126 return kernel_entry
;
1129 static void malta_mips_config(MIPSCPU
*cpu
)
1131 MachineState
*ms
= MACHINE(qdev_get_machine());
1132 unsigned int smp_cpus
= ms
->smp
.cpus
;
1133 CPUMIPSState
*env
= &cpu
->env
;
1134 CPUState
*cs
= CPU(cpu
);
1136 env
->mvp
->CP0_MVPConf0
|= ((smp_cpus
- 1) << CP0MVPC0_PVPE
) |
1137 ((smp_cpus
* cs
->nr_threads
- 1) << CP0MVPC0_PTC
);
1140 static void main_cpu_reset(void *opaque
)
1142 MIPSCPU
*cpu
= opaque
;
1143 CPUMIPSState
*env
= &cpu
->env
;
1145 cpu_reset(CPU(cpu
));
1148 * The bootloader does not need to be rewritten as it is located in a
1149 * read only location. The kernel location and the arguments table
1150 * location does not change.
1152 if (loaderparams
.kernel_filename
) {
1153 env
->CP0_Status
&= ~(1 << CP0St_ERL
);
1156 malta_mips_config(cpu
);
1158 if (kvm_enabled()) {
1159 /* Start running from the bootloader we wrote to end of RAM */
1160 env
->active_tc
.PC
= 0x40000000 + loaderparams
.ram_low_size
;
1164 static void create_cpu_without_cps(MachineState
*ms
,
1165 qemu_irq
*cbus_irq
, qemu_irq
*i8259_irq
)
1171 for (i
= 0; i
< ms
->smp
.cpus
; i
++) {
1172 cpu
= MIPS_CPU(cpu_create(ms
->cpu_type
));
1174 /* Init internal devices */
1175 cpu_mips_irq_init_cpu(cpu
);
1176 cpu_mips_clock_init(cpu
);
1177 qemu_register_reset(main_cpu_reset
, cpu
);
1180 cpu
= MIPS_CPU(first_cpu
);
1182 *i8259_irq
= env
->irq
[2];
1183 *cbus_irq
= env
->irq
[4];
1186 static void create_cps(MachineState
*ms
, MaltaState
*s
,
1187 qemu_irq
*cbus_irq
, qemu_irq
*i8259_irq
)
1189 object_initialize_child(OBJECT(s
), "cps", &s
->cps
, TYPE_MIPS_CPS
);
1190 object_property_set_str(OBJECT(&s
->cps
), "cpu-type", ms
->cpu_type
,
1192 object_property_set_int(OBJECT(&s
->cps
), "num-vp", ms
->smp
.cpus
,
1194 sysbus_realize(SYS_BUS_DEVICE(&s
->cps
), &error_fatal
);
1196 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s
->cps
), 0, 0, 1);
1198 *i8259_irq
= get_cps_irq(&s
->cps
, 3);
1202 static void mips_create_cpu(MachineState
*ms
, MaltaState
*s
,
1203 qemu_irq
*cbus_irq
, qemu_irq
*i8259_irq
)
1205 if ((ms
->smp
.cpus
> 1) && cpu_supports_cps_smp(ms
->cpu_type
)) {
1206 create_cps(ms
, s
, cbus_irq
, i8259_irq
);
1208 create_cpu_without_cps(ms
, cbus_irq
, i8259_irq
);
1213 void mips_malta_init(MachineState
*machine
)
1215 ram_addr_t ram_size
= machine
->ram_size
;
1216 ram_addr_t ram_low_size
;
1217 const char *kernel_filename
= machine
->kernel_filename
;
1218 const char *kernel_cmdline
= machine
->kernel_cmdline
;
1219 const char *initrd_filename
= machine
->initrd_filename
;
1222 MemoryRegion
*system_memory
= get_system_memory();
1223 MemoryRegion
*ram_low_preio
= g_new(MemoryRegion
, 1);
1224 MemoryRegion
*ram_low_postio
;
1225 MemoryRegion
*bios
, *bios_copy
= g_new(MemoryRegion
, 1);
1226 const size_t smbus_eeprom_size
= 8 * 256;
1227 uint8_t *smbus_eeprom_buf
= g_malloc0(smbus_eeprom_size
);
1228 int64_t kernel_entry
, bootloader_run_addr
;
1231 qemu_irq cbus_irq
, i8259_irq
;
1237 DeviceState
*dev
= qdev_new(TYPE_MIPS_MALTA
);
1238 MaltaState
*s
= MIPS_MALTA(dev
);
1241 * The whole address space decoded by the GT-64120A doesn't generate
1242 * exception when accessing invalid memory. Create an empty slot to
1243 * emulate this feature.
1245 empty_slot_init("GT64120", 0, 0x20000000);
1247 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
1250 mips_create_cpu(machine
, s
, &cbus_irq
, &i8259_irq
);
1253 if (ram_size
> 2 * GiB
) {
1254 error_report("Too much memory for this machine: %" PRId64
"MB,"
1255 " maximum 2048MB", ram_size
/ MiB
);
1259 /* register RAM at high address where it is undisturbed by IO */
1260 memory_region_add_subregion(system_memory
, 0x80000000, machine
->ram
);
1262 /* alias for pre IO hole access */
1263 memory_region_init_alias(ram_low_preio
, NULL
, "mips_malta_low_preio.ram",
1264 machine
->ram
, 0, MIN(ram_size
, 256 * MiB
));
1265 memory_region_add_subregion(system_memory
, 0, ram_low_preio
);
1267 /* alias for post IO hole access, if there is enough RAM */
1268 if (ram_size
> 512 * MiB
) {
1269 ram_low_postio
= g_new(MemoryRegion
, 1);
1270 memory_region_init_alias(ram_low_postio
, NULL
,
1271 "mips_malta_low_postio.ram",
1272 machine
->ram
, 512 * MiB
,
1273 ram_size
- 512 * MiB
);
1274 memory_region_add_subregion(system_memory
, 512 * MiB
,
1278 #ifdef TARGET_WORDS_BIGENDIAN
1286 /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
1287 malta_fpga_init(system_memory
, FPGA_ADDRESS
, cbus_irq
, serial_hd(2));
1289 /* Load firmware in flash / BIOS. */
1290 dinfo
= drive_get(IF_PFLASH
, 0, fl_idx
);
1291 fl
= pflash_cfi01_register(FLASH_ADDRESS
, "mips_malta.bios",
1293 dinfo
? blk_by_legacy_dinfo(dinfo
) : NULL
,
1295 4, 0x0000, 0x0000, 0x0000, 0x0000, be
);
1296 bios
= pflash_cfi01_get_memory(fl
);
1298 if (kernel_filename
) {
1299 ram_low_size
= MIN(ram_size
, 256 * MiB
);
1300 /* For KVM we reserve 1MB of RAM for running bootloader */
1301 if (kvm_enabled()) {
1302 ram_low_size
-= 0x100000;
1303 bootloader_run_addr
= 0x40000000 + ram_low_size
;
1305 bootloader_run_addr
= 0xbfc00000;
1308 /* Write a small bootloader to the flash location. */
1309 loaderparams
.ram_size
= ram_size
;
1310 loaderparams
.ram_low_size
= ram_low_size
;
1311 loaderparams
.kernel_filename
= kernel_filename
;
1312 loaderparams
.kernel_cmdline
= kernel_cmdline
;
1313 loaderparams
.initrd_filename
= initrd_filename
;
1314 kernel_entry
= load_kernel();
1316 if (!cpu_supports_isa(machine
->cpu_type
, ISA_NANOMIPS32
)) {
1317 write_bootloader(memory_region_get_ram_ptr(bios
),
1318 bootloader_run_addr
, kernel_entry
);
1320 write_bootloader_nanomips(memory_region_get_ram_ptr(bios
),
1321 bootloader_run_addr
, kernel_entry
);
1323 if (kvm_enabled()) {
1324 /* Write the bootloader code @ the end of RAM, 1MB reserved */
1325 write_bootloader(memory_region_get_ram_ptr(ram_low_preio
) +
1327 bootloader_run_addr
, kernel_entry
);
1330 target_long bios_size
= FLASH_SIZE
;
1331 /* The flash region isn't executable from a KVM guest */
1332 if (kvm_enabled()) {
1333 error_report("KVM enabled but no -kernel argument was specified. "
1334 "Booting from flash is not supported with KVM.");
1337 /* Load firmware from flash. */
1339 /* Load a BIOS image. */
1340 if (bios_name
== NULL
) {
1341 bios_name
= BIOS_FILENAME
;
1343 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
1345 bios_size
= load_image_targphys(filename
, FLASH_ADDRESS
,
1351 if ((bios_size
< 0 || bios_size
> BIOS_SIZE
) &&
1352 !kernel_filename
&& !qtest_enabled()) {
1353 error_report("Could not load MIPS bios '%s', and no "
1354 "-kernel argument was specified", bios_name
);
1359 * In little endian mode the 32bit words in the bios are swapped,
1360 * a neat trick which allows bi-endian firmware.
1362 #ifndef TARGET_WORDS_BIGENDIAN
1364 uint32_t *end
, *addr
;
1365 const size_t swapsize
= MIN(bios_size
, 0x3e0000);
1366 addr
= rom_ptr(FLASH_ADDRESS
, swapsize
);
1368 addr
= memory_region_get_ram_ptr(bios
);
1370 end
= (void *)addr
+ swapsize
;
1371 while (addr
< end
) {
1380 * Map the BIOS at a 2nd physical location, as on the real board.
1381 * Copy it so that we can patch in the MIPS revision, which cannot be
1382 * handled by an overlapping region as the resulting ROM code subpage
1383 * regions are not executable.
1385 memory_region_init_ram(bios_copy
, NULL
, "bios.1fc", BIOS_SIZE
,
1387 if (!rom_copy(memory_region_get_ram_ptr(bios_copy
),
1388 FLASH_ADDRESS
, BIOS_SIZE
)) {
1389 memcpy(memory_region_get_ram_ptr(bios_copy
),
1390 memory_region_get_ram_ptr(bios
), BIOS_SIZE
);
1392 memory_region_set_readonly(bios_copy
, true);
1393 memory_region_add_subregion(system_memory
, RESET_ADDRESS
, bios_copy
);
1395 /* Board ID = 0x420 (Malta Board with CoreLV) */
1396 stl_p(memory_region_get_ram_ptr(bios_copy
) + 0x10, 0x00000420);
1399 pci_bus
= gt64120_register(s
->i8259
);
1402 dev
= piix4_create(pci_bus
, &isa_bus
, &smbus
);
1404 /* Interrupt controller */
1405 qdev_connect_gpio_out_named(dev
, "intr", 0, i8259_irq
);
1406 for (int i
= 0; i
< ISA_NUM_IRQS
; i
++) {
1407 s
->i8259
[i
] = qdev_get_gpio_in_named(dev
, "isa", i
);
1410 /* generate SPD EEPROM data */
1411 generate_eeprom_spd(&smbus_eeprom_buf
[0 * 256], ram_size
);
1412 generate_eeprom_serial(&smbus_eeprom_buf
[6 * 256]);
1413 smbus_eeprom_init(smbus
, 8, smbus_eeprom_buf
, smbus_eeprom_size
);
1414 g_free(smbus_eeprom_buf
);
1416 /* Super I/O: SMS FDC37M817 */
1417 isa_create_simple(isa_bus
, TYPE_FDC37M81X_SUPERIO
);
1420 network_init(pci_bus
);
1422 /* Optional PCI video card */
1423 pci_vga_init(pci_bus
);
1426 static const TypeInfo mips_malta_device
= {
1427 .name
= TYPE_MIPS_MALTA
,
1428 .parent
= TYPE_SYS_BUS_DEVICE
,
1429 .instance_size
= sizeof(MaltaState
),
1432 static void mips_malta_machine_init(MachineClass
*mc
)
1434 mc
->desc
= "MIPS Malta Core LV";
1435 mc
->init
= mips_malta_init
;
1436 mc
->block_default_type
= IF_IDE
;
1438 mc
->is_default
= true;
1439 #ifdef TARGET_MIPS64
1440 mc
->default_cpu_type
= MIPS_CPU_TYPE_NAME("20Kc");
1442 mc
->default_cpu_type
= MIPS_CPU_TYPE_NAME("24Kf");
1444 mc
->default_ram_id
= "mips_malta.ram";
1447 DEFINE_MACHINE("malta", mips_malta_machine_init
)
1449 static void mips_malta_register_types(void)
1451 type_register_static(&mips_malta_device
);
1454 type_init(mips_malta_register_types
)