hw/mips/mips_jazz.c

   1 /*
   2  * QEMU MIPS Jazz support
   3  *
   4  * Copyright (c) 2007-2008 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/hw.h"
  27 #include "hw/mips/mips.h"
  28 #include "hw/mips/cpudevs.h"
  29 #include "hw/i386/pc.h"
  30 #include "hw/char/serial.h"
  31 #include "hw/isa/isa.h"
  32 #include "hw/block/fdc.h"
  33 #include "sysemu/sysemu.h"
  34 #include "sysemu/arch_init.h"
  35 #include "hw/boards.h"
  36 #include "net/net.h"
  37 #include "hw/scsi/esp.h"
  38 #include "hw/mips/bios.h"
  39 #include "hw/loader.h"
  40 #include "hw/timer/mc146818rtc.h"
  41 #include "hw/timer/i8254.h"
  42 #include "hw/display/vga.h"
  43 #include "hw/audio/pcspk.h"
  44 #include "hw/sysbus.h"
  45 #include "exec/address-spaces.h"
  46 #include "sysemu/qtest.h"
  47 #include "qapi/error.h"
  48 #include "qemu/error-report.h"
  49 #include "qemu/help_option.h"
  50
  51 enum jazz_model_e
  52 {
  53     JAZZ_MAGNUM,
  54     JAZZ_PICA61,
  55 };
  56
  57 static void main_cpu_reset(void *opaque)
  58 {
  59     MIPSCPU *cpu = opaque;
  60
  61     cpu_reset(CPU(cpu));
  62 }
  63
  64 static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
  65 {
  66     uint8_t val;
  67     address_space_read(&address_space_memory, 0x90000071,
  68                        MEMTXATTRS_UNSPECIFIED, &val, 1);
  69     return val;
  70 }
  71
  72 static void rtc_write(void *opaque, hwaddr addr,
  73                       uint64_t val, unsigned size)
  74 {
  75     uint8_t buf = val & 0xff;
  76     address_space_write(&address_space_memory, 0x90000071,
  77                         MEMTXATTRS_UNSPECIFIED, &buf, 1);
  78 }
  79
  80 static const MemoryRegionOps rtc_ops = {
  81     .read = rtc_read,
  82     .write = rtc_write,
  83     .endianness = DEVICE_NATIVE_ENDIAN,
  84 };
  85
  86 static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
  87                                unsigned size)
  88 {
  89     /* Nothing to do. That is only to ensure that
  90      * the current DMA acknowledge cycle is completed. */
  91     return 0xff;
  92 }
  93
  94 static void dma_dummy_write(void *opaque, hwaddr addr,
  95                             uint64_t val, unsigned size)
  96 {
  97     /* Nothing to do. That is only to ensure that
  98      * the current DMA acknowledge cycle is completed. */
  99 }
 100
 101 static const MemoryRegionOps dma_dummy_ops = {
 102     .read = dma_dummy_read,
 103     .write = dma_dummy_write,
 104     .endianness = DEVICE_NATIVE_ENDIAN,
 105 };
 106
 107 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
 108 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
 109
 110 static CPUUnassignedAccess real_do_unassigned_access;
 111 static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr,
 112                                            bool is_write, bool is_exec,
 113                                            int opaque, unsigned size)
 114 {
 115     if (!is_exec) {
 116         /* ignore invalid access (ie do not raise exception) */
 117         return;
 118     }
 119     (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size);
 120 }
 121
 122 static void mips_jazz_init(MachineState *machine,
 123                            enum jazz_model_e jazz_model)
 124 {
 125     MemoryRegion *address_space = get_system_memory();
 126     char *filename;
 127     int bios_size, n;
 128     MIPSCPU *cpu;
 129     CPUClass *cc;
 130     CPUMIPSState *env;
 131     qemu_irq *i8259;
 132     rc4030_dma *dmas;
 133     IOMMUMemoryRegion *rc4030_dma_mr;
 134     MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
 135     MemoryRegion *isa_io = g_new(MemoryRegion, 1);
 136     MemoryRegion *rtc = g_new(MemoryRegion, 1);
 137     MemoryRegion *i8042 = g_new(MemoryRegion, 1);
 138     MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
 139     NICInfo *nd;
 140     DeviceState *dev, *rc4030;
 141     SysBusDevice *sysbus;
 142     ISABus *isa_bus;
 143     ISADevice *pit;
 144     DriveInfo *fds[MAX_FD];
 145     qemu_irq esp_reset, dma_enable;
 146     MemoryRegion *ram = g_new(MemoryRegion, 1);
 147     MemoryRegion *bios = g_new(MemoryRegion, 1);
 148     MemoryRegion *bios2 = g_new(MemoryRegion, 1);
 149
 150     /* init CPUs */
 151     cpu = MIPS_CPU(cpu_create(machine->cpu_type));
 152     env = &cpu->env;
 153     qemu_register_reset(main_cpu_reset, cpu);
 154
 155     /* Chipset returns 0 in invalid reads and do not raise data exceptions.
 156      * However, we can't simply add a global memory region to catch
 157      * everything, as memory core directly call unassigned_mem_read/write
 158      * on some invalid accesses, which call do_unassigned_access on the
 159      * CPU, which raise an exception.
 160      * Handle that case by hijacking the do_unassigned_access method on
 161      * the CPU, and do not raise exceptions for data access. */
 162     cc = CPU_GET_CLASS(cpu);
 163     real_do_unassigned_access = cc->do_unassigned_access;
 164     cc->do_unassigned_access = mips_jazz_do_unassigned_access;
 165
 166     /* allocate RAM */
 167     memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
 168                                          machine->ram_size);
 169     memory_region_add_subregion(address_space, 0, ram);
 170
 171     memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
 172                            &error_fatal);
 173     memory_region_set_readonly(bios, true);
 174     memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
 175                              0, MAGNUM_BIOS_SIZE);
 176     memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
 177     memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
 178
 179     /* load the BIOS image. */
 180     if (bios_name == NULL)
 181         bios_name = BIOS_FILENAME;
 182     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 183     if (filename) {
 184         bios_size = load_image_targphys(filename, 0xfff00000LL,
 185                                         MAGNUM_BIOS_SIZE);
 186         g_free(filename);
 187     } else {
 188         bios_size = -1;
 189     }
 190     if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
 191         error_report("Could not load MIPS bios '%s'", bios_name);
 192         exit(1);
 193     }
 194
 195     /* Init CPU internal devices */
 196     cpu_mips_irq_init_cpu(cpu);
 197     cpu_mips_clock_init(cpu);
 198
 199     /* Chipset */
 200     rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
 201     sysbus = SYS_BUS_DEVICE(rc4030);
 202     sysbus_connect_irq(sysbus, 0, env->irq[6]);
 203     sysbus_connect_irq(sysbus, 1, env->irq[3]);
 204     memory_region_add_subregion(address_space, 0x80000000,
 205                                 sysbus_mmio_get_region(sysbus, 0));
 206     memory_region_add_subregion(address_space, 0xf0000000,
 207                                 sysbus_mmio_get_region(sysbus, 1));
 208     memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
 209     memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
 210
 211     /* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
 212     memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
 213     memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
 214     memory_region_add_subregion(address_space, 0x90000000, isa_io);
 215     memory_region_add_subregion(address_space, 0x91000000, isa_mem);
 216     isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
 217
 218     /* ISA devices */
 219     i8259 = i8259_init(isa_bus, env->irq[4]);
 220     isa_bus_irqs(isa_bus, i8259);
 221     DMA_init(isa_bus, 0);
 222     pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
 223     pcspk_init(isa_bus, pit);
 224
 225     /* Video card */
 226     switch (jazz_model) {
 227     case JAZZ_MAGNUM:
 228         dev = qdev_create(NULL, "sysbus-g364");
 229         qdev_init_nofail(dev);
 230         sysbus = SYS_BUS_DEVICE(dev);
 231         sysbus_mmio_map(sysbus, 0, 0x60080000);
 232         sysbus_mmio_map(sysbus, 1, 0x40000000);
 233         sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
 234         {
 235             /* Simple ROM, so user doesn't have to provide one */
 236             MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
 237             memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
 238                                    &error_fatal);
 239             memory_region_set_readonly(rom_mr, true);
 240             uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
 241             memory_region_add_subregion(address_space, 0x60000000, rom_mr);
 242             rom[0] = 0x10; /* Mips G364 */
 243         }
 244         break;
 245     case JAZZ_PICA61:
 246         isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
 247         break;
 248     default:
 249         break;
 250     }
 251
 252     /* Network controller */
 253     for (n = 0; n < nb_nics; n++) {
 254         nd = &nd_table[n];
 255         if (!nd->model)
 256             nd->model = g_strdup("dp83932");
 257         if (strcmp(nd->model, "dp83932") == 0) {
 258             qemu_check_nic_model(nd, "dp83932");
 259
 260             dev = qdev_create(NULL, "dp8393x");
 261             qdev_set_nic_properties(dev, nd);
 262             qdev_prop_set_uint8(dev, "it_shift", 2);
 263             qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
 264             qdev_init_nofail(dev);
 265             sysbus = SYS_BUS_DEVICE(dev);
 266             sysbus_mmio_map(sysbus, 0, 0x80001000);
 267             sysbus_mmio_map(sysbus, 1, 0x8000b000);
 268             sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
 269             break;
 270         } else if (is_help_option(nd->model)) {
 271             error_report("Supported NICs: dp83932");
 272             exit(1);
 273         } else {
 274             error_report("Unsupported NIC: %s", nd->model);
 275             exit(1);
 276         }
 277     }
 278
 279     /* SCSI adapter */
 280     esp_init(0x80002000, 0,
 281              rc4030_dma_read, rc4030_dma_write, dmas[0],
 282              qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
 283
 284     /* Floppy */
 285     for (n = 0; n < MAX_FD; n++) {
 286         fds[n] = drive_get(IF_FLOPPY, 0, n);
 287     }
 288     /* FIXME: we should enable DMA with a custom IsaDma device */
 289     fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
 290
 291     /* Real time clock */
 292     mc146818_rtc_init(isa_bus, 1980, NULL);
 293     memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
 294     memory_region_add_subregion(address_space, 0x80004000, rtc);
 295
 296     /* Keyboard (i8042) */
 297     i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
 298                   i8042, 0x1000, 0x1);
 299     memory_region_add_subregion(address_space, 0x80005000, i8042);
 300
 301     /* Serial ports */
 302     if (serial_hds[0]) {
 303         serial_mm_init(address_space, 0x80006000, 0,
 304                        qdev_get_gpio_in(rc4030, 8), 8000000/16,
 305                        serial_hds[0], DEVICE_NATIVE_ENDIAN);
 306     }
 307     if (serial_hds[1]) {
 308         serial_mm_init(address_space, 0x80007000, 0,
 309                        qdev_get_gpio_in(rc4030, 9), 8000000/16,
 310                        serial_hds[1], DEVICE_NATIVE_ENDIAN);
 311     }
 312
 313     /* Parallel port */
 314     if (parallel_hds[0])
 315         parallel_mm_init(address_space, 0x80008000, 0,
 316                          qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
 317
 318     /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
 319
 320     /* NVRAM */
 321     dev = qdev_create(NULL, "ds1225y");
 322     qdev_init_nofail(dev);
 323     sysbus = SYS_BUS_DEVICE(dev);
 324     sysbus_mmio_map(sysbus, 0, 0x80009000);
 325
 326     /* LED indicator */
 327     sysbus_create_simple("jazz-led", 0x8000f000, NULL);
 328 }
 329
 330 static
 331 void mips_magnum_init(MachineState *machine)
 332 {
 333     mips_jazz_init(machine, JAZZ_MAGNUM);
 334 }
 335
 336 static
 337 void mips_pica61_init(MachineState *machine)
 338 {
 339     mips_jazz_init(machine, JAZZ_PICA61);
 340 }
 341
 342 static void mips_magnum_class_init(ObjectClass *oc, void *data)
 343 {
 344     MachineClass *mc = MACHINE_CLASS(oc);
 345
 346     mc->desc = "MIPS Magnum";
 347     mc->init = mips_magnum_init;
 348     mc->block_default_type = IF_SCSI;
 349     mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
 350 }
 351
 352 static const TypeInfo mips_magnum_type = {
 353     .name = MACHINE_TYPE_NAME("magnum"),
 354     .parent = TYPE_MACHINE,
 355     .class_init = mips_magnum_class_init,
 356 };
 357
 358 static void mips_pica61_class_init(ObjectClass *oc, void *data)
 359 {
 360     MachineClass *mc = MACHINE_CLASS(oc);
 361
 362     mc->desc = "Acer Pica 61";
 363     mc->init = mips_pica61_init;
 364     mc->block_default_type = IF_SCSI;
 365     mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000");
 366 }
 367
 368 static const TypeInfo mips_pica61_type = {
 369     .name = MACHINE_TYPE_NAME("pica61"),
 370     .parent = TYPE_MACHINE,
 371     .class_init = mips_pica61_class_init,
 372 };
 373
 374 static void mips_jazz_machine_init(void)
 375 {
 376     type_register_static(&mips_magnum_type);
 377     type_register_static(&mips_pica61_type);
 378 }
 379
 380 type_init(mips_jazz_machine_init)