2 * QEMU Malta board support
4 * Copyright (c) 2006 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/i386/pc.h"
27 #include "hw/char/serial.h"
28 #include "hw/block/fdc.h"
30 #include "hw/boards.h"
31 #include "hw/i2c/smbus.h"
32 #include "block/block.h"
33 #include "hw/block/flash.h"
34 #include "hw/mips/mips.h"
35 #include "hw/mips/cpudevs.h"
36 #include "hw/pci/pci.h"
37 #include "sysemu/char.h"
38 #include "sysemu/sysemu.h"
39 #include "sysemu/arch_init.h"
41 #include "hw/mips/bios.h"
43 #include "hw/loader.h"
45 #include "hw/timer/mc146818rtc.h"
46 #include "hw/timer/i8254.h"
47 #include "sysemu/blockdev.h"
48 #include "exec/address-spaces.h"
49 #include "hw/sysbus.h" /* SysBusDevice */
51 //#define DEBUG_BOARD_INIT
53 #define ENVP_ADDR 0x80002000l
54 #define ENVP_NB_ENTRIES 16
55 #define ENVP_ENTRY_SIZE 256
57 /* Hardware addresses */
58 #define FLASH_ADDRESS 0x1e000000ULL
59 #define FPGA_ADDRESS 0x1f000000ULL
60 #define RESET_ADDRESS 0x1fc00000ULL
62 #define FLASH_SIZE 0x400000
68 MemoryRegion iomem_lo
; /* 0 - 0x900 */
69 MemoryRegion iomem_hi
; /* 0xa00 - 0x100000 */
77 CharDriverState
*display
;
82 #define TYPE_MIPS_MALTA "mips-malta"
83 #define MIPS_MALTA(obj) OBJECT_CHECK(MaltaState, (obj), TYPE_MIPS_MALTA)
86 SysBusDevice parent_obj
;
91 static ISADevice
*pit
;
93 static struct _loaderparams
{
95 const char *kernel_filename
;
96 const char *kernel_cmdline
;
97 const char *initrd_filename
;
101 static void malta_fpga_update_display(void *opaque
)
105 MaltaFPGAState
*s
= opaque
;
107 for (i
= 7 ; i
>= 0 ; i
--) {
108 if (s
->leds
& (1 << i
))
115 qemu_chr_fe_printf(s
->display
, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text
);
116 qemu_chr_fe_printf(s
->display
, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s
->display_text
);
120 * EEPROM 24C01 / 24C02 emulation.
122 * Emulation for serial EEPROMs:
123 * 24C01 - 1024 bit (128 x 8)
124 * 24C02 - 2048 bit (256 x 8)
126 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
132 # define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
134 # define logout(fmt, ...) ((void)0)
137 struct _eeprom24c0x_t
{
146 uint8_t contents
[256];
149 typedef struct _eeprom24c0x_t eeprom24c0x_t
;
151 static eeprom24c0x_t eeprom
= {
153 /* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
154 /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
155 /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00,
156 /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
157 /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
158 /* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
159 /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
160 /* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
161 /* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
162 /* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
163 /* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
164 /* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
165 /* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
166 /* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
167 /* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
168 /* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
172 static uint8_t eeprom24c0x_read(void)
174 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
175 eeprom
.tick
, eeprom
.scl
, eeprom
.sda
, eeprom
.data
);
179 static void eeprom24c0x_write(int scl
, int sda
)
181 if (eeprom
.scl
&& scl
&& (eeprom
.sda
!= sda
)) {
182 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
183 eeprom
.tick
, eeprom
.scl
, scl
, eeprom
.sda
, sda
, sda
? "stop" : "start");
188 } else if (eeprom
.tick
== 0 && !eeprom
.ack
) {
189 /* Waiting for start. */
190 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
191 eeprom
.tick
, eeprom
.scl
, scl
, eeprom
.sda
, sda
);
192 } else if (!eeprom
.scl
&& scl
) {
193 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
194 eeprom
.tick
, eeprom
.scl
, scl
, eeprom
.sda
, sda
);
196 logout("\ti2c ack bit = 0\n");
199 } else if (eeprom
.sda
== sda
) {
200 uint8_t bit
= (sda
!= 0);
201 logout("\ti2c bit = %d\n", bit
);
202 if (eeprom
.tick
< 9) {
203 eeprom
.command
<<= 1;
204 eeprom
.command
+= bit
;
206 if (eeprom
.tick
== 9) {
207 logout("\tcommand 0x%04x, %s\n", eeprom
.command
, bit
? "read" : "write");
210 } else if (eeprom
.tick
< 17) {
211 if (eeprom
.command
& 1) {
212 sda
= ((eeprom
.data
& 0x80) != 0);
214 eeprom
.address
<<= 1;
215 eeprom
.address
+= bit
;
218 if (eeprom
.tick
== 17) {
219 eeprom
.data
= eeprom
.contents
[eeprom
.address
];
220 logout("\taddress 0x%04x, data 0x%02x\n", eeprom
.address
, eeprom
.data
);
224 } else if (eeprom
.tick
>= 17) {
228 logout("\tsda changed with raising scl\n");
231 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom
.tick
, eeprom
.scl
, scl
, eeprom
.sda
, sda
);
237 static uint64_t malta_fpga_read(void *opaque
, hwaddr addr
,
240 MaltaFPGAState
*s
= opaque
;
244 saddr
= (addr
& 0xfffff);
248 /* SWITCH Register */
250 val
= 0x00000000; /* All switches closed */
253 /* STATUS Register */
255 #ifdef TARGET_WORDS_BIGENDIAN
267 /* LEDBAR Register */
272 /* BRKRES Register */
277 /* UART Registers are handled directly by the serial device */
284 /* XXX: implement a real I2C controller */
288 /* IN = OUT until a real I2C control is implemented */
295 /* I2CINP Register */
297 val
= ((s
->i2cin
& ~1) | eeprom24c0x_read());
305 /* I2COUT Register */
310 /* I2CSEL Register */
317 printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx
"\n",
325 static void malta_fpga_write(void *opaque
, hwaddr addr
,
326 uint64_t val
, unsigned size
)
328 MaltaFPGAState
*s
= opaque
;
331 saddr
= (addr
& 0xfffff);
335 /* SWITCH Register */
343 /* LEDBAR Register */
345 s
->leds
= val
& 0xff;
346 malta_fpga_update_display(s
);
349 /* ASCIIWORD Register */
351 snprintf(s
->display_text
, 9, "%08X", (uint32_t)val
);
352 malta_fpga_update_display(s
);
355 /* ASCIIPOS0 to ASCIIPOS7 Registers */
364 s
->display_text
[(saddr
- 0x00418) >> 3] = (char) val
;
365 malta_fpga_update_display(s
);
368 /* SOFTRES Register */
371 qemu_system_reset_request ();
374 /* BRKRES Register */
379 /* UART Registers are handled directly by the serial device */
383 s
->gpout
= val
& 0xff;
388 s
->i2coe
= val
& 0x03;
391 /* I2COUT Register */
393 eeprom24c0x_write(val
& 0x02, val
& 0x01);
397 /* I2CSEL Register */
399 s
->i2csel
= val
& 0x01;
404 printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx
"\n",
411 static const MemoryRegionOps malta_fpga_ops
= {
412 .read
= malta_fpga_read
,
413 .write
= malta_fpga_write
,
414 .endianness
= DEVICE_NATIVE_ENDIAN
,
417 static void malta_fpga_reset(void *opaque
)
419 MaltaFPGAState
*s
= opaque
;
429 s
->display_text
[8] = '\0';
430 snprintf(s
->display_text
, 9, " ");
433 static void malta_fpga_led_init(CharDriverState
*chr
)
435 qemu_chr_fe_printf(chr
, "\e[HMalta LEDBAR\r\n");
436 qemu_chr_fe_printf(chr
, "+--------+\r\n");
437 qemu_chr_fe_printf(chr
, "+ +\r\n");
438 qemu_chr_fe_printf(chr
, "+--------+\r\n");
439 qemu_chr_fe_printf(chr
, "\n");
440 qemu_chr_fe_printf(chr
, "Malta ASCII\r\n");
441 qemu_chr_fe_printf(chr
, "+--------+\r\n");
442 qemu_chr_fe_printf(chr
, "+ +\r\n");
443 qemu_chr_fe_printf(chr
, "+--------+\r\n");
446 static MaltaFPGAState
*malta_fpga_init(MemoryRegion
*address_space
,
447 hwaddr base
, qemu_irq uart_irq
, CharDriverState
*uart_chr
)
451 s
= (MaltaFPGAState
*)g_malloc0(sizeof(MaltaFPGAState
));
453 memory_region_init_io(&s
->iomem
, NULL
, &malta_fpga_ops
, s
,
454 "malta-fpga", 0x100000);
455 memory_region_init_alias(&s
->iomem_lo
, NULL
, "malta-fpga",
456 &s
->iomem
, 0, 0x900);
457 memory_region_init_alias(&s
->iomem_hi
, NULL
, "malta-fpga",
458 &s
->iomem
, 0xa00, 0x10000-0xa00);
460 memory_region_add_subregion(address_space
, base
, &s
->iomem_lo
);
461 memory_region_add_subregion(address_space
, base
+ 0xa00, &s
->iomem_hi
);
463 s
->display
= qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init
);
465 s
->uart
= serial_mm_init(address_space
, base
+ 0x900, 3, uart_irq
,
466 230400, uart_chr
, DEVICE_NATIVE_ENDIAN
);
469 qemu_register_reset(malta_fpga_reset
, s
);
474 /* Network support */
475 static void network_init(PCIBus
*pci_bus
)
479 for(i
= 0; i
< nb_nics
; i
++) {
480 NICInfo
*nd
= &nd_table
[i
];
481 const char *default_devaddr
= NULL
;
483 if (i
== 0 && (!nd
->model
|| strcmp(nd
->model
, "pcnet") == 0))
484 /* The malta board has a PCNet card using PCI SLOT 11 */
485 default_devaddr
= "0b";
487 pci_nic_init_nofail(nd
, pci_bus
, "pcnet", default_devaddr
);
491 /* ROM and pseudo bootloader
493 The following code implements a very very simple bootloader. It first
494 loads the registers a0 to a3 to the values expected by the OS, and
495 then jump at the kernel address.
497 The bootloader should pass the locations of the kernel arguments and
498 environment variables tables. Those tables contain the 32-bit address
499 of NULL terminated strings. The environment variables table should be
500 terminated by a NULL address.
502 For a simpler implementation, the number of kernel arguments is fixed
503 to two (the name of the kernel and the command line), and the two
504 tables are actually the same one.
506 The registers a0 to a3 should contain the following values:
507 a0 - number of kernel arguments
508 a1 - 32-bit address of the kernel arguments table
509 a2 - 32-bit address of the environment variables table
510 a3 - RAM size in bytes
513 static void write_bootloader (CPUMIPSState
*env
, uint8_t *base
,
514 int64_t kernel_entry
)
518 /* Small bootloader */
519 p
= (uint32_t *)base
;
520 stl_raw(p
++, 0x0bf00160); /* j 0x1fc00580 */
521 stl_raw(p
++, 0x00000000); /* nop */
523 /* YAMON service vector */
524 stl_raw(base
+ 0x500, 0xbfc00580); /* start: */
525 stl_raw(base
+ 0x504, 0xbfc0083c); /* print_count: */
526 stl_raw(base
+ 0x520, 0xbfc00580); /* start: */
527 stl_raw(base
+ 0x52c, 0xbfc00800); /* flush_cache: */
528 stl_raw(base
+ 0x534, 0xbfc00808); /* print: */
529 stl_raw(base
+ 0x538, 0xbfc00800); /* reg_cpu_isr: */
530 stl_raw(base
+ 0x53c, 0xbfc00800); /* unred_cpu_isr: */
531 stl_raw(base
+ 0x540, 0xbfc00800); /* reg_ic_isr: */
532 stl_raw(base
+ 0x544, 0xbfc00800); /* unred_ic_isr: */
533 stl_raw(base
+ 0x548, 0xbfc00800); /* reg_esr: */
534 stl_raw(base
+ 0x54c, 0xbfc00800); /* unreg_esr: */
535 stl_raw(base
+ 0x550, 0xbfc00800); /* getchar: */
536 stl_raw(base
+ 0x554, 0xbfc00800); /* syscon_read: */
539 /* Second part of the bootloader */
540 p
= (uint32_t *) (base
+ 0x580);
541 stl_raw(p
++, 0x24040002); /* addiu a0, zero, 2 */
542 stl_raw(p
++, 0x3c1d0000 | (((ENVP_ADDR
- 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
543 stl_raw(p
++, 0x37bd0000 | ((ENVP_ADDR
- 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
544 stl_raw(p
++, 0x3c050000 | ((ENVP_ADDR
>> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
545 stl_raw(p
++, 0x34a50000 | (ENVP_ADDR
& 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
546 stl_raw(p
++, 0x3c060000 | (((ENVP_ADDR
+ 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
547 stl_raw(p
++, 0x34c60000 | ((ENVP_ADDR
+ 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
548 stl_raw(p
++, 0x3c070000 | (loaderparams
.ram_size
>> 16)); /* lui a3, high(ram_size) */
549 stl_raw(p
++, 0x34e70000 | (loaderparams
.ram_size
& 0xffff)); /* ori a3, a3, low(ram_size) */
551 /* Load BAR registers as done by YAMON */
552 stl_raw(p
++, 0x3c09b400); /* lui t1, 0xb400 */
554 #ifdef TARGET_WORDS_BIGENDIAN
555 stl_raw(p
++, 0x3c08df00); /* lui t0, 0xdf00 */
557 stl_raw(p
++, 0x340800df); /* ori t0, r0, 0x00df */
559 stl_raw(p
++, 0xad280068); /* sw t0, 0x0068(t1) */
561 stl_raw(p
++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
563 #ifdef TARGET_WORDS_BIGENDIAN
564 stl_raw(p
++, 0x3c08c000); /* lui t0, 0xc000 */
566 stl_raw(p
++, 0x340800c0); /* ori t0, r0, 0x00c0 */
568 stl_raw(p
++, 0xad280048); /* sw t0, 0x0048(t1) */
569 #ifdef TARGET_WORDS_BIGENDIAN
570 stl_raw(p
++, 0x3c084000); /* lui t0, 0x4000 */
572 stl_raw(p
++, 0x34080040); /* ori t0, r0, 0x0040 */
574 stl_raw(p
++, 0xad280050); /* sw t0, 0x0050(t1) */
576 #ifdef TARGET_WORDS_BIGENDIAN
577 stl_raw(p
++, 0x3c088000); /* lui t0, 0x8000 */
579 stl_raw(p
++, 0x34080080); /* ori t0, r0, 0x0080 */
581 stl_raw(p
++, 0xad280058); /* sw t0, 0x0058(t1) */
582 #ifdef TARGET_WORDS_BIGENDIAN
583 stl_raw(p
++, 0x3c083f00); /* lui t0, 0x3f00 */
585 stl_raw(p
++, 0x3408003f); /* ori t0, r0, 0x003f */
587 stl_raw(p
++, 0xad280060); /* sw t0, 0x0060(t1) */
589 #ifdef TARGET_WORDS_BIGENDIAN
590 stl_raw(p
++, 0x3c08c100); /* lui t0, 0xc100 */
592 stl_raw(p
++, 0x340800c1); /* ori t0, r0, 0x00c1 */
594 stl_raw(p
++, 0xad280080); /* sw t0, 0x0080(t1) */
595 #ifdef TARGET_WORDS_BIGENDIAN
596 stl_raw(p
++, 0x3c085e00); /* lui t0, 0x5e00 */
598 stl_raw(p
++, 0x3408005e); /* ori t0, r0, 0x005e */
600 stl_raw(p
++, 0xad280088); /* sw t0, 0x0088(t1) */
602 /* Jump to kernel code */
603 stl_raw(p
++, 0x3c1f0000 | ((kernel_entry
>> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
604 stl_raw(p
++, 0x37ff0000 | (kernel_entry
& 0xffff)); /* ori ra, ra, low(kernel_entry) */
605 stl_raw(p
++, 0x03e00008); /* jr ra */
606 stl_raw(p
++, 0x00000000); /* nop */
608 /* YAMON subroutines */
609 p
= (uint32_t *) (base
+ 0x800);
610 stl_raw(p
++, 0x03e00008); /* jr ra */
611 stl_raw(p
++, 0x24020000); /* li v0,0 */
612 /* 808 YAMON print */
613 stl_raw(p
++, 0x03e06821); /* move t5,ra */
614 stl_raw(p
++, 0x00805821); /* move t3,a0 */
615 stl_raw(p
++, 0x00a05021); /* move t2,a1 */
616 stl_raw(p
++, 0x91440000); /* lbu a0,0(t2) */
617 stl_raw(p
++, 0x254a0001); /* addiu t2,t2,1 */
618 stl_raw(p
++, 0x10800005); /* beqz a0,834 */
619 stl_raw(p
++, 0x00000000); /* nop */
620 stl_raw(p
++, 0x0ff0021c); /* jal 870 */
621 stl_raw(p
++, 0x00000000); /* nop */
622 stl_raw(p
++, 0x08000205); /* j 814 */
623 stl_raw(p
++, 0x00000000); /* nop */
624 stl_raw(p
++, 0x01a00008); /* jr t5 */
625 stl_raw(p
++, 0x01602021); /* move a0,t3 */
626 /* 0x83c YAMON print_count */
627 stl_raw(p
++, 0x03e06821); /* move t5,ra */
628 stl_raw(p
++, 0x00805821); /* move t3,a0 */
629 stl_raw(p
++, 0x00a05021); /* move t2,a1 */
630 stl_raw(p
++, 0x00c06021); /* move t4,a2 */
631 stl_raw(p
++, 0x91440000); /* lbu a0,0(t2) */
632 stl_raw(p
++, 0x0ff0021c); /* jal 870 */
633 stl_raw(p
++, 0x00000000); /* nop */
634 stl_raw(p
++, 0x254a0001); /* addiu t2,t2,1 */
635 stl_raw(p
++, 0x258cffff); /* addiu t4,t4,-1 */
636 stl_raw(p
++, 0x1580fffa); /* bnez t4,84c */
637 stl_raw(p
++, 0x00000000); /* nop */
638 stl_raw(p
++, 0x01a00008); /* jr t5 */
639 stl_raw(p
++, 0x01602021); /* move a0,t3 */
641 stl_raw(p
++, 0x3c08b800); /* lui t0,0xb400 */
642 stl_raw(p
++, 0x350803f8); /* ori t0,t0,0x3f8 */
643 stl_raw(p
++, 0x91090005); /* lbu t1,5(t0) */
644 stl_raw(p
++, 0x00000000); /* nop */
645 stl_raw(p
++, 0x31290040); /* andi t1,t1,0x40 */
646 stl_raw(p
++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
647 stl_raw(p
++, 0x00000000); /* nop */
648 stl_raw(p
++, 0x03e00008); /* jr ra */
649 stl_raw(p
++, 0xa1040000); /* sb a0,0(t0) */
653 static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf
, int index
,
654 const char *string
, ...)
659 if (index
>= ENVP_NB_ENTRIES
)
662 if (string
== NULL
) {
667 table_addr
= sizeof(int32_t) * ENVP_NB_ENTRIES
+ index
* ENVP_ENTRY_SIZE
;
668 prom_buf
[index
] = tswap32(ENVP_ADDR
+ table_addr
);
670 va_start(ap
, string
);
671 vsnprintf((char *)prom_buf
+ table_addr
, ENVP_ENTRY_SIZE
, string
, ap
);
676 static int64_t load_kernel (void)
678 int64_t kernel_entry
, kernel_high
;
680 ram_addr_t initrd_offset
;
686 #ifdef TARGET_WORDS_BIGENDIAN
692 if (load_elf(loaderparams
.kernel_filename
, cpu_mips_kseg0_to_phys
, NULL
,
693 (uint64_t *)&kernel_entry
, NULL
, (uint64_t *)&kernel_high
,
694 big_endian
, ELF_MACHINE
, 1) < 0) {
695 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
696 loaderparams
.kernel_filename
);
703 if (loaderparams
.initrd_filename
) {
704 initrd_size
= get_image_size (loaderparams
.initrd_filename
);
705 if (initrd_size
> 0) {
706 initrd_offset
= (kernel_high
+ ~TARGET_PAGE_MASK
) & TARGET_PAGE_MASK
;
707 if (initrd_offset
+ initrd_size
> ram_size
) {
709 "qemu: memory too small for initial ram disk '%s'\n",
710 loaderparams
.initrd_filename
);
713 initrd_size
= load_image_targphys(loaderparams
.initrd_filename
,
715 ram_size
- initrd_offset
);
717 if (initrd_size
== (target_ulong
) -1) {
718 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
719 loaderparams
.initrd_filename
);
724 /* Setup prom parameters. */
725 prom_size
= ENVP_NB_ENTRIES
* (sizeof(int32_t) + ENVP_ENTRY_SIZE
);
726 prom_buf
= g_malloc(prom_size
);
728 prom_set(prom_buf
, prom_index
++, "%s", loaderparams
.kernel_filename
);
729 if (initrd_size
> 0) {
730 prom_set(prom_buf
, prom_index
++, "rd_start=0x%" PRIx64
" rd_size=%li %s",
731 cpu_mips_phys_to_kseg0(NULL
, initrd_offset
), initrd_size
,
732 loaderparams
.kernel_cmdline
);
734 prom_set(prom_buf
, prom_index
++, "%s", loaderparams
.kernel_cmdline
);
737 prom_set(prom_buf
, prom_index
++, "memsize");
738 prom_set(prom_buf
, prom_index
++, "%i", loaderparams
.ram_size
);
739 prom_set(prom_buf
, prom_index
++, "modetty0");
740 prom_set(prom_buf
, prom_index
++, "38400n8r");
741 prom_set(prom_buf
, prom_index
++, NULL
);
743 rom_add_blob_fixed("prom", prom_buf
, prom_size
,
744 cpu_mips_kseg0_to_phys(NULL
, ENVP_ADDR
));
749 static void malta_mips_config(MIPSCPU
*cpu
)
751 CPUMIPSState
*env
= &cpu
->env
;
752 CPUState
*cs
= CPU(cpu
);
754 env
->mvp
->CP0_MVPConf0
|= ((smp_cpus
- 1) << CP0MVPC0_PVPE
) |
755 ((smp_cpus
* cs
->nr_threads
- 1) << CP0MVPC0_PTC
);
758 static void main_cpu_reset(void *opaque
)
760 MIPSCPU
*cpu
= opaque
;
761 CPUMIPSState
*env
= &cpu
->env
;
765 /* The bootloader does not need to be rewritten as it is located in a
766 read only location. The kernel location and the arguments table
767 location does not change. */
768 if (loaderparams
.kernel_filename
) {
769 env
->CP0_Status
&= ~((1 << CP0St_BEV
) | (1 << CP0St_ERL
));
772 malta_mips_config(cpu
);
775 static void cpu_request_exit(void *opaque
, int irq
, int level
)
777 CPUState
*cpu
= current_cpu
;
785 void mips_malta_init(QEMUMachineInitArgs
*args
)
787 ram_addr_t ram_size
= args
->ram_size
;
788 const char *cpu_model
= args
->cpu_model
;
789 const char *kernel_filename
= args
->kernel_filename
;
790 const char *kernel_cmdline
= args
->kernel_cmdline
;
791 const char *initrd_filename
= args
->initrd_filename
;
794 MemoryRegion
*system_memory
= get_system_memory();
795 MemoryRegion
*ram
= g_new(MemoryRegion
, 1);
796 MemoryRegion
*bios
, *bios_copy
= g_new(MemoryRegion
, 1);
797 target_long bios_size
= FLASH_SIZE
;
798 int64_t kernel_entry
;
804 qemu_irq
*cpu_exit_irq
;
809 DriveInfo
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
810 DriveInfo
*fd
[MAX_FD
];
812 int fl_sectors
= bios_size
>> 16;
815 DeviceState
*dev
= qdev_create(NULL
, TYPE_MIPS_MALTA
);
816 MaltaState
*s
= MIPS_MALTA(dev
);
818 qdev_init_nofail(dev
);
820 /* Make sure the first 3 serial ports are associated with a device. */
821 for(i
= 0; i
< 3; i
++) {
822 if (!serial_hds
[i
]) {
824 snprintf(label
, sizeof(label
), "serial%d", i
);
825 serial_hds
[i
] = qemu_chr_new(label
, "null", NULL
);
830 if (cpu_model
== NULL
) {
838 for (i
= 0; i
< smp_cpus
; i
++) {
839 cpu
= cpu_mips_init(cpu_model
);
841 fprintf(stderr
, "Unable to find CPU definition\n");
846 /* Init internal devices */
847 cpu_mips_irq_init_cpu(env
);
848 cpu_mips_clock_init(env
);
849 qemu_register_reset(main_cpu_reset
, cpu
);
851 cpu
= MIPS_CPU(first_cpu
);
855 if (ram_size
> (256 << 20)) {
857 "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n",
858 ((unsigned int)ram_size
/ (1 << 20)));
861 memory_region_init_ram(ram
, NULL
, "mips_malta.ram", ram_size
);
862 vmstate_register_ram_global(ram
);
863 memory_region_add_subregion(system_memory
, 0, ram
);
865 #ifdef TARGET_WORDS_BIGENDIAN
871 /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
872 malta_fpga_init(system_memory
, FPGA_ADDRESS
, env
->irq
[4], serial_hds
[2]);
874 /* Load firmware in flash / BIOS. */
875 dinfo
= drive_get(IF_PFLASH
, 0, fl_idx
);
876 #ifdef DEBUG_BOARD_INIT
878 printf("Register parallel flash %d size " TARGET_FMT_lx
" at "
879 "addr %08llx '%s' %x\n",
880 fl_idx
, bios_size
, FLASH_ADDRESS
,
881 bdrv_get_device_name(dinfo
->bdrv
), fl_sectors
);
884 fl
= pflash_cfi01_register(FLASH_ADDRESS
, NULL
, "mips_malta.bios",
885 BIOS_SIZE
, dinfo
? dinfo
->bdrv
: NULL
,
887 4, 0x0000, 0x0000, 0x0000, 0x0000, be
);
888 bios
= pflash_cfi01_get_memory(fl
);
890 if (kernel_filename
) {
891 /* Write a small bootloader to the flash location. */
892 loaderparams
.ram_size
= ram_size
;
893 loaderparams
.kernel_filename
= kernel_filename
;
894 loaderparams
.kernel_cmdline
= kernel_cmdline
;
895 loaderparams
.initrd_filename
= initrd_filename
;
896 kernel_entry
= load_kernel();
897 write_bootloader(env
, memory_region_get_ram_ptr(bios
), kernel_entry
);
899 /* Load firmware from flash. */
901 /* Load a BIOS image. */
902 if (bios_name
== NULL
) {
903 bios_name
= BIOS_FILENAME
;
905 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
907 bios_size
= load_image_targphys(filename
, FLASH_ADDRESS
,
913 if ((bios_size
< 0 || bios_size
> BIOS_SIZE
) && !kernel_filename
) {
915 "qemu: Warning, could not load MIPS bios '%s', and no -kernel argument was specified\n",
919 /* In little endian mode the 32bit words in the bios are swapped,
920 a neat trick which allows bi-endian firmware. */
921 #ifndef TARGET_WORDS_BIGENDIAN
923 uint32_t *end
, *addr
= rom_ptr(FLASH_ADDRESS
);
925 addr
= memory_region_get_ram_ptr(bios
);
927 end
= (void *)addr
+ bios_size
;
937 * Map the BIOS at a 2nd physical location, as on the real board.
938 * Copy it so that we can patch in the MIPS revision, which cannot be
939 * handled by an overlapping region as the resulting ROM code subpage
940 * regions are not executable.
942 memory_region_init_ram(bios_copy
, NULL
, "bios.1fc", BIOS_SIZE
);
943 if (!rom_copy(memory_region_get_ram_ptr(bios_copy
),
944 FLASH_ADDRESS
, bios_size
)) {
945 memcpy(memory_region_get_ram_ptr(bios_copy
),
946 memory_region_get_ram_ptr(bios
), bios_size
);
948 memory_region_set_readonly(bios_copy
, true);
949 memory_region_add_subregion(system_memory
, RESET_ADDRESS
, bios_copy
);
951 /* Board ID = 0x420 (Malta Board with CoreLV) */
952 stl_p(memory_region_get_ram_ptr(bios_copy
) + 0x10, 0x00000420);
954 /* Init internal devices */
955 cpu_mips_irq_init_cpu(env
);
956 cpu_mips_clock_init(env
);
959 * We have a circular dependency problem: pci_bus depends on isa_irq,
960 * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
961 * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
962 * qemu_irq_proxy() adds an extra bit of indirection, allowing us
963 * to resolve the isa_irq -> i8259 dependency after i8259 is initialized.
965 isa_irq
= qemu_irq_proxy(&s
->i8259
, 16);
968 pci_bus
= gt64120_register(isa_irq
);
971 ide_drive_get(hd
, MAX_IDE_BUS
);
973 piix4_devfn
= piix4_init(pci_bus
, &isa_bus
, 80);
975 /* Interrupt controller */
976 /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
977 s
->i8259
= i8259_init(isa_bus
, env
->irq
[2]);
979 isa_bus_irqs(isa_bus
, s
->i8259
);
980 pci_piix4_ide_init(pci_bus
, hd
, piix4_devfn
+ 1);
981 pci_create_simple(pci_bus
, piix4_devfn
+ 2, "piix4-usb-uhci");
982 smbus
= piix4_pm_init(pci_bus
, piix4_devfn
+ 3, 0x1100,
983 isa_get_irq(NULL
, 9), NULL
, 0, NULL
);
984 /* TODO: Populate SPD eeprom data. */
985 smbus_eeprom_init(smbus
, 8, NULL
, 0);
986 pit
= pit_init(isa_bus
, 0x40, 0, NULL
);
987 cpu_exit_irq
= qemu_allocate_irqs(cpu_request_exit
, NULL
, 1);
988 DMA_init(0, cpu_exit_irq
);
991 isa_create_simple(isa_bus
, "i8042");
993 rtc_init(isa_bus
, 2000, NULL
);
994 serial_isa_init(isa_bus
, 0, serial_hds
[0]);
995 serial_isa_init(isa_bus
, 1, serial_hds
[1]);
997 parallel_init(isa_bus
, 0, parallel_hds
[0]);
998 for(i
= 0; i
< MAX_FD
; i
++) {
999 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
1001 fdctrl_init_isa(isa_bus
, fd
);
1004 network_init(pci_bus
);
1006 /* Optional PCI video card */
1007 pci_vga_init(pci_bus
);
1010 static int mips_malta_sysbus_device_init(SysBusDevice
*sysbusdev
)
1015 static void mips_malta_class_init(ObjectClass
*klass
, void *data
)
1017 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1019 k
->init
= mips_malta_sysbus_device_init
;
1022 static const TypeInfo mips_malta_device
= {
1023 .name
= TYPE_MIPS_MALTA
,
1024 .parent
= TYPE_SYS_BUS_DEVICE
,
1025 .instance_size
= sizeof(MaltaState
),
1026 .class_init
= mips_malta_class_init
,
1029 static QEMUMachine mips_malta_machine
= {
1031 .desc
= "MIPS Malta Core LV",
1032 .init
= mips_malta_init
,
1035 DEFAULT_MACHINE_OPTIONS
,
1038 static void mips_malta_register_types(void)
1040 type_register_static(&mips_malta_device
);
1043 static void mips_malta_machine_init(void)
1045 qemu_register_machine(&mips_malta_machine
);
1048 type_init(mips_malta_register_types
)
1049 machine_init(mips_malta_machine_init
);