hw/mips_r4k.c

   1 /*
   2  * QEMU/MIPS pseudo-board
   3  *
   4  * emulates a simple machine with ISA-like bus.
   5  * ISA IO space mapped to the 0x14000000 (PHYS) and
   6  * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
   7  * All peripherial devices are attached to this "bus" with
   8  * the standard PC ISA addresses.
   9 */
  10 #include "hw.h"
  11 #include "mips.h"
  12 #include "pc.h"
  13 #include "isa.h"
  14 #include "net.h"
  15 #include "sysemu.h"
  16 #include "boards.h"
  17
  18 #ifdef TARGET_WORDS_BIGENDIAN
  19 #define BIOS_FILENAME "mips_bios.bin"
  20 #else
  21 #define BIOS_FILENAME "mipsel_bios.bin"
  22 #endif
  23
  24 #define PHYS_TO_VIRT(x) ((x) | ~(target_ulong)0x7fffffff)
  25
  26 #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
  27
  28 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  29 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  30 static const int ide_irq[2] = { 14, 15 };
  31
  32 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
  33 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
  34
  35 extern FILE *logfile;
  36
  37 static PITState *pit; /* PIT i8254 */
  38
  39 /*i8254 PIT is attached to the IRQ0 at PIC i8259 */
  40
  41 static struct _loaderparams {
  42     int ram_size;
  43     const char *kernel_filename;
  44     const char *kernel_cmdline;
  45     const char *initrd_filename;
  46 } loaderparams;
  47
  48 static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
  49                               uint32_t val)
  50 {
  51     if ((addr & 0xffff) == 0 && val == 42)
  52         qemu_system_reset_request ();
  53     else if ((addr & 0xffff) == 4 && val == 42)
  54         qemu_system_shutdown_request ();
  55 }
  56
  57 static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
  58 {
  59     return 0;
  60 }
  61
  62 static CPUWriteMemoryFunc *mips_qemu_write[] = {
  63     &mips_qemu_writel,
  64     &mips_qemu_writel,
  65     &mips_qemu_writel,
  66 };
  67
  68 static CPUReadMemoryFunc *mips_qemu_read[] = {
  69     &mips_qemu_readl,
  70     &mips_qemu_readl,
  71     &mips_qemu_readl,
  72 };
  73
  74 static int mips_qemu_iomemtype = 0;
  75
  76 static void load_kernel (CPUState *env)
  77 {
  78     int64_t entry, kernel_low, kernel_high;
  79     long kernel_size, initrd_size;
  80     ram_addr_t initrd_offset;
  81
  82     kernel_size = load_elf(loaderparams.kernel_filename, VIRT_TO_PHYS_ADDEND,
  83                            &entry, &kernel_low, &kernel_high);
  84     if (kernel_size >= 0) {
  85         if ((entry & ~0x7fffffffULL) == 0x80000000)
  86             entry = (int32_t)entry;
  87         env->PC[env->current_tc] = entry;
  88     } else {
  89         fprintf(stderr, "qemu: could not load kernel '%s'\n",
  90                 loaderparams.kernel_filename);
  91         exit(1);
  92     }
  93
  94     /* load initrd */
  95     initrd_size = 0;
  96     initrd_offset = 0;
  97     if (loaderparams.initrd_filename) {
  98         initrd_size = get_image_size (loaderparams.initrd_filename);
  99         if (initrd_size > 0) {
 100             initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
 101             if (initrd_offset + initrd_size > ram_size) {
 102                 fprintf(stderr,
 103                         "qemu: memory too small for initial ram disk '%s'\n",
 104                         loaderparams.initrd_filename);
 105                 exit(1);
 106             }
 107             initrd_size = load_image(loaderparams.initrd_filename,
 108                                      phys_ram_base + initrd_offset);
 109         }
 110         if (initrd_size == (target_ulong) -1) {
 111             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 112                     loaderparams.initrd_filename);
 113             exit(1);
 114         }
 115     }
 116
 117     /* Store command line.  */
 118     if (initrd_size > 0) {
 119         int ret;
 120         ret = sprintf(phys_ram_base + (16 << 20) - 256,
 121                       "rd_start=0x" TARGET_FMT_lx " rd_size=%li ",
 122                       PHYS_TO_VIRT((uint32_t)initrd_offset),
 123                       initrd_size);
 124         strcpy (phys_ram_base + (16 << 20) - 256 + ret,
 125                 loaderparams.kernel_cmdline);
 126     }
 127     else {
 128         strcpy (phys_ram_base + (16 << 20) - 256,
 129                 loaderparams.kernel_cmdline);
 130     }
 131
 132     *(int32_t *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
 133     *(int32_t *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
 134 }
 135
 136 static void main_cpu_reset(void *opaque)
 137 {
 138     CPUState *env = opaque;
 139     cpu_reset(env);
 140
 141     if (loaderparams.kernel_filename)
 142         load_kernel (env);
 143 }
 144
 145 static
 146 void mips_r4k_init (int ram_size, int vga_ram_size, const char *boot_device,
 147                     DisplayState *ds, const char **fd_filename, int snapshot,
 148                     const char *kernel_filename, const char *kernel_cmdline,
 149                     const char *initrd_filename, const char *cpu_model)
 150 {
 151     char buf[1024];
 152     unsigned long bios_offset;
 153     int bios_size;
 154     CPUState *env;
 155     RTCState *rtc_state;
 156     int i;
 157     qemu_irq *i8259;
 158
 159     /* init CPUs */
 160     if (cpu_model == NULL) {
 161 #ifdef TARGET_MIPS64
 162         cpu_model = "R4000";
 163 #else
 164         cpu_model = "24Kf";
 165 #endif
 166     }
 167     env = cpu_init(cpu_model);
 168     if (!env) {
 169         fprintf(stderr, "Unable to find CPU definition\n");
 170         exit(1);
 171     }
 172     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 173     qemu_register_reset(main_cpu_reset, env);
 174
 175     /* allocate RAM */
 176     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 177
 178     if (!mips_qemu_iomemtype) {
 179         mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
 180                                                      mips_qemu_write, NULL);
 181     }
 182     cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
 183
 184     /* Try to load a BIOS image. If this fails, we continue regardless,
 185        but initialize the hardware ourselves. When a kernel gets
 186        preloaded we also initialize the hardware, since the BIOS wasn't
 187        run. */
 188     bios_offset = ram_size + vga_ram_size;
 189     if (bios_name == NULL)
 190         bios_name = BIOS_FILENAME;
 191     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 192     bios_size = load_image(buf, phys_ram_base + bios_offset);
 193     if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
 194         cpu_register_physical_memory(0x1fc00000,
 195                                      BIOS_SIZE, bios_offset | IO_MEM_ROM);
 196     } else {
 197         /* not fatal */
 198         fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
 199                 buf);
 200     }
 201
 202     if (kernel_filename) {
 203         loaderparams.ram_size = ram_size;
 204         loaderparams.kernel_filename = kernel_filename;
 205         loaderparams.kernel_cmdline = kernel_cmdline;
 206         loaderparams.initrd_filename = initrd_filename;
 207         load_kernel (env);
 208     }
 209
 210     /* Init CPU internal devices */
 211     cpu_mips_irq_init_cpu(env);
 212     cpu_mips_clock_init(env);
 213     cpu_mips_irqctrl_init();
 214
 215     /* The PIC is attached to the MIPS CPU INT0 pin */
 216     i8259 = i8259_init(env->irq[2]);
 217
 218     rtc_state = rtc_init(0x70, i8259[8]);
 219
 220     /* Register 64 KB of ISA IO space at 0x14000000 */
 221     isa_mmio_init(0x14000000, 0x00010000);
 222     isa_mem_base = 0x10000000;
 223
 224     pit = pit_init(0x40, i8259[0]);
 225
 226     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 227         if (serial_hds[i]) {
 228             serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]);
 229         }
 230     }
 231
 232     isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
 233                  vga_ram_size);
 234
 235     if (nd_table[0].vlan) {
 236         if (nd_table[0].model == NULL
 237             || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
 238             isa_ne2000_init(0x300, i8259[9], &nd_table[0]);
 239         } else if (strcmp(nd_table[0].model, "?") == 0) {
 240             fprintf(stderr, "qemu: Supported NICs: ne2k_isa\n");
 241             exit (1);
 242         } else {
 243             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 244             exit (1);
 245         }
 246     }
 247
 248     for(i = 0; i < 2; i++)
 249         isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
 250                      bs_table[2 * i], bs_table[2 * i + 1]);
 251
 252     i8042_init(i8259[1], i8259[12], 0x60);
 253     ds1225y_init(0x9000, "nvram");
 254 }
 255
 256 QEMUMachine mips_machine = {
 257     "mips",
 258     "mips r4k platform",
 259     mips_r4k_init,
 260 };