hw/mips_r4k.c

   1 #include "vl.h"
   2
   3 #define BIOS_FILENAME "mips_bios.bin"
   4 //#define BIOS_FILENAME "system.bin"
   5 #define KERNEL_LOAD_ADDR 0x80010000
   6 #define INITRD_LOAD_ADDR 0x80800000
   7
   8 #define VIRT_TO_PHYS_ADDEND (-0x80000000LL)
   9
  10 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  11 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  12 static const int ide_irq[2] = { 14, 15 };
  13
  14 extern FILE *logfile;
  15
  16 static PITState *pit;
  17
  18 static void pic_irq_request(void *opaque, int level)
  19 {
  20     CPUState *env = first_cpu;
  21     if (level) {
  22         env->CP0_Cause |= 0x00000400;
  23         cpu_interrupt(env, CPU_INTERRUPT_HARD);
  24     } else {
  25         env->CP0_Cause &= ~0x00000400;
  26         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  27     }
  28 }
  29
  30 void cpu_mips_irqctrl_init (void)
  31 {
  32 }
  33
  34 /* XXX: do not use a global */
  35 uint32_t cpu_mips_get_random (CPUState *env)
  36 {
  37     static uint32_t seed = 0;
  38     uint32_t idx;
  39     seed = seed * 314159 + 1;
  40     idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
  41     return idx;
  42 }
  43
  44 /* MIPS R4K timer */
  45 uint32_t cpu_mips_get_count (CPUState *env)
  46 {
  47     return env->CP0_Count +
  48         (uint32_t)muldiv64(qemu_get_clock(vm_clock),
  49                            100 * 1000 * 1000, ticks_per_sec);
  50 }
  51
  52 static void cpu_mips_update_count (CPUState *env, uint32_t count,
  53                                    uint32_t compare)
  54 {
  55     uint64_t now, next;
  56     uint32_t tmp;
  57
  58     tmp = count;
  59     if (count == compare)
  60         tmp++;
  61     now = qemu_get_clock(vm_clock);
  62     next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
  63     if (next == now)
  64         next++;
  65 #if 0
  66     if (logfile) {
  67         fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
  68                 __func__, now, count, compare, next - now);
  69     }
  70 #endif
  71     /* Store new count and compare registers */
  72     env->CP0_Compare = compare;
  73     env->CP0_Count =
  74         count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
  75     /* Adjust timer */
  76     qemu_mod_timer(env->timer, next);
  77 }
  78
  79 void cpu_mips_store_count (CPUState *env, uint32_t value)
  80 {
  81     cpu_mips_update_count(env, value, env->CP0_Compare);
  82 }
  83
  84 void cpu_mips_store_compare (CPUState *env, uint32_t value)
  85 {
  86     cpu_mips_update_count(env, cpu_mips_get_count(env), value);
  87     env->CP0_Cause &= ~0x00008000;
  88     cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  89 }
  90
  91 static void mips_timer_cb (void *opaque)
  92 {
  93     CPUState *env;
  94
  95     env = opaque;
  96 #if 0
  97     if (logfile) {
  98         fprintf(logfile, "%s\n", __func__);
  99     }
 100 #endif
 101     cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
 102     env->CP0_Cause |= 0x00008000;
 103     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 104 }
 105
 106 void cpu_mips_clock_init (CPUState *env)
 107 {
 108     env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
 109     env->CP0_Compare = 0;
 110     cpu_mips_update_count(env, 1, 0);
 111 }
 112
 113
 114 void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
 115                     DisplayState *ds, const char **fd_filename, int snapshot,
 116                     const char *kernel_filename, const char *kernel_cmdline,
 117                     const char *initrd_filename)
 118 {
 119     char buf[1024];
 120     int64_t entry = 0;
 121     unsigned long bios_offset;
 122     int ret;
 123     CPUState *env;
 124     long kernel_size;
 125     int i;
 126
 127     env = cpu_init();
 128     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 129
 130     /* allocate RAM */
 131     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 132
 133     /* Try to load a BIOS image. If this fails, we continue regardless,
 134        but initialize the hardware ourselves. When a kernel gets
 135        preloaded we also initialize the hardware, since the BIOS wasn't
 136        run. */
 137     bios_offset = ram_size + vga_ram_size;
 138     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
 139     ret = load_image(buf, phys_ram_base + bios_offset);
 140     if (ret == BIOS_SIZE) {
 141         cpu_register_physical_memory((uint32_t)(0x1fc00000),
 142                                      BIOS_SIZE, bios_offset | IO_MEM_ROM);
 143     } else {
 144         /* not fatal */
 145         fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
 146                 buf);
 147     }
 148
 149     kernel_size = 0;
 150     if (kernel_filename) {
 151         kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry);
 152         if (kernel_size >= 0)
 153             env->PC = entry;
 154         else {
 155             kernel_size = load_image(kernel_filename,
 156                                      phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
 157             if (kernel_size < 0) {
 158                 fprintf(stderr, "qemu: could not load kernel '%s'\n",
 159                         kernel_filename);
 160                 exit(1);
 161             }
 162             env->PC = KERNEL_LOAD_ADDR;
 163         }
 164
 165         /* load initrd */
 166         if (initrd_filename) {
 167             if (load_image(initrd_filename,
 168                            phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND)
 169                 == (target_ulong) -1) {
 170                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 171                         initrd_filename);
 172                 exit(1);
 173             }
 174         }
 175
 176         /* Store command line.  */
 177         strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
 178         /* FIXME: little endian support */
 179         *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
 180         *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
 181     }
 182
 183     /* Init internal devices */
 184     cpu_mips_clock_init(env);
 185     cpu_mips_irqctrl_init();
 186
 187     /* Register 64 KB of ISA IO space at 0x14000000 */
 188     isa_mmio_init(0x14000000, 0x00010000);
 189     isa_mem_base = 0x10000000;
 190
 191     isa_pic = pic_init(pic_irq_request, env);
 192     pit = pit_init(0x40, 0);
 193     serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
 194     isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
 195                  vga_ram_size);
 196
 197     if (nd_table[0].vlan) {
 198         if (nd_table[0].model == NULL
 199             || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
 200             isa_ne2000_init(0x300, 9, &nd_table[0]);
 201         } else {
 202             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 203             exit (1);
 204         }
 205     }
 206
 207     for(i = 0; i < 2; i++)
 208         isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
 209                      bs_table[2 * i], bs_table[2 * i + 1]);
 210 }
 211
 212 QEMUMachine mips_machine = {
 213     "mips",
 214     "mips r4k platform",
 215     mips_r4k_init,
 216 };