hw/mips_r4k.c

   1 /*
   2  * QEMU/MIPS pseudo-board
   3  *
   4  * emulates a simple machine with ISA-like bus.
   5  * ISA IO space mapped to the 0x14000000 (PHYS) and
   6  * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
   7  * All peripherial devices are attached to this "bus" with
   8  * the standard PC ISA addresses.
   9 */
  10 #include "vl.h"
  11
  12 #ifdef TARGET_WORDS_BIGENDIAN
  13 #define BIOS_FILENAME "mips_bios.bin"
  14 #else
  15 #define BIOS_FILENAME "mipsel_bios.bin"
  16 #endif
  17 //#define BIOS_FILENAME "system.bin"
  18 #ifdef MIPS_HAS_MIPS64
  19 #define INITRD_LOAD_ADDR (int64_t)(int32_t)0x80800000
  20 #else
  21 #define INITRD_LOAD_ADDR (int32_t)0x80800000
  22 #endif
  23
  24 #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
  25
  26 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  27 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  28 static const int ide_irq[2] = { 14, 15 };
  29
  30 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
  31 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
  32
  33 extern FILE *logfile;
  34
  35 static PITState *pit; /* PIT i8254 */
  36
  37 /*i8254 PIT is attached to the IRQ0 at PIC i8259 */
  38 /*The PIC is attached to the MIPS CPU INT0 pin */
  39 static void pic_irq_request(void *opaque, int level)
  40 {
  41     CPUState *env = first_cpu;
  42     if (level) {
  43         env->CP0_Cause |= 0x00000400;
  44         cpu_interrupt(env, CPU_INTERRUPT_HARD);
  45     } else {
  46         env->CP0_Cause &= ~0x00000400;
  47         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  48     }
  49 }
  50
  51 static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
  52                               uint32_t val)
  53 {
  54     if ((addr & 0xffff) == 0 && val == 42)
  55         qemu_system_reset_request ();
  56     else if ((addr & 0xffff) == 4 && val == 42)
  57         qemu_system_shutdown_request ();
  58 }
  59
  60 static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
  61 {
  62     return 0;
  63 }
  64
  65 static CPUWriteMemoryFunc *mips_qemu_write[] = {
  66     &mips_qemu_writel,
  67     &mips_qemu_writel,
  68     &mips_qemu_writel,
  69 };
  70
  71 static CPUReadMemoryFunc *mips_qemu_read[] = {
  72     &mips_qemu_readl,
  73     &mips_qemu_readl,
  74     &mips_qemu_readl,
  75 };
  76
  77 static int mips_qemu_iomemtype = 0;
  78
  79 void load_kernel (CPUState *env, int ram_size, const char *kernel_filename,
  80                   const char *kernel_cmdline,
  81                   const char *initrd_filename)
  82 {
  83     int64_t entry = 0;
  84     long kernel_size, initrd_size;
  85
  86     kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry);
  87     if (kernel_size >= 0) {
  88         if ((entry & ~0x7fffffffULL) == 0x80000000)
  89             entry = (int32_t)entry;
  90         env->PC = entry;
  91     } else {
  92         fprintf(stderr, "qemu: could not load kernel '%s'\n",
  93                 kernel_filename);
  94         exit(1);
  95     }
  96
  97     /* load initrd */
  98     initrd_size = 0;
  99     if (initrd_filename) {
 100         initrd_size = load_image(initrd_filename,
 101                                  phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
 102         if (initrd_size == (target_ulong) -1) {
 103             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 104                     initrd_filename);
 105             exit(1);
 106         }
 107     }
 108
 109     /* Store command line.  */
 110     if (initrd_size > 0) {
 111         int ret;
 112         ret = sprintf(phys_ram_base + (16 << 20) - 256,
 113                       "rd_start=0x" TLSZ " rd_size=%li ",
 114                       INITRD_LOAD_ADDR,
 115                       initrd_size);
 116         strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline);
 117     }
 118     else {
 119         strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
 120     }
 121
 122     *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
 123     *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
 124 }
 125
 126 static void main_cpu_reset(void *opaque)
 127 {
 128     CPUState *env = opaque;
 129     cpu_reset(env);
 130
 131     if (env->kernel_filename)
 132         load_kernel (env, env->ram_size, env->kernel_filename,
 133                      env->kernel_cmdline, env->initrd_filename);
 134 }
 135
 136 void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
 137                     DisplayState *ds, const char **fd_filename, int snapshot,
 138                     const char *kernel_filename, const char *kernel_cmdline,
 139                     const char *initrd_filename)
 140 {
 141     char buf[1024];
 142     unsigned long bios_offset;
 143     int bios_size;
 144     CPUState *env;
 145     static RTCState *rtc_state;
 146     int i;
 147
 148     env = cpu_init();
 149     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 150     qemu_register_reset(main_cpu_reset, env);
 151
 152     /* allocate RAM */
 153     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 154
 155     if (!mips_qemu_iomemtype) {
 156         mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
 157                                                      mips_qemu_write, NULL);
 158     }
 159     cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
 160
 161     /* Try to load a BIOS image. If this fails, we continue regardless,
 162        but initialize the hardware ourselves. When a kernel gets
 163        preloaded we also initialize the hardware, since the BIOS wasn't
 164        run. */
 165     bios_offset = ram_size + vga_ram_size;
 166     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
 167     bios_size = load_image(buf, phys_ram_base + bios_offset);
 168     if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
 169         cpu_register_physical_memory((uint32_t)(0x1fc00000),
 170                                      BIOS_SIZE, bios_offset | IO_MEM_ROM);
 171     } else {
 172         /* not fatal */
 173         fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
 174                 buf);
 175     }
 176
 177     if (kernel_filename) {
 178         load_kernel (env, ram_size, kernel_filename, kernel_cmdline,
 179                      initrd_filename);
 180         env->ram_size = ram_size;
 181         env->kernel_filename = kernel_filename;
 182         env->kernel_cmdline = kernel_cmdline;
 183         env->initrd_filename = initrd_filename;
 184     }
 185
 186     /* Init CPU internal devices */
 187     cpu_mips_clock_init(env);
 188     cpu_mips_irqctrl_init();
 189
 190     rtc_state = rtc_init(0x70, 8);
 191
 192     /* Register 64 KB of ISA IO space at 0x14000000 */
 193     isa_mmio_init(0x14000000, 0x00010000);
 194     isa_mem_base = 0x10000000;
 195
 196     isa_pic = pic_init(pic_irq_request, env);
 197     pit = pit_init(0x40, 0);
 198
 199     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 200         if (serial_hds[i]) {
 201             serial_init(&pic_set_irq_new, isa_pic,
 202                         serial_io[i], serial_irq[i], serial_hds[i]);
 203         }
 204     }
 205
 206     isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
 207                  vga_ram_size);
 208
 209     if (nd_table[0].vlan) {
 210         if (nd_table[0].model == NULL
 211             || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
 212             isa_ne2000_init(0x300, 9, &nd_table[0]);
 213         } else {
 214             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 215             exit (1);
 216         }
 217     }
 218
 219     for(i = 0; i < 2; i++)
 220         isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
 221                      bs_table[2 * i], bs_table[2 * i + 1]);
 222 }
 223
 224 QEMUMachine mips_machine = {
 225     "mips",
 226     "mips r4k platform",
 227     mips_r4k_init,
 228 };