hw/mips_r4k.c

   1 #include "vl.h"
   2
   3 #define BIOS_FILENAME "mips_bios.bin"
   4 //#define BIOS_FILENAME "system.bin"
   5 #define KERNEL_LOAD_ADDR 0x80010000
   6 #define INITRD_LOAD_ADDR 0x80800000
   7
   8 #define VIRT_TO_PHYS_ADDEND (-0x80000000LL)
   9
  10 extern FILE *logfile;
  11
  12 static PITState *pit;
  13
  14 static void pic_irq_request(void *opaque, int level)
  15 {
  16     CPUState *env = first_cpu;
  17     if (level) {
  18         env->CP0_Cause |= 0x00000400;
  19         cpu_interrupt(env, CPU_INTERRUPT_HARD);
  20     } else {
  21         env->CP0_Cause &= ~0x00000400;
  22         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  23     }
  24 }
  25
  26 void cpu_mips_irqctrl_init (void)
  27 {
  28 }
  29
  30 /* XXX: do not use a global */
  31 uint32_t cpu_mips_get_random (CPUState *env)
  32 {
  33     static uint32_t seed = 0;
  34     uint32_t idx;
  35     seed = seed * 314159 + 1;
  36     idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
  37     return idx;
  38 }
  39
  40 /* MIPS R4K timer */
  41 uint32_t cpu_mips_get_count (CPUState *env)
  42 {
  43     return env->CP0_Count +
  44         (uint32_t)muldiv64(qemu_get_clock(vm_clock),
  45                            100 * 1000 * 1000, ticks_per_sec);
  46 }
  47
  48 static void cpu_mips_update_count (CPUState *env, uint32_t count,
  49                                    uint32_t compare)
  50 {
  51     uint64_t now, next;
  52     uint32_t tmp;
  53
  54     tmp = count;
  55     if (count == compare)
  56         tmp++;
  57     now = qemu_get_clock(vm_clock);
  58     next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000);
  59     if (next == now)
  60         next++;
  61 #if 0
  62     if (logfile) {
  63         fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
  64                 __func__, now, count, compare, next - now);
  65     }
  66 #endif
  67     /* Store new count and compare registers */
  68     env->CP0_Compare = compare;
  69     env->CP0_Count =
  70         count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec);
  71     /* Adjust timer */
  72     qemu_mod_timer(env->timer, next);
  73 }
  74
  75 void cpu_mips_store_count (CPUState *env, uint32_t value)
  76 {
  77     cpu_mips_update_count(env, value, env->CP0_Compare);
  78 }
  79
  80 void cpu_mips_store_compare (CPUState *env, uint32_t value)
  81 {
  82     cpu_mips_update_count(env, cpu_mips_get_count(env), value);
  83     env->CP0_Cause &= ~0x00008000;
  84     cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  85 }
  86
  87 static void mips_timer_cb (void *opaque)
  88 {
  89     CPUState *env;
  90
  91     env = opaque;
  92 #if 0
  93     if (logfile) {
  94         fprintf(logfile, "%s\n", __func__);
  95     }
  96 #endif
  97     cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare);
  98     env->CP0_Cause |= 0x00008000;
  99     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 100 }
 101
 102 void cpu_mips_clock_init (CPUState *env)
 103 {
 104     env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env);
 105     env->CP0_Compare = 0;
 106     cpu_mips_update_count(env, 1, 0);
 107 }
 108
 109
 110 void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
 111                     DisplayState *ds, const char **fd_filename, int snapshot,
 112                     const char *kernel_filename, const char *kernel_cmdline,
 113                     const char *initrd_filename)
 114 {
 115     char buf[1024];
 116     int64_t entry = 0;
 117     unsigned long bios_offset;
 118     int ret;
 119     CPUState *env;
 120     long kernel_size;
 121
 122     env = cpu_init();
 123     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 124
 125     /* allocate RAM */
 126     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 127
 128     /* Try to load a BIOS image. If this fails, we continue regardless,
 129        but initialize the hardware ourselves. When a kernel gets
 130        preloaded we also initialize the hardware, since the BIOS wasn't
 131        run. */
 132     bios_offset = ram_size + vga_ram_size;
 133     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
 134     ret = load_image(buf, phys_ram_base + bios_offset);
 135     if (ret == BIOS_SIZE) {
 136         cpu_register_physical_memory((uint32_t)(0x1fc00000),
 137                                      BIOS_SIZE, bios_offset | IO_MEM_ROM);
 138     } else {
 139         /* not fatal */
 140         fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
 141                 buf);
 142     }
 143
 144     kernel_size = 0;
 145     if (kernel_filename) {
 146         kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry);
 147         if (kernel_size >= 0)
 148             env->PC = entry;
 149         else {
 150             kernel_size = load_image(kernel_filename,
 151                                      phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
 152             if (kernel_size < 0) {
 153                 fprintf(stderr, "qemu: could not load kernel '%s'\n",
 154                         kernel_filename);
 155                 exit(1);
 156             }
 157             env->PC = KERNEL_LOAD_ADDR;
 158         }
 159
 160         /* load initrd */
 161         if (initrd_filename) {
 162             if (load_image(initrd_filename,
 163                            phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND)
 164                 == (target_ulong) -1) {
 165                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 166                         initrd_filename);
 167                 exit(1);
 168             }
 169         }
 170
 171         /* Store command line.  */
 172         strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
 173         /* FIXME: little endian support */
 174         *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
 175         *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
 176     }
 177
 178     /* Init internal devices */
 179     cpu_mips_clock_init(env);
 180     cpu_mips_irqctrl_init();
 181
 182     /* Register 64 KB of ISA IO space at 0x14000000 */
 183     isa_mmio_init(0x14000000, 0x00010000);
 184     isa_mem_base = 0x10000000;
 185
 186     isa_pic = pic_init(pic_irq_request, env);
 187     pit = pit_init(0x40, 0);
 188     serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
 189     isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
 190                  vga_ram_size);
 191
 192     if (nd_table[0].vlan) {
 193         if (nd_table[0].model == NULL
 194             || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
 195             isa_ne2000_init(0x300, 9, &nd_table[0]);
 196         } else {
 197             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 198             exit (1);
 199         }
 200     }
 201 }
 202
 203 QEMUMachine mips_machine = {
 204     "mips",
 205     "mips r4k platform",
 206     mips_r4k_init,
 207 };