hw/mips_r4k.c

   1 /*
   2  * QEMU/MIPS pseudo-board
   3  *
   4  * emulates a simple machine with ISA-like bus.
   5  * ISA IO space mapped to the 0x14000000 (PHYS) and
   6  * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
   7  * All peripherial devices are attached to this "bus" with
   8  * the standard PC ISA addresses.
   9 */
  10 #include "vl.h"
  11
  12 #define BIOS_FILENAME "mips_bios.bin"
  13 //#define BIOS_FILENAME "system.bin"
  14 #define KERNEL_LOAD_ADDR SIGN_EXTEND32(0x80010000)
  15 #define INITRD_LOAD_ADDR SIGN_EXTEND32(0x80800000)
  16
  17 #define VIRT_TO_PHYS_ADDEND (-SIGN_EXTEND32(0x80000000LL))
  18
  19 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  20 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  21 static const int ide_irq[2] = { 14, 15 };
  22
  23 extern FILE *logfile;
  24
  25 static PITState *pit; /* PIT i8254 */
  26
  27 /*i8254 PIT is attached to the IRQ0 at PIC i8259 */
  28 /*The PIC is attached to the MIPS CPU INT0 pin */
  29 static void pic_irq_request(void *opaque, int level)
  30 {
  31     CPUState *env = first_cpu;
  32     if (level) {
  33         env->CP0_Cause |= 0x00000400;
  34         cpu_interrupt(env, CPU_INTERRUPT_HARD);
  35     } else {
  36         env->CP0_Cause &= ~0x00000400;
  37         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  38     }
  39 }
  40
  41 static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
  42                               uint32_t val)
  43 {
  44     if ((addr & 0xffff) == 0 && val == 42)
  45         qemu_system_reset_request ();
  46     else if ((addr & 0xffff) == 4 && val == 42)
  47         qemu_system_shutdown_request ();
  48 }
  49
  50 static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
  51 {
  52     return 0;
  53 }
  54
  55 static CPUWriteMemoryFunc *mips_qemu_write[] = {
  56     &mips_qemu_writel,
  57     &mips_qemu_writel,
  58     &mips_qemu_writel,
  59 };
  60
  61 static CPUReadMemoryFunc *mips_qemu_read[] = {
  62     &mips_qemu_readl,
  63     &mips_qemu_readl,
  64     &mips_qemu_readl,
  65 };
  66
  67 static int mips_qemu_iomemtype = 0;
  68
  69 void load_kernel (CPUState *env, int ram_size, const char *kernel_filename,
  70                   const char *kernel_cmdline,
  71                   const char *initrd_filename)
  72 {
  73     int64_t entry = 0;
  74     long kernel_size, initrd_size;
  75
  76     kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry);
  77     if (kernel_size >= 0) {
  78         if ((entry & ~0x7fffffffULL) == 0x80000000)
  79             entry = SIGN_EXTEND32(entry);
  80         env->PC = entry;
  81     } else {
  82         kernel_size = load_image(kernel_filename,
  83                                  phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
  84         if (kernel_size < 0) {
  85             fprintf(stderr, "qemu: could not load kernel '%s'\n",
  86                     kernel_filename);
  87             exit(1);
  88         }
  89         env->PC = KERNEL_LOAD_ADDR;
  90     }
  91
  92     /* load initrd */
  93     initrd_size = 0;
  94     if (initrd_filename) {
  95         initrd_size = load_image(initrd_filename,
  96                                  phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
  97         if (initrd_size == (target_ulong) -1) {
  98             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
  99                     initrd_filename);
 100             exit(1);
 101         }
 102     }
 103
 104     /* Store command line.  */
 105     if (initrd_size > 0) {
 106         int ret;
 107         ret = sprintf(phys_ram_base + (16 << 20) - 256,
 108                       "rd_start=0x" TLSZ " rd_size=%li ",
 109                       INITRD_LOAD_ADDR,
 110                       initrd_size);
 111         strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline);
 112     }
 113     else {
 114         strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
 115     }
 116
 117     *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
 118     *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
 119 }
 120
 121 static void main_cpu_reset(void *opaque)
 122 {
 123     CPUState *env = opaque;
 124     cpu_reset(env);
 125
 126     if (env->kernel_filename)
 127         load_kernel (env, env->ram_size, env->kernel_filename,
 128                      env->kernel_cmdline, env->initrd_filename);
 129 }
 130
 131 void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
 132                     DisplayState *ds, const char **fd_filename, int snapshot,
 133                     const char *kernel_filename, const char *kernel_cmdline,
 134                     const char *initrd_filename)
 135 {
 136     char buf[1024];
 137     unsigned long bios_offset;
 138     int ret;
 139     CPUState *env;
 140     static RTCState *rtc_state;
 141     int i;
 142
 143     env = cpu_init();
 144     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 145     qemu_register_reset(main_cpu_reset, env);
 146
 147     /* allocate RAM */
 148     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 149
 150     if (!mips_qemu_iomemtype) {
 151         mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
 152                                                      mips_qemu_write, NULL);
 153     }
 154     cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
 155
 156     /* Try to load a BIOS image. If this fails, we continue regardless,
 157        but initialize the hardware ourselves. When a kernel gets
 158        preloaded we also initialize the hardware, since the BIOS wasn't
 159        run. */
 160     bios_offset = ram_size + vga_ram_size;
 161     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
 162     ret = load_image(buf, phys_ram_base + bios_offset);
 163     if (ret == BIOS_SIZE) {
 164         cpu_register_physical_memory((uint32_t)(0x1fc00000),
 165                                      BIOS_SIZE, bios_offset | IO_MEM_ROM);
 166     } else {
 167         /* not fatal */
 168         fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
 169                 buf);
 170     }
 171
 172     if (kernel_filename) {
 173         load_kernel (env, ram_size, kernel_filename, kernel_cmdline,
 174                      initrd_filename);
 175         env->ram_size = ram_size;
 176         env->kernel_filename = kernel_filename;
 177         env->kernel_cmdline = kernel_cmdline;
 178         env->initrd_filename = initrd_filename;
 179     }
 180
 181     /* Init CPU internal devices */
 182     cpu_mips_clock_init(env);
 183     cpu_mips_irqctrl_init();
 184
 185     rtc_state = rtc_init(0x70, 8);
 186
 187     /* Register 64 KB of ISA IO space at 0x14000000 */
 188     isa_mmio_init(0x14000000, 0x00010000);
 189     isa_mem_base = 0x10000000;
 190
 191     isa_pic = pic_init(pic_irq_request, env);
 192     pit = pit_init(0x40, 0);
 193
 194     serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]);
 195     isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
 196                  vga_ram_size);
 197
 198     if (nd_table[0].vlan) {
 199         if (nd_table[0].model == NULL
 200             || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
 201             isa_ne2000_init(0x300, 9, &nd_table[0]);
 202         } else {
 203             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 204             exit (1);
 205         }
 206     }
 207
 208     for(i = 0; i < 2; i++)
 209         isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
 210                      bs_table[2 * i], bs_table[2 * i + 1]);
 211 }
 212
 213 QEMUMachine mips_machine = {
 214     "mips",
 215     "mips r4k platform",
 216     mips_r4k_init,
 217 };