hw/mips_r4k.c

   1 /*
   2  * QEMU/MIPS pseudo-board
   3  *
   4  * emulates a simple machine with ISA-like bus.
   5  * ISA IO space mapped to the 0x14000000 (PHYS) and
   6  * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
   7  * All peripherial devices are attached to this "bus" with
   8  * the standard PC ISA addresses.
   9 */
  10 #include "vl.h"
  11
  12 #define BIOS_FILENAME "mips_bios.bin"
  13 //#define BIOS_FILENAME "system.bin"
  14 #define KERNEL_LOAD_ADDR (int32_t)0x80010000
  15 #ifdef MIPS_HAS_MIPS64
  16 #define INITRD_LOAD_ADDR (int64_t)0x80800000
  17 #else
  18 #define INITRD_LOAD_ADDR (int32_t)0x80800000
  19 #endif
  20
  21 #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000))
  22
  23 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  24 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  25 static const int ide_irq[2] = { 14, 15 };
  26
  27 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
  28 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
  29
  30 extern FILE *logfile;
  31
  32 static PITState *pit; /* PIT i8254 */
  33
  34 /*i8254 PIT is attached to the IRQ0 at PIC i8259 */
  35 /*The PIC is attached to the MIPS CPU INT0 pin */
  36 static void pic_irq_request(void *opaque, int level)
  37 {
  38     CPUState *env = first_cpu;
  39     if (level) {
  40         env->CP0_Cause |= 0x00000400;
  41         cpu_interrupt(env, CPU_INTERRUPT_HARD);
  42     } else {
  43         env->CP0_Cause &= ~0x00000400;
  44         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
  45     }
  46 }
  47
  48 static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
  49                               uint32_t val)
  50 {
  51     if ((addr & 0xffff) == 0 && val == 42)
  52         qemu_system_reset_request ();
  53     else if ((addr & 0xffff) == 4 && val == 42)
  54         qemu_system_shutdown_request ();
  55 }
  56
  57 static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
  58 {
  59     return 0;
  60 }
  61
  62 static CPUWriteMemoryFunc *mips_qemu_write[] = {
  63     &mips_qemu_writel,
  64     &mips_qemu_writel,
  65     &mips_qemu_writel,
  66 };
  67
  68 static CPUReadMemoryFunc *mips_qemu_read[] = {
  69     &mips_qemu_readl,
  70     &mips_qemu_readl,
  71     &mips_qemu_readl,
  72 };
  73
  74 static int mips_qemu_iomemtype = 0;
  75
  76 void load_kernel (CPUState *env, int ram_size, const char *kernel_filename,
  77                   const char *kernel_cmdline,
  78                   const char *initrd_filename)
  79 {
  80     int64_t entry = 0;
  81     long kernel_size, initrd_size;
  82
  83     kernel_size = load_elf(kernel_filename, VIRT_TO_PHYS_ADDEND, &entry);
  84     if (kernel_size >= 0) {
  85         if ((entry & ~0x7fffffffULL) == 0x80000000)
  86             entry = (int32_t)entry;
  87         env->PC = entry;
  88     } else {
  89         kernel_size = load_image(kernel_filename,
  90                                  phys_ram_base + KERNEL_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
  91         if (kernel_size < 0) {
  92             fprintf(stderr, "qemu: could not load kernel '%s'\n",
  93                     kernel_filename);
  94             exit(1);
  95         }
  96         env->PC = KERNEL_LOAD_ADDR;
  97     }
  98
  99     /* load initrd */
 100     initrd_size = 0;
 101     if (initrd_filename) {
 102         initrd_size = load_image(initrd_filename,
 103                                  phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND);
 104         if (initrd_size == (target_ulong) -1) {
 105             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 106                     initrd_filename);
 107             exit(1);
 108         }
 109     }
 110
 111     /* Store command line.  */
 112     if (initrd_size > 0) {
 113         int ret;
 114         ret = sprintf(phys_ram_base + (16 << 20) - 256,
 115                       "rd_start=0x" TLSZ " rd_size=%li ",
 116                       INITRD_LOAD_ADDR,
 117                       initrd_size);
 118         strcpy (phys_ram_base + (16 << 20) - 256 + ret, kernel_cmdline);
 119     }
 120     else {
 121         strcpy (phys_ram_base + (16 << 20) - 256, kernel_cmdline);
 122     }
 123
 124     *(int *)(phys_ram_base + (16 << 20) - 260) = tswap32 (0x12345678);
 125     *(int *)(phys_ram_base + (16 << 20) - 264) = tswap32 (ram_size);
 126 }
 127
 128 static void main_cpu_reset(void *opaque)
 129 {
 130     CPUState *env = opaque;
 131     cpu_reset(env);
 132
 133     if (env->kernel_filename)
 134         load_kernel (env, env->ram_size, env->kernel_filename,
 135                      env->kernel_cmdline, env->initrd_filename);
 136 }
 137
 138 void mips_r4k_init (int ram_size, int vga_ram_size, int boot_device,
 139                     DisplayState *ds, const char **fd_filename, int snapshot,
 140                     const char *kernel_filename, const char *kernel_cmdline,
 141                     const char *initrd_filename)
 142 {
 143     char buf[1024];
 144     unsigned long bios_offset;
 145     int ret;
 146     CPUState *env;
 147     static RTCState *rtc_state;
 148     int i;
 149
 150     env = cpu_init();
 151     register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
 152     qemu_register_reset(main_cpu_reset, env);
 153
 154     /* allocate RAM */
 155     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 156
 157     if (!mips_qemu_iomemtype) {
 158         mips_qemu_iomemtype = cpu_register_io_memory(0, mips_qemu_read,
 159                                                      mips_qemu_write, NULL);
 160     }
 161     cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
 162
 163     /* Try to load a BIOS image. If this fails, we continue regardless,
 164        but initialize the hardware ourselves. When a kernel gets
 165        preloaded we also initialize the hardware, since the BIOS wasn't
 166        run. */
 167     bios_offset = ram_size + vga_ram_size;
 168     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
 169     ret = load_image(buf, phys_ram_base + bios_offset);
 170     if (ret == BIOS_SIZE) {
 171         cpu_register_physical_memory((uint32_t)(0x1fc00000),
 172                                      BIOS_SIZE, bios_offset | IO_MEM_ROM);
 173     } else {
 174         /* not fatal */
 175         fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
 176                 buf);
 177     }
 178
 179     if (kernel_filename) {
 180         load_kernel (env, ram_size, kernel_filename, kernel_cmdline,
 181                      initrd_filename);
 182         env->ram_size = ram_size;
 183         env->kernel_filename = kernel_filename;
 184         env->kernel_cmdline = kernel_cmdline;
 185         env->initrd_filename = initrd_filename;
 186     }
 187
 188     /* Init CPU internal devices */
 189     cpu_mips_clock_init(env);
 190     cpu_mips_irqctrl_init();
 191
 192     rtc_state = rtc_init(0x70, 8);
 193
 194     /* Register 64 KB of ISA IO space at 0x14000000 */
 195     isa_mmio_init(0x14000000, 0x00010000);
 196     isa_mem_base = 0x10000000;
 197
 198     isa_pic = pic_init(pic_irq_request, env);
 199     pit = pit_init(0x40, 0);
 200
 201     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 202         if (serial_hds[i]) {
 203             serial_init(&pic_set_irq_new, isa_pic,
 204                         serial_io[i], serial_irq[i], serial_hds[i]);
 205         }
 206     }
 207
 208     isa_vga_init(ds, phys_ram_base + ram_size, ram_size,
 209                  vga_ram_size);
 210
 211     if (nd_table[0].vlan) {
 212         if (nd_table[0].model == NULL
 213             || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
 214             isa_ne2000_init(0x300, 9, &nd_table[0]);
 215         } else {
 216             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
 217             exit (1);
 218         }
 219     }
 220
 221     for(i = 0; i < 2; i++)
 222         isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
 223                      bs_table[2 * i], bs_table[2 * i + 1]);
 224 }
 225
 226 QEMUMachine mips_machine = {
 227     "mips",
 228     "mips r4k platform",
 229     mips_r4k_init,
 230 };