hw/misc/arm_l2x0.c

   1 /*
   2  * ARM dummy L210, L220, PL310 cache controller.
   3  *
   4  * Copyright (c) 2010-2012 Calxeda
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or any later version, as published by the Free Software
   9  * Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  *
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "hw/qdev-properties.h"
  23 #include "hw/sysbus.h"
  24 #include "migration/vmstate.h"
  25 #include "qemu/log.h"
  26 #include "qemu/module.h"
  27 #include "qom/object.h"
  28
  29 /* L2C-310 r3p2 */
  30 #define CACHE_ID 0x410000c8
  31
  32 #define TYPE_ARM_L2X0 "l2x0"
  33 typedef struct L2x0State L2x0State;
  34 #define ARM_L2X0(obj) OBJECT_CHECK(L2x0State, (obj), TYPE_ARM_L2X0)
  35
  36 struct L2x0State {
  37     SysBusDevice parent_obj;
  38
  39     MemoryRegion iomem;
  40     uint32_t cache_type;
  41     uint32_t ctrl;
  42     uint32_t aux_ctrl;
  43     uint32_t data_ctrl;
  44     uint32_t tag_ctrl;
  45     uint32_t filter_start;
  46     uint32_t filter_end;
  47 };
  48
  49 static const VMStateDescription vmstate_l2x0 = {
  50     .name = "l2x0",
  51     .version_id = 1,
  52     .minimum_version_id = 1,
  53     .fields = (VMStateField[]) {
  54         VMSTATE_UINT32(ctrl, L2x0State),
  55         VMSTATE_UINT32(aux_ctrl, L2x0State),
  56         VMSTATE_UINT32(data_ctrl, L2x0State),
  57         VMSTATE_UINT32(tag_ctrl, L2x0State),
  58         VMSTATE_UINT32(filter_start, L2x0State),
  59         VMSTATE_UINT32(filter_end, L2x0State),
  60         VMSTATE_END_OF_LIST()
  61     }
  62 };
  63
  64
  65 static uint64_t l2x0_priv_read(void *opaque, hwaddr offset,
  66                                unsigned size)
  67 {
  68     uint32_t cache_data;
  69     L2x0State *s = (L2x0State *)opaque;
  70     offset &= 0xfff;
  71     if (offset >= 0x730 && offset < 0x800) {
  72         return 0; /* cache ops complete */
  73     }
  74     switch (offset) {
  75     case 0:
  76         return CACHE_ID;
  77     case 0x4:
  78         /* aux_ctrl values affect cache_type values */
  79         cache_data = (s->aux_ctrl & (7 << 17)) >> 15;
  80         cache_data |= (s->aux_ctrl & (1 << 16)) >> 16;
  81         return s->cache_type |= (cache_data << 18) | (cache_data << 6);
  82     case 0x100:
  83         return s->ctrl;
  84     case 0x104:
  85         return s->aux_ctrl;
  86     case 0x108:
  87         return s->tag_ctrl;
  88     case 0x10C:
  89         return s->data_ctrl;
  90     case 0xC00:
  91         return s->filter_start;
  92     case 0xC04:
  93         return s->filter_end;
  94     case 0xF40:
  95         return 0;
  96     case 0xF60:
  97         return 0;
  98     case 0xF80:
  99         return 0;
 100     default:
 101         qemu_log_mask(LOG_GUEST_ERROR,
 102                       "l2x0_priv_read: Bad offset %x\n", (int)offset);
 103         break;
 104     }
 105     return 0;
 106 }
 107
 108 static void l2x0_priv_write(void *opaque, hwaddr offset,
 109                             uint64_t value, unsigned size)
 110 {
 111     L2x0State *s = (L2x0State *)opaque;
 112     offset &= 0xfff;
 113     if (offset >= 0x730 && offset < 0x800) {
 114         /* ignore */
 115         return;
 116     }
 117     switch (offset) {
 118     case 0x100:
 119         s->ctrl = value & 1;
 120         break;
 121     case 0x104:
 122         s->aux_ctrl = value;
 123         break;
 124     case 0x108:
 125         s->tag_ctrl = value;
 126         break;
 127     case 0x10C:
 128         s->data_ctrl = value;
 129         break;
 130     case 0xC00:
 131         s->filter_start = value;
 132         break;
 133     case 0xC04:
 134         s->filter_end = value;
 135         break;
 136     case 0xF40:
 137         return;
 138     case 0xF60:
 139         return;
 140     case 0xF80:
 141         return;
 142     default:
 143         qemu_log_mask(LOG_GUEST_ERROR,
 144                       "l2x0_priv_write: Bad offset %x\n", (int)offset);
 145         break;
 146     }
 147 }
 148
 149 static void l2x0_priv_reset(DeviceState *dev)
 150 {
 151     L2x0State *s = ARM_L2X0(dev);
 152
 153     s->ctrl = 0;
 154     s->aux_ctrl = 0x02020000;
 155     s->tag_ctrl = 0;
 156     s->data_ctrl = 0;
 157     s->filter_start = 0;
 158     s->filter_end = 0;
 159 }
 160
 161 static const MemoryRegionOps l2x0_mem_ops = {
 162     .read = l2x0_priv_read,
 163     .write = l2x0_priv_write,
 164     .endianness = DEVICE_NATIVE_ENDIAN,
 165  };
 166
 167 static void l2x0_priv_init(Object *obj)
 168 {
 169     L2x0State *s = ARM_L2X0(obj);
 170     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 171
 172     memory_region_init_io(&s->iomem, obj, &l2x0_mem_ops, s,
 173                           "l2x0_cc", 0x1000);
 174     sysbus_init_mmio(dev, &s->iomem);
 175 }
 176
 177 static Property l2x0_properties[] = {
 178     DEFINE_PROP_UINT32("cache-type", L2x0State, cache_type, 0x1c100100),
 179     DEFINE_PROP_END_OF_LIST(),
 180 };
 181
 182 static void l2x0_class_init(ObjectClass *klass, void *data)
 183 {
 184     DeviceClass *dc = DEVICE_CLASS(klass);
 185
 186     dc->vmsd = &vmstate_l2x0;
 187     device_class_set_props(dc, l2x0_properties);
 188     dc->reset = l2x0_priv_reset;
 189 }
 190
 191 static const TypeInfo l2x0_info = {
 192     .name = TYPE_ARM_L2X0,
 193     .parent = TYPE_SYS_BUS_DEVICE,
 194     .instance_size = sizeof(L2x0State),
 195     .instance_init = l2x0_priv_init,
 196     .class_init = l2x0_class_init,
 197 };
 198
 199 static void l2x0_register_types(void)
 200 {
 201     type_register_static(&l2x0_info);
 202 }
 203
 204 type_init(l2x0_register_types)