hw/misc/milkymist-hpdmc.c

   1 /*
   2  *  QEMU model of the Milkymist High Performance Dynamic Memory Controller.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://milkymist.walle.cc/socdoc/hpdmc.pdf
  22  */
  23
  24 #include "qemu/osdep.h"
  25 #include "hw/sysbus.h"
  26 #include "migration/vmstate.h"
  27 #include "trace.h"
  28 #include "qemu/error-report.h"
  29 #include "qemu/module.h"
  30 #include "qom/object.h"
  31
  32 enum {
  33     R_SYSTEM = 0,
  34     R_BYPASS,
  35     R_TIMING,
  36     R_IODELAY,
  37     R_MAX
  38 };
  39
  40 enum {
  41     IODELAY_DQSDELAY_RDY = (1<<5),
  42     IODELAY_PLL1_LOCKED  = (1<<6),
  43     IODELAY_PLL2_LOCKED  = (1<<7),
  44 };
  45
  46 #define TYPE_MILKYMIST_HPDMC "milkymist-hpdmc"
  47 typedef struct MilkymistHpdmcState MilkymistHpdmcState;
  48 #define MILKYMIST_HPDMC(obj) \
  49     OBJECT_CHECK(MilkymistHpdmcState, (obj), TYPE_MILKYMIST_HPDMC)
  50
  51 struct MilkymistHpdmcState {
  52     SysBusDevice parent_obj;
  53
  54     MemoryRegion regs_region;
  55
  56     uint32_t regs[R_MAX];
  57 };
  58
  59 static uint64_t hpdmc_read(void *opaque, hwaddr addr,
  60                            unsigned size)
  61 {
  62     MilkymistHpdmcState *s = opaque;
  63     uint32_t r = 0;
  64
  65     addr >>= 2;
  66     switch (addr) {
  67     case R_SYSTEM:
  68     case R_BYPASS:
  69     case R_TIMING:
  70     case R_IODELAY:
  71         r = s->regs[addr];
  72         break;
  73
  74     default:
  75         error_report("milkymist_hpdmc: read access to unknown register 0x"
  76                 TARGET_FMT_plx, addr << 2);
  77         break;
  78     }
  79
  80     trace_milkymist_hpdmc_memory_read(addr << 2, r);
  81
  82     return r;
  83 }
  84
  85 static void hpdmc_write(void *opaque, hwaddr addr, uint64_t value,
  86                         unsigned size)
  87 {
  88     MilkymistHpdmcState *s = opaque;
  89
  90     trace_milkymist_hpdmc_memory_write(addr, value);
  91
  92     addr >>= 2;
  93     switch (addr) {
  94     case R_SYSTEM:
  95     case R_BYPASS:
  96     case R_TIMING:
  97         s->regs[addr] = value;
  98         break;
  99     case R_IODELAY:
 100         /* ignore writes */
 101         break;
 102
 103     default:
 104         error_report("milkymist_hpdmc: write access to unknown register 0x"
 105                 TARGET_FMT_plx, addr << 2);
 106         break;
 107     }
 108 }
 109
 110 static const MemoryRegionOps hpdmc_mmio_ops = {
 111     .read = hpdmc_read,
 112     .write = hpdmc_write,
 113     .valid = {
 114         .min_access_size = 4,
 115         .max_access_size = 4,
 116     },
 117     .endianness = DEVICE_NATIVE_ENDIAN,
 118 };
 119
 120 static void milkymist_hpdmc_reset(DeviceState *d)
 121 {
 122     MilkymistHpdmcState *s = MILKYMIST_HPDMC(d);
 123     int i;
 124
 125     for (i = 0; i < R_MAX; i++) {
 126         s->regs[i] = 0;
 127     }
 128
 129     /* defaults */
 130     s->regs[R_IODELAY] = IODELAY_DQSDELAY_RDY | IODELAY_PLL1_LOCKED
 131                          | IODELAY_PLL2_LOCKED;
 132 }
 133
 134 static void milkymist_hpdmc_realize(DeviceState *dev, Error **errp)
 135 {
 136     MilkymistHpdmcState *s = MILKYMIST_HPDMC(dev);
 137
 138     memory_region_init_io(&s->regs_region, OBJECT(dev), &hpdmc_mmio_ops, s,
 139             "milkymist-hpdmc", R_MAX * 4);
 140     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->regs_region);
 141 }
 142
 143 static const VMStateDescription vmstate_milkymist_hpdmc = {
 144     .name = "milkymist-hpdmc",
 145     .version_id = 1,
 146     .minimum_version_id = 1,
 147     .fields = (VMStateField[]) {
 148         VMSTATE_UINT32_ARRAY(regs, MilkymistHpdmcState, R_MAX),
 149         VMSTATE_END_OF_LIST()
 150     }
 151 };
 152
 153 static void milkymist_hpdmc_class_init(ObjectClass *klass, void *data)
 154 {
 155     DeviceClass *dc = DEVICE_CLASS(klass);
 156
 157     dc->realize = milkymist_hpdmc_realize;
 158     dc->reset = milkymist_hpdmc_reset;
 159     dc->vmsd = &vmstate_milkymist_hpdmc;
 160 }
 161
 162 static const TypeInfo milkymist_hpdmc_info = {
 163     .name          = TYPE_MILKYMIST_HPDMC,
 164     .parent        = TYPE_SYS_BUS_DEVICE,
 165     .instance_size = sizeof(MilkymistHpdmcState),
 166     .class_init    = milkymist_hpdmc_class_init,
 167 };
 168
 169 static void milkymist_hpdmc_register_types(void)
 170 {
 171     type_register_static(&milkymist_hpdmc_info);
 172 }
 173
 174 type_init(milkymist_hpdmc_register_types)