hw/misc/mips_cpc.c

   1 /*
   2  * Cluster Power Controller emulation
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "qemu/log.h"
  24 #include "qemu/module.h"
  25 #include "hw/sysbus.h"
  26 #include "migration/vmstate.h"
  27
  28 #include "hw/misc/mips_cpc.h"
  29
  30 static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc)
  31 {
  32     return (1ULL << cpc->num_vp) - 1;
  33 }
  34
  35 static void mips_cpu_reset_async_work(CPUState *cs, run_on_cpu_data data)
  36 {
  37     MIPSCPCState *cpc = (MIPSCPCState *) data.host_ptr;
  38
  39     cpu_reset(cs);
  40     cpc->vp_running |= 1ULL << cs->cpu_index;
  41 }
  42
  43 static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
  44 {
  45     CPUState *cs = first_cpu;
  46
  47     CPU_FOREACH(cs) {
  48         uint64_t i = 1ULL << cs->cpu_index;
  49         if (i & vp_run & ~cpc->vp_running) {
  50             /*
  51              * To avoid racing with a CPU we are just kicking off.
  52              * We do the final bit of preparation for the work in
  53              * the target CPUs context.
  54              */
  55             async_safe_run_on_cpu(cs, mips_cpu_reset_async_work,
  56                                   RUN_ON_CPU_HOST_PTR(cpc));
  57         }
  58     }
  59 }
  60
  61 static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
  62 {
  63     CPUState *cs = first_cpu;
  64
  65     CPU_FOREACH(cs) {
  66         uint64_t i = 1ULL << cs->cpu_index;
  67         if (i & vp_stop & cpc->vp_running) {
  68             cpu_interrupt(cs, CPU_INTERRUPT_HALT);
  69             cpc->vp_running &= ~i;
  70         }
  71     }
  72 }
  73
  74 static void cpc_write(void *opaque, hwaddr offset, uint64_t data,
  75                       unsigned size)
  76 {
  77     MIPSCPCState *s = opaque;
  78
  79     switch (offset) {
  80     case CPC_CL_BASE_OFS + CPC_VP_RUN_OFS:
  81     case CPC_CO_BASE_OFS + CPC_VP_RUN_OFS:
  82         cpc_run_vp(s, data & cpc_vp_run_mask(s));
  83         break;
  84     case CPC_CL_BASE_OFS + CPC_VP_STOP_OFS:
  85     case CPC_CO_BASE_OFS + CPC_VP_STOP_OFS:
  86         cpc_stop_vp(s, data & cpc_vp_run_mask(s));
  87         break;
  88     default:
  89         qemu_log_mask(LOG_UNIMP,
  90                       "%s: Bad offset 0x%x\n",  __func__, (int)offset);
  91         break;
  92     }
  93
  94     return;
  95 }
  96
  97 static uint64_t cpc_read(void *opaque, hwaddr offset, unsigned size)
  98 {
  99     MIPSCPCState *s = opaque;
 100
 101     switch (offset) {
 102     case CPC_CL_BASE_OFS + CPC_VP_RUNNING_OFS:
 103     case CPC_CO_BASE_OFS + CPC_VP_RUNNING_OFS:
 104         return s->vp_running;
 105     default:
 106         qemu_log_mask(LOG_UNIMP,
 107                       "%s: Bad offset 0x%x\n",  __func__, (int)offset);
 108         return 0;
 109     }
 110 }
 111
 112 static const MemoryRegionOps cpc_ops = {
 113     .read = cpc_read,
 114     .write = cpc_write,
 115     .endianness = DEVICE_NATIVE_ENDIAN,
 116     .impl = {
 117         .max_access_size = 8,
 118     },
 119 };
 120
 121 static void mips_cpc_init(Object *obj)
 122 {
 123     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 124     MIPSCPCState *s = MIPS_CPC(obj);
 125
 126     memory_region_init_io(&s->mr, OBJECT(s), &cpc_ops, s, "mips-cpc",
 127                           CPC_ADDRSPACE_SZ);
 128     sysbus_init_mmio(sbd, &s->mr);
 129 }
 130
 131 static void mips_cpc_realize(DeviceState *dev, Error **errp)
 132 {
 133     MIPSCPCState *s = MIPS_CPC(dev);
 134
 135     if (s->vp_start_running > cpc_vp_run_mask(s)) {
 136         error_setg(errp,
 137                    "incorrect vp_start_running 0x%" PRIx64 " for num_vp = %d",
 138                    s->vp_running, s->num_vp);
 139         return;
 140     }
 141 }
 142
 143 static void mips_cpc_reset(DeviceState *dev)
 144 {
 145     MIPSCPCState *s = MIPS_CPC(dev);
 146
 147     /* Reflect the fact that all VPs are halted on reset */
 148     s->vp_running = 0;
 149
 150     /* Put selected VPs into run state */
 151     cpc_run_vp(s, s->vp_start_running);
 152 }
 153
 154 static const VMStateDescription vmstate_mips_cpc = {
 155     .name = "mips-cpc",
 156     .version_id = 0,
 157     .minimum_version_id = 0,
 158     .fields = (VMStateField[]) {
 159         VMSTATE_UINT64(vp_running, MIPSCPCState),
 160         VMSTATE_END_OF_LIST()
 161     },
 162 };
 163
 164 static Property mips_cpc_properties[] = {
 165     DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1),
 166     DEFINE_PROP_UINT64("vp-start-running", MIPSCPCState, vp_start_running, 0x1),
 167     DEFINE_PROP_END_OF_LIST(),
 168 };
 169
 170 static void mips_cpc_class_init(ObjectClass *klass, void *data)
 171 {
 172     DeviceClass *dc = DEVICE_CLASS(klass);
 173
 174     dc->realize = mips_cpc_realize;
 175     dc->reset = mips_cpc_reset;
 176     dc->vmsd = &vmstate_mips_cpc;
 177     dc->props = mips_cpc_properties;
 178 }
 179
 180 static const TypeInfo mips_cpc_info = {
 181     .name          = TYPE_MIPS_CPC,
 182     .parent        = TYPE_SYS_BUS_DEVICE,
 183     .instance_size = sizeof(MIPSCPCState),
 184     .instance_init = mips_cpc_init,
 185     .class_init    = mips_cpc_class_init,
 186 };
 187
 188 static void mips_cpc_register_types(void)
 189 {
 190     type_register_static(&mips_cpc_info);
 191 }
 192
 193 type_init(mips_cpc_register_types)