hw/misc/mips_cpc.c

   1 /*
   2  * Cluster Power Controller emulation
   3  *
   4  * Copyright (c) 2016 Imagination Technologies
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include "qemu/osdep.h"
  21 #include "qapi/error.h"
  22 #include "cpu.h"
  23 #include "qemu/log.h"
  24 #include "hw/sysbus.h"
  25
  26 #include "hw/misc/mips_cpc.h"
  27
  28 static inline uint64_t cpc_vp_run_mask(MIPSCPCState *cpc)
  29 {
  30     return (1ULL << cpc->num_vp) - 1;
  31 }
  32
  33 static void cpc_run_vp(MIPSCPCState *cpc, uint64_t vp_run)
  34 {
  35     CPUState *cs = first_cpu;
  36
  37     CPU_FOREACH(cs) {
  38         uint64_t i = 1ULL << cs->cpu_index;
  39         if (i & vp_run & ~cpc->vp_running) {
  40             cpu_interrupt(cs, CPU_INTERRUPT_WAKE);
  41             cpc->vp_running |= i;
  42         }
  43     }
  44 }
  45
  46 static void cpc_stop_vp(MIPSCPCState *cpc, uint64_t vp_stop)
  47 {
  48     CPUState *cs = first_cpu;
  49
  50     CPU_FOREACH(cs) {
  51         uint64_t i = 1ULL << cs->cpu_index;
  52         if (i & vp_stop & cpc->vp_running) {
  53             cs->halted = 1;
  54             cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
  55             cpc->vp_running &= ~i;
  56         }
  57     }
  58 }
  59
  60 static void cpc_write(void *opaque, hwaddr offset, uint64_t data,
  61                       unsigned size)
  62 {
  63     MIPSCPCState *s = opaque;
  64
  65     switch (offset) {
  66     case CPC_CL_BASE_OFS + CPC_VP_RUN_OFS:
  67     case CPC_CO_BASE_OFS + CPC_VP_RUN_OFS:
  68         cpc_run_vp(s, data & cpc_vp_run_mask(s));
  69         break;
  70     case CPC_CL_BASE_OFS + CPC_VP_STOP_OFS:
  71     case CPC_CO_BASE_OFS + CPC_VP_STOP_OFS:
  72         cpc_stop_vp(s, data & cpc_vp_run_mask(s));
  73         break;
  74     default:
  75         qemu_log_mask(LOG_UNIMP,
  76                       "%s: Bad offset 0x%x\n",  __func__, (int)offset);
  77         break;
  78     }
  79
  80     return;
  81 }
  82
  83 static uint64_t cpc_read(void *opaque, hwaddr offset, unsigned size)
  84 {
  85     MIPSCPCState *s = opaque;
  86
  87     switch (offset) {
  88     case CPC_CL_BASE_OFS + CPC_VP_RUNNING_OFS:
  89     case CPC_CO_BASE_OFS + CPC_VP_RUNNING_OFS:
  90         return s->vp_running;
  91     default:
  92         qemu_log_mask(LOG_UNIMP,
  93                       "%s: Bad offset 0x%x\n",  __func__, (int)offset);
  94         return 0;
  95     }
  96 }
  97
  98 static const MemoryRegionOps cpc_ops = {
  99     .read = cpc_read,
 100     .write = cpc_write,
 101     .endianness = DEVICE_NATIVE_ENDIAN,
 102     .impl = {
 103         .max_access_size = 8,
 104     },
 105 };
 106
 107 static void mips_cpc_init(Object *obj)
 108 {
 109     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 110     MIPSCPCState *s = MIPS_CPC(obj);
 111
 112     memory_region_init_io(&s->mr, OBJECT(s), &cpc_ops, s, "mips-cpc",
 113                           CPC_ADDRSPACE_SZ);
 114     sysbus_init_mmio(sbd, &s->mr);
 115 }
 116
 117 static void mips_cpc_realize(DeviceState *dev, Error **errp)
 118 {
 119     MIPSCPCState *s = MIPS_CPC(dev);
 120
 121     if (s->vp_start_running > cpc_vp_run_mask(s)) {
 122         error_setg(errp,
 123                    "incorrect vp_start_running 0x%" PRIx64 " for num_vp = %d",
 124                    s->vp_running, s->num_vp);
 125         return;
 126     }
 127 }
 128
 129 static void mips_cpc_reset(DeviceState *dev)
 130 {
 131     MIPSCPCState *s = MIPS_CPC(dev);
 132
 133     /* Reflect the fact that all VPs are halted on reset */
 134     s->vp_running = 0;
 135
 136     /* Put selected VPs into run state */
 137     cpc_run_vp(s, s->vp_start_running);
 138 }
 139
 140 static const VMStateDescription vmstate_mips_cpc = {
 141     .name = "mips-cpc",
 142     .version_id = 0,
 143     .minimum_version_id = 0,
 144     .fields = (VMStateField[]) {
 145         VMSTATE_UINT64(vp_running, MIPSCPCState),
 146         VMSTATE_END_OF_LIST()
 147     },
 148 };
 149
 150 static Property mips_cpc_properties[] = {
 151     DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1),
 152     DEFINE_PROP_UINT64("vp-start-running", MIPSCPCState, vp_start_running, 0x1),
 153     DEFINE_PROP_END_OF_LIST(),
 154 };
 155
 156 static void mips_cpc_class_init(ObjectClass *klass, void *data)
 157 {
 158     DeviceClass *dc = DEVICE_CLASS(klass);
 159
 160     dc->realize = mips_cpc_realize;
 161     dc->reset = mips_cpc_reset;
 162     dc->vmsd = &vmstate_mips_cpc;
 163     dc->props = mips_cpc_properties;
 164 }
 165
 166 static const TypeInfo mips_cpc_info = {
 167     .name          = TYPE_MIPS_CPC,
 168     .parent        = TYPE_SYS_BUS_DEVICE,
 169     .instance_size = sizeof(MIPSCPCState),
 170     .instance_init = mips_cpc_init,
 171     .class_init    = mips_cpc_class_init,
 172 };
 173
 174 static void mips_cpc_register_types(void)
 175 {
 176     type_register_static(&mips_cpc_info);
 177 }
 178
 179 type_init(mips_cpc_register_types)