hw/misc/mos6522.c

   1 /*
   2  * QEMU MOS6522 VIA emulation
   3  *
   4  * Copyright (c) 2004-2007 Fabrice Bellard
   5  * Copyright (c) 2007 Jocelyn Mayer
   6  * Copyright (c) 2018 Mark Cave-Ayland
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "hw/input/adb.h"
  29 #include "hw/irq.h"
  30 #include "hw/misc/mos6522.h"
  31 #include "hw/qdev-properties.h"
  32 #include "migration/vmstate.h"
  33 #include "qemu/timer.h"
  34 #include "sysemu/sysemu.h"
  35 #include "qemu/cutils.h"
  36 #include "qemu/log.h"
  37 #include "qemu/module.h"
  38 #include "trace.h"
  39
  40 /* XXX: implement all timer modes */
  41
  42 static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti,
  43                                  int64_t current_time);
  44
  45 static void mos6522_update_irq(MOS6522State *s)
  46 {
  47     if (s->ifr & s->ier) {
  48         qemu_irq_raise(s->irq);
  49     } else {
  50         qemu_irq_lower(s->irq);
  51     }
  52 }
  53
  54 static uint64_t get_counter_value(MOS6522State *s, MOS6522Timer *ti)
  55 {
  56     MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
  57
  58     if (ti->index == 0) {
  59         return mdc->get_timer1_counter_value(s, ti);
  60     } else {
  61         return mdc->get_timer2_counter_value(s, ti);
  62     }
  63 }
  64
  65 static uint64_t get_load_time(MOS6522State *s, MOS6522Timer *ti)
  66 {
  67     MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
  68
  69     if (ti->index == 0) {
  70         return mdc->get_timer1_load_time(s, ti);
  71     } else {
  72         return mdc->get_timer2_load_time(s, ti);
  73     }
  74 }
  75
  76 static unsigned int get_counter(MOS6522State *s, MOS6522Timer *ti)
  77 {
  78     int64_t d;
  79     unsigned int counter;
  80
  81     d = get_counter_value(s, ti);
  82
  83     if (ti->index == 0) {
  84         /* the timer goes down from latch to -1 (period of latch + 2) */
  85         if (d <= (ti->counter_value + 1)) {
  86             counter = (ti->counter_value - d) & 0xffff;
  87         } else {
  88             counter = (d - (ti->counter_value + 1)) % (ti->latch + 2);
  89             counter = (ti->latch - counter) & 0xffff;
  90         }
  91     } else {
  92         counter = (ti->counter_value - d) & 0xffff;
  93     }
  94     return counter;
  95 }
  96
  97 static void set_counter(MOS6522State *s, MOS6522Timer *ti, unsigned int val)
  98 {
  99     trace_mos6522_set_counter(1 + ti->index, val);
 100     ti->load_time = get_load_time(s, ti);
 101     ti->counter_value = val;
 102     mos6522_timer_update(s, ti, ti->load_time);
 103 }
 104
 105 static int64_t get_next_irq_time(MOS6522State *s, MOS6522Timer *ti,
 106                                  int64_t current_time)
 107 {
 108     int64_t d, next_time;
 109     unsigned int counter;
 110
 111     /* current counter value */
 112     d = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time,
 113                  ti->frequency, NANOSECONDS_PER_SECOND);
 114
 115     /* the timer goes down from latch to -1 (period of latch + 2) */
 116     if (d <= (ti->counter_value + 1)) {
 117         counter = (ti->counter_value - d) & 0xffff;
 118     } else {
 119         counter = (d - (ti->counter_value + 1)) % (ti->latch + 2);
 120         counter = (ti->latch - counter) & 0xffff;
 121     }
 122
 123     /* Note: we consider the irq is raised on 0 */
 124     if (counter == 0xffff) {
 125         next_time = d + ti->latch + 1;
 126     } else if (counter == 0) {
 127         next_time = d + ti->latch + 2;
 128     } else {
 129         next_time = d + counter;
 130     }
 131     trace_mos6522_get_next_irq_time(ti->latch, d, next_time - d);
 132     next_time = muldiv64(next_time, NANOSECONDS_PER_SECOND, ti->frequency) +
 133                          ti->load_time;
 134     if (next_time <= current_time) {
 135         next_time = current_time + 1;
 136     }
 137     return next_time;
 138 }
 139
 140 static void mos6522_timer_update(MOS6522State *s, MOS6522Timer *ti,
 141                                  int64_t current_time)
 142 {
 143     if (!ti->timer) {
 144         return;
 145     }
 146     if (ti->index == 0 && (s->acr & T1MODE) != T1MODE_CONT) {
 147         timer_del(ti->timer);
 148     } else {
 149         ti->next_irq_time = get_next_irq_time(s, ti, current_time);
 150         timer_mod(ti->timer, ti->next_irq_time);
 151     }
 152 }
 153
 154 static void mos6522_timer1(void *opaque)
 155 {
 156     MOS6522State *s = opaque;
 157     MOS6522Timer *ti = &s->timers[0];
 158
 159     mos6522_timer_update(s, ti, ti->next_irq_time);
 160     s->ifr |= T1_INT;
 161     mos6522_update_irq(s);
 162 }
 163
 164 static void mos6522_timer2(void *opaque)
 165 {
 166     MOS6522State *s = opaque;
 167     MOS6522Timer *ti = &s->timers[1];
 168
 169     mos6522_timer_update(s, ti, ti->next_irq_time);
 170     s->ifr |= T2_INT;
 171     mos6522_update_irq(s);
 172 }
 173
 174 static void mos6522_set_sr_int(MOS6522State *s)
 175 {
 176     trace_mos6522_set_sr_int();
 177     s->ifr |= SR_INT;
 178     mos6522_update_irq(s);
 179 }
 180
 181 static uint64_t mos6522_get_counter_value(MOS6522State *s, MOS6522Timer *ti)
 182 {
 183     return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ti->load_time,
 184                     ti->frequency, NANOSECONDS_PER_SECOND);
 185 }
 186
 187 static uint64_t mos6522_get_load_time(MOS6522State *s, MOS6522Timer *ti)
 188 {
 189     uint64_t load_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
 190
 191     return load_time;
 192 }
 193
 194 static void mos6522_portA_write(MOS6522State *s)
 195 {
 196     qemu_log_mask(LOG_UNIMP, "portA_write unimplemented\n");
 197 }
 198
 199 static void mos6522_portB_write(MOS6522State *s)
 200 {
 201     qemu_log_mask(LOG_UNIMP, "portB_write unimplemented\n");
 202 }
 203
 204 uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
 205 {
 206     MOS6522State *s = opaque;
 207     uint32_t val;
 208
 209     switch (addr) {
 210     case VIA_REG_B:
 211         val = s->b;
 212         break;
 213     case VIA_REG_A:
 214         val = s->a;
 215         break;
 216     case VIA_REG_DIRB:
 217         val = s->dirb;
 218         break;
 219     case VIA_REG_DIRA:
 220         val = s->dira;
 221         break;
 222     case VIA_REG_T1CL:
 223         val = get_counter(s, &s->timers[0]) & 0xff;
 224         s->ifr &= ~T1_INT;
 225         mos6522_update_irq(s);
 226         break;
 227     case VIA_REG_T1CH:
 228         val = get_counter(s, &s->timers[0]) >> 8;
 229         mos6522_update_irq(s);
 230         break;
 231     case VIA_REG_T1LL:
 232         val = s->timers[0].latch & 0xff;
 233         break;
 234     case VIA_REG_T1LH:
 235         /* XXX: check this */
 236         val = (s->timers[0].latch >> 8) & 0xff;
 237         break;
 238     case VIA_REG_T2CL:
 239         val = get_counter(s, &s->timers[1]) & 0xff;
 240         s->ifr &= ~T2_INT;
 241         mos6522_update_irq(s);
 242         break;
 243     case VIA_REG_T2CH:
 244         val = get_counter(s, &s->timers[1]) >> 8;
 245         break;
 246     case VIA_REG_SR:
 247         val = s->sr;
 248         s->ifr &= ~SR_INT;
 249         mos6522_update_irq(s);
 250         break;
 251     case VIA_REG_ACR:
 252         val = s->acr;
 253         break;
 254     case VIA_REG_PCR:
 255         val = s->pcr;
 256         break;
 257     case VIA_REG_IFR:
 258         val = s->ifr;
 259         if (s->ifr & s->ier) {
 260             val |= 0x80;
 261         }
 262         break;
 263     case VIA_REG_IER:
 264         val = s->ier | 0x80;
 265         break;
 266     default:
 267     case VIA_REG_ANH:
 268         val = s->anh;
 269         break;
 270     }
 271
 272     if (addr != VIA_REG_IFR || val != 0) {
 273         trace_mos6522_read(addr, val);
 274     }
 275
 276     return val;
 277 }
 278
 279 void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size)
 280 {
 281     MOS6522State *s = opaque;
 282     MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(s);
 283
 284     trace_mos6522_write(addr, val);
 285
 286     switch (addr) {
 287     case VIA_REG_B:
 288         s->b = (s->b & ~s->dirb) | (val & s->dirb);
 289         mdc->portB_write(s);
 290         break;
 291     case VIA_REG_A:
 292         s->a = (s->a & ~s->dira) | (val & s->dira);
 293         mdc->portA_write(s);
 294         break;
 295     case VIA_REG_DIRB:
 296         s->dirb = val;
 297         break;
 298     case VIA_REG_DIRA:
 299         s->dira = val;
 300         break;
 301     case VIA_REG_T1CL:
 302         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
 303         mos6522_timer_update(s, &s->timers[0],
 304                              qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 305         break;
 306     case VIA_REG_T1CH:
 307         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
 308         s->ifr &= ~T1_INT;
 309         set_counter(s, &s->timers[0], s->timers[0].latch);
 310         break;
 311     case VIA_REG_T1LL:
 312         s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
 313         mos6522_timer_update(s, &s->timers[0],
 314                              qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 315         break;
 316     case VIA_REG_T1LH:
 317         s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
 318         s->ifr &= ~T1_INT;
 319         mos6522_timer_update(s, &s->timers[0],
 320                              qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 321         break;
 322     case VIA_REG_T2CL:
 323         s->timers[1].latch = (s->timers[1].latch & 0xff00) | val;
 324         break;
 325     case VIA_REG_T2CH:
 326         /* To ensure T2 generates an interrupt on zero crossing with the
 327            common timer code, write the value directly from the latch to
 328            the counter */
 329         s->timers[1].latch = (s->timers[1].latch & 0xff) | (val << 8);
 330         s->ifr &= ~T2_INT;
 331         set_counter(s, &s->timers[1], s->timers[1].latch);
 332         break;
 333     case VIA_REG_SR:
 334         s->sr = val;
 335         break;
 336     case VIA_REG_ACR:
 337         s->acr = val;
 338         mos6522_timer_update(s, &s->timers[0],
 339                              qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
 340         break;
 341     case VIA_REG_PCR:
 342         s->pcr = val;
 343         break;
 344     case VIA_REG_IFR:
 345         /* reset bits */
 346         s->ifr &= ~val;
 347         mos6522_update_irq(s);
 348         break;
 349     case VIA_REG_IER:
 350         if (val & IER_SET) {
 351             /* set bits */
 352             s->ier |= val & 0x7f;
 353         } else {
 354             /* reset bits */
 355             s->ier &= ~val;
 356         }
 357         mos6522_update_irq(s);
 358         break;
 359     default:
 360     case VIA_REG_ANH:
 361         s->anh = val;
 362         break;
 363     }
 364 }
 365
 366 static const MemoryRegionOps mos6522_ops = {
 367     .read = mos6522_read,
 368     .write = mos6522_write,
 369     .endianness = DEVICE_NATIVE_ENDIAN,
 370     .valid = {
 371         .min_access_size = 1,
 372         .max_access_size = 1,
 373     },
 374 };
 375
 376 static const VMStateDescription vmstate_mos6522_timer = {
 377     .name = "mos6522_timer",
 378     .version_id = 0,
 379     .minimum_version_id = 0,
 380     .fields = (VMStateField[]) {
 381         VMSTATE_UINT16(latch, MOS6522Timer),
 382         VMSTATE_UINT16(counter_value, MOS6522Timer),
 383         VMSTATE_INT64(load_time, MOS6522Timer),
 384         VMSTATE_INT64(next_irq_time, MOS6522Timer),
 385         VMSTATE_TIMER_PTR(timer, MOS6522Timer),
 386         VMSTATE_END_OF_LIST()
 387     }
 388 };
 389
 390 const VMStateDescription vmstate_mos6522 = {
 391     .name = "mos6522",
 392     .version_id = 0,
 393     .minimum_version_id = 0,
 394     .fields = (VMStateField[]) {
 395         VMSTATE_UINT8(a, MOS6522State),
 396         VMSTATE_UINT8(b, MOS6522State),
 397         VMSTATE_UINT8(dira, MOS6522State),
 398         VMSTATE_UINT8(dirb, MOS6522State),
 399         VMSTATE_UINT8(sr, MOS6522State),
 400         VMSTATE_UINT8(acr, MOS6522State),
 401         VMSTATE_UINT8(pcr, MOS6522State),
 402         VMSTATE_UINT8(ifr, MOS6522State),
 403         VMSTATE_UINT8(ier, MOS6522State),
 404         VMSTATE_UINT8(anh, MOS6522State),
 405         VMSTATE_STRUCT_ARRAY(timers, MOS6522State, 2, 0,
 406                              vmstate_mos6522_timer, MOS6522Timer),
 407         VMSTATE_END_OF_LIST()
 408     }
 409 };
 410
 411 static void mos6522_reset(DeviceState *dev)
 412 {
 413     MOS6522State *s = MOS6522(dev);
 414
 415     s->b = 0;
 416     s->a = 0;
 417     s->dirb = 0xff;
 418     s->dira = 0;
 419     s->sr = 0;
 420     s->acr = 0;
 421     s->pcr = 0;
 422     s->ifr = 0;
 423     s->ier = 0;
 424     /* s->ier = T1_INT | SR_INT; */
 425     s->anh = 0;
 426
 427     s->timers[0].frequency = s->frequency;
 428     s->timers[0].latch = 0xffff;
 429     set_counter(s, &s->timers[0], 0xffff);
 430
 431     s->timers[1].frequency = s->frequency;
 432     s->timers[1].latch = 0xffff;
 433 }
 434
 435 static void mos6522_init(Object *obj)
 436 {
 437     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 438     MOS6522State *s = MOS6522(obj);
 439     int i;
 440
 441     memory_region_init_io(&s->mem, obj, &mos6522_ops, s, "mos6522", 0x10);
 442     sysbus_init_mmio(sbd, &s->mem);
 443     sysbus_init_irq(sbd, &s->irq);
 444
 445     for (i = 0; i < ARRAY_SIZE(s->timers); i++) {
 446         s->timers[i].index = i;
 447     }
 448
 449     s->timers[0].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer1, s);
 450     s->timers[1].timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, mos6522_timer2, s);
 451 }
 452
 453 static Property mos6522_properties[] = {
 454     DEFINE_PROP_UINT64("frequency", MOS6522State, frequency, 0),
 455     DEFINE_PROP_END_OF_LIST()
 456 };
 457
 458 static void mos6522_class_init(ObjectClass *oc, void *data)
 459 {
 460     DeviceClass *dc = DEVICE_CLASS(oc);
 461     MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc);
 462
 463     dc->reset = mos6522_reset;
 464     dc->vmsd = &vmstate_mos6522;
 465     dc->props = mos6522_properties;
 466     mdc->parent_reset = dc->reset;
 467     mdc->set_sr_int = mos6522_set_sr_int;
 468     mdc->portB_write = mos6522_portB_write;
 469     mdc->portA_write = mos6522_portA_write;
 470     mdc->update_irq = mos6522_update_irq;
 471     mdc->get_timer1_counter_value = mos6522_get_counter_value;
 472     mdc->get_timer2_counter_value = mos6522_get_counter_value;
 473     mdc->get_timer1_load_time = mos6522_get_load_time;
 474     mdc->get_timer2_load_time = mos6522_get_load_time;
 475 }
 476
 477 static const TypeInfo mos6522_type_info = {
 478     .name = TYPE_MOS6522,
 479     .parent = TYPE_SYS_BUS_DEVICE,
 480     .instance_size = sizeof(MOS6522State),
 481     .instance_init = mos6522_init,
 482     .abstract = true,
 483     .class_size = sizeof(MOS6522DeviceClass),
 484     .class_init = mos6522_class_init,
 485 };
 486
 487 static void mos6522_register_types(void)
 488 {
 489     type_register_static(&mos6522_type_info);
 490 }
 491
 492 type_init(mos6522_register_types)