2 * ARM TrustZone peripheral protection controller emulation
4 * Copyright (c) 2018 Linaro Limited
5 * Written by Peter Maydell
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
12 #include "qemu/osdep.h"
14 #include "qemu/module.h"
15 #include "qapi/error.h"
17 #include "hw/sysbus.h"
18 #include "hw/registerfields.h"
19 #include "hw/misc/tz-ppc.h"
21 static void tz_ppc_update_irq(TZPPC
*s
)
23 bool level
= s
->irq_status
&& s
->irq_enable
;
25 trace_tz_ppc_update_irq(level
);
26 qemu_set_irq(s
->irq
, level
);
29 static void tz_ppc_cfg_nonsec(void *opaque
, int n
, int level
)
31 TZPPC
*s
= TZ_PPC(opaque
);
33 assert(n
< TZ_NUM_PORTS
);
34 trace_tz_ppc_cfg_nonsec(n
, level
);
35 s
->cfg_nonsec
[n
] = level
;
38 static void tz_ppc_cfg_ap(void *opaque
, int n
, int level
)
40 TZPPC
*s
= TZ_PPC(opaque
);
42 assert(n
< TZ_NUM_PORTS
);
43 trace_tz_ppc_cfg_ap(n
, level
);
47 static void tz_ppc_cfg_sec_resp(void *opaque
, int n
, int level
)
49 TZPPC
*s
= TZ_PPC(opaque
);
51 trace_tz_ppc_cfg_sec_resp(level
);
52 s
->cfg_sec_resp
= level
;
55 static void tz_ppc_irq_enable(void *opaque
, int n
, int level
)
57 TZPPC
*s
= TZ_PPC(opaque
);
59 trace_tz_ppc_irq_enable(level
);
60 s
->irq_enable
= level
;
64 static void tz_ppc_irq_clear(void *opaque
, int n
, int level
)
66 TZPPC
*s
= TZ_PPC(opaque
);
68 trace_tz_ppc_irq_clear(level
);
72 s
->irq_status
= false;
77 static bool tz_ppc_check(TZPPC
*s
, int n
, MemTxAttrs attrs
)
79 /* Check whether to allow an access to port n; return true if
80 * the check passes, and false if the transaction must be blocked.
81 * If the latter, the caller must check cfg_sec_resp to determine
82 * whether to abort or RAZ/WI the transaction.
84 * + nonsec_mask suppresses any check of the secure attribute
85 * + otherwise, block if cfg_nonsec is 1 and transaction is secure,
86 * or if cfg_nonsec is 0 and transaction is non-secure
87 * + block if transaction is usermode and cfg_ap is 0
89 if ((attrs
.secure
== s
->cfg_nonsec
[n
] && !(s
->nonsec_mask
& (1 << n
))) ||
90 (attrs
.user
&& !s
->cfg_ap
[n
])) {
91 /* Block the transaction. */
93 /* Note that holding irq_clear high suppresses interrupts */
102 static MemTxResult
tz_ppc_read(void *opaque
, hwaddr addr
, uint64_t *pdata
,
103 unsigned size
, MemTxAttrs attrs
)
105 TZPPCPort
*p
= opaque
;
108 AddressSpace
*as
= &p
->downstream_as
;
112 if (!tz_ppc_check(s
, n
, attrs
)) {
113 trace_tz_ppc_read_blocked(n
, addr
, attrs
.secure
, attrs
.user
);
114 if (s
->cfg_sec_resp
) {
124 data
= address_space_ldub(as
, addr
, attrs
, &res
);
127 data
= address_space_lduw_le(as
, addr
, attrs
, &res
);
130 data
= address_space_ldl_le(as
, addr
, attrs
, &res
);
133 data
= address_space_ldq_le(as
, addr
, attrs
, &res
);
136 g_assert_not_reached();
142 static MemTxResult
tz_ppc_write(void *opaque
, hwaddr addr
, uint64_t val
,
143 unsigned size
, MemTxAttrs attrs
)
145 TZPPCPort
*p
= opaque
;
147 AddressSpace
*as
= &p
->downstream_as
;
151 if (!tz_ppc_check(s
, n
, attrs
)) {
152 trace_tz_ppc_write_blocked(n
, addr
, attrs
.secure
, attrs
.user
);
153 if (s
->cfg_sec_resp
) {
162 address_space_stb(as
, addr
, val
, attrs
, &res
);
165 address_space_stw_le(as
, addr
, val
, attrs
, &res
);
168 address_space_stl_le(as
, addr
, val
, attrs
, &res
);
171 address_space_stq_le(as
, addr
, val
, attrs
, &res
);
174 g_assert_not_reached();
179 static const MemoryRegionOps tz_ppc_ops
= {
180 .read_with_attrs
= tz_ppc_read
,
181 .write_with_attrs
= tz_ppc_write
,
182 .endianness
= DEVICE_LITTLE_ENDIAN
,
185 static bool tz_ppc_dummy_accepts(void *opaque
, hwaddr addr
,
186 unsigned size
, bool is_write
,
190 * Board code should never map the upstream end of an unused port,
191 * so we should never try to make a memory access to it.
193 g_assert_not_reached();
196 static const MemoryRegionOps tz_ppc_dummy_ops
= {
197 .valid
.accepts
= tz_ppc_dummy_accepts
,
200 static void tz_ppc_reset(DeviceState
*dev
)
202 TZPPC
*s
= TZ_PPC(dev
);
204 trace_tz_ppc_reset();
205 s
->cfg_sec_resp
= false;
206 memset(s
->cfg_nonsec
, 0, sizeof(s
->cfg_nonsec
));
207 memset(s
->cfg_ap
, 0, sizeof(s
->cfg_ap
));
210 static void tz_ppc_init(Object
*obj
)
212 DeviceState
*dev
= DEVICE(obj
);
213 TZPPC
*s
= TZ_PPC(obj
);
215 qdev_init_gpio_in_named(dev
, tz_ppc_cfg_nonsec
, "cfg_nonsec", TZ_NUM_PORTS
);
216 qdev_init_gpio_in_named(dev
, tz_ppc_cfg_ap
, "cfg_ap", TZ_NUM_PORTS
);
217 qdev_init_gpio_in_named(dev
, tz_ppc_cfg_sec_resp
, "cfg_sec_resp", 1);
218 qdev_init_gpio_in_named(dev
, tz_ppc_irq_enable
, "irq_enable", 1);
219 qdev_init_gpio_in_named(dev
, tz_ppc_irq_clear
, "irq_clear", 1);
220 qdev_init_gpio_out_named(dev
, &s
->irq
, "irq", 1);
223 static void tz_ppc_realize(DeviceState
*dev
, Error
**errp
)
225 Object
*obj
= OBJECT(dev
);
226 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
227 TZPPC
*s
= TZ_PPC(dev
);
231 /* We can't create the upstream end of the port until realize,
232 * as we don't know the size of the MR used as the downstream until then.
234 for (i
= 0; i
< TZ_NUM_PORTS
; i
++) {
235 if (s
->port
[i
].downstream
) {
240 for (i
= 0; i
<= max_port
; i
++) {
241 TZPPCPort
*port
= &s
->port
[i
];
245 if (!port
->downstream
) {
247 * Create dummy sysbus MMIO region so the sysbus region
248 * numbering doesn't get out of sync with the port numbers.
249 * The size is entirely arbitrary.
251 name
= g_strdup_printf("tz-ppc-dummy-port[%d]", i
);
252 memory_region_init_io(&port
->upstream
, obj
, &tz_ppc_dummy_ops
,
253 port
, name
, 0x10000);
254 sysbus_init_mmio(sbd
, &port
->upstream
);
259 name
= g_strdup_printf("tz-ppc-port[%d]", i
);
262 address_space_init(&port
->downstream_as
, port
->downstream
, name
);
264 size
= memory_region_size(port
->downstream
);
265 memory_region_init_io(&port
->upstream
, obj
, &tz_ppc_ops
,
267 sysbus_init_mmio(sbd
, &port
->upstream
);
272 static const VMStateDescription tz_ppc_vmstate
= {
275 .minimum_version_id
= 1,
276 .fields
= (VMStateField
[]) {
277 VMSTATE_BOOL_ARRAY(cfg_nonsec
, TZPPC
, 16),
278 VMSTATE_BOOL_ARRAY(cfg_ap
, TZPPC
, 16),
279 VMSTATE_BOOL(cfg_sec_resp
, TZPPC
),
280 VMSTATE_BOOL(irq_enable
, TZPPC
),
281 VMSTATE_BOOL(irq_clear
, TZPPC
),
282 VMSTATE_BOOL(irq_status
, TZPPC
),
283 VMSTATE_END_OF_LIST()
287 #define DEFINE_PORT(N) \
288 DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \
289 TYPE_MEMORY_REGION, MemoryRegion *)
291 static Property tz_ppc_properties
[] = {
292 DEFINE_PROP_UINT32("NONSEC_MASK", TZPPC
, nonsec_mask
, 0),
309 DEFINE_PROP_END_OF_LIST(),
312 static void tz_ppc_class_init(ObjectClass
*klass
, void *data
)
314 DeviceClass
*dc
= DEVICE_CLASS(klass
);
316 dc
->realize
= tz_ppc_realize
;
317 dc
->vmsd
= &tz_ppc_vmstate
;
318 dc
->reset
= tz_ppc_reset
;
319 dc
->props
= tz_ppc_properties
;
322 static const TypeInfo tz_ppc_info
= {
324 .parent
= TYPE_SYS_BUS_DEVICE
,
325 .instance_size
= sizeof(TZPPC
),
326 .instance_init
= tz_ppc_init
,
327 .class_init
= tz_ppc_class_init
,
330 static void tz_ppc_register_types(void)
332 type_register_static(&tz_ppc_info
);
335 type_init(tz_ppc_register_types
);